854S015CKI-01LFT [IDT]
Low Skew, 1-to-5, Differential-to-LVDS/LVPECL Fanout Buffer;
| 型号： | 854S015CKI-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-5, Differential-to-LVDS/LVPECL Fanout Buffer 驱动 逻辑集成电路 |
| 文件： | 总27页 (文件大小：940K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-5,
Differential-to-LVDS/LVPECL Fanout Buffer
ICS854S015I-01
DATA SHEET
General Description
Features
The ICS854S015I-01 is a low skew, high performance 1-to-5, 2.5V,
3.3V Differential-to-LVPECL/LVDS Fanout Buffer. The
ICS854S015I-01 has two selectable differential clock inputs.
• Five differential LVPECL or LVDS output pairs
• Two differential clock input pairs
• CLK, nCLK pair can accept the following differential input levels:
Guaranteed output and part-to-part skew characteristics make the
ICS854S015I-01 ideal for those applications demanding well defined
performance and repeatability.
LVDS, LVPECL, LVHSTL, HCSL
• PCLK, nPCLK can accept the following input levels: LVPECL,
LVDS, CML
• Either CLK or PCLK inputs can be configured to accept
single-ended inputs
• Maximum output frequency: 2GHz
• Additive phase jitter, RMS: 0.065ps (maximum), 3.3V,
156.25MHz, 12kHz – 5MHz)
• Output Skew: 55ps (maximum)
• Propagation delay: 570ps (typical) @ 3.3V
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
Pulldown
nCLK_EN
D
Q
LE
Pulldown
PCLK
nPCLK
24 23 22 21 20 19
0
1
Pullup/Pulldown
PCLK
1
2
3
4
5
6
nQ1
VCC
18
Q0
nQ0
17
Pulldown
nPCLK
VCC
CLK
nCLK
Pullup/Pulldown
Q1
16 VEE
15 Q2
nQ1
VCC_TAP
CLK
Pulldown
CLK_SEL
VCC_TAP
Q2
nQ2
14
nQ2
13 Q3
nCLK
7
8
9 10 11 12
Q3
nQ3
Q4
nQ4
ICS854S015I-01
24-Lead VFQFN
Pulldown
SEL_OUT
4mm x 4mm x 0.925mm package body
K Package
Top View
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Pulldown
Description
1
PCLK
Input
Input
Non-inverting differential LVPECL clock input.
Pullup/
Pulldown
2
nPCLK
Inverting differential LVPECL clock input. VCC/2 default when left floating.
3, 9, 17
VCC
VCC_TAP
CLK
Power
Power
Input
Positive supply pins.
4
5
Power supply pin. See Table 3C.
Non-inverting differential clock input.
Pulldown
Pullup/
Pulldown
6
7
nCLK
Input
Input
Inverting differential clock input. VCC/2 default when left floating.
Output select pin. When LOW, selects LVDS output levels. When HIGH, selects
LVPECL output levels. See Table 3. LVCMOS/LVTTL interface levels.
SEL_OUT
Pulldown
8
nc
Unused
Output
Output
Output
Power
Output
Output
No-connect.
10, 11
12, 13
14, 15
16, 22
18, 19
20, 21
nQ4, Q4
nQ3, Q3
nQ2, Q2
VEE
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Negative supply pins.
nQ1, Q1
nQ0, Q0
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW, selects
PCLK, nPCLK inputs. LVTTL / LVCMOS interface levels.
23
CLK_SEL
Input
Pulldown
Pulldown
Synchronizing clock enable. When LOW, clock outputs follow clock input.
When HIGH, Qx outputs are forced low, nQx outputs are forced high.
LVTTL / LVCMOS interface levels.
24
nCLK_EN
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
2
RPULLDOWN Input Pulldown Resistor
RVCC/2 Pullup/Pulldown Resistor
50
50
kΩ
kΩ
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
nCLK_EN
CLK_SEL
Selected Source
PCLK, nPCLK
CLK, nCLK
Q[0:4]
nQ[0:4]
Enabled
0
0
1
1
0
1
0
1
Enabled
Enabled
Enabled
PCLK, nPCLK
CLK, nCLK
Disabled; Low
Disabled; Low
Disabled; High
Disabled; High
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. In the active
mode, the state of the outputs are a function of the PCLK, nPCLK and CLK, nCLK inputs as described in Table 3B.
Enabled
Disabled
nPCLK, nCLK
PCLK, CLK
nCLK_EN
nQ[0:4]
Q[0:4]
Figure 1. nCLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
PCLK or CLK
nPCLK or nCLK
Q[0:4]
nQ[0:4]
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Polarity
0
1
1
0
LOW
Non-Inverting
Non-Inverting
HIGH
Table 3C. VCC_TAP Function Table
Outputs
Table 3D. SEL_OUT Function Table
Input
SEL_OUT
0 (default)
1
Outputs
Q[0:4], nQ[0:4]
LVDS
Q[0:4], nQ[0:4]
LVPECL
LVPECL
LVDS
Output Level Supply
VCC_TAP
2.5V
3.3V
2.5V
3.3V
2.5V
3.3V
2.5V
Float
LVPECL
LVDS
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
49.5°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
85
Units
V
VCC
Positive Supply Voltage
VCC_TAP Power Supply Voltage
3.135
3.3
V
IEE
Power Supply Current
Power Supply Current
mA
mA
ITAP
5
Table 4B. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
78
Units
V
VCC
Positive Supply Voltage
VCC_TAP Power Supply Voltage
2.375
2.5
V
IEE
Power Supply Current
Power Supply Current
mA
mA
ITAP
5
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Table 4C. LVDS Power Supply DC Characteristics, VCC = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
VCC Positive Supply Voltage
ICC Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
Units
V
3.135
3.3
160
mA
NOTE: VCC_TAP is left floating for 3.3V operation.
Table 4D. LVDS Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
150
Units
V
VCC
Positive Supply Voltage
VCC_TAP Power Supply Voltage
2.375
2.5
V
ICC
Power Supply Current
Power Supply Current
mA
mA
ICC_TAP
5
Table 4E. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5% or VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VCC = 3.465V
VCC = 2.625V
Minimum
2.2
Typical
Maximum
VCC + 0.3
VCC + 0.3
0.8
Units
V
V
V
V
VIH
VIL
Input High Voltage
1.7
V
CC = 3.465V
CC = 2.625V
-0.3
Input Low Voltage
Input High Current
V
-0.3
0.7
CLK_SEL,
SEL_OUT,
nCLK_EN
IIH
VCC = VIN = 3.465V or 2.625V
150
µA
µA
CLK_SEL,
SEL_OUT,
nCLK_EN
IIL
Input Low Current
VCC = 3.465V or 2.625V, VIN = 0V
-10
Table 4F. Differential DC Characteristics, VCC = 3.3V 5% or VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
Minimum
Typical
Maximum
Units
µA
CLK, nCLK
CLK
150
V
-10
µA
IIL
Input Low Current
nCLK
VCC = 3.465V, VIN = 0V
-150
µA
Peak-to-Peak Input
Voltage
VPP
CLK, nCLK
CLK, nCLK
0.15
1.3
V
V
Common Mode Input
Voltage; NOTE 1
VCMR
VEE + 0.5
VCC – 0.85
NOTE 1. Common mode voltage is defined as VIH.
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Table 4G. LVPECL DC Characteristics, VCC = VCC_TAP = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
Minimum
Typical
Maximum
Units
µA
PCLK, nPCLK
PCLK
150
V
-10
µA
IIL
Input Low Current
nPCLK
VCC = 3.465V, VIN = 0V
-150
µA
Peak-to-Peak Input
Voltage
VPP
PCLK, nPCLK
PCLK, nPCLK
0.15
1.3
V
V
Common Mode Input
Voltage; NOTE 1
VCMR
VEE + 1.2
VCC
VOH
VOL
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
VCC – 1.4
VCC – 2.0
0.6
VCC – 0.9
VCC – 1.7
1.0
V
V
V
VSWING Peak-to-peak Output Voltage Swing
NOTE 1. Common mode voltage is defined as VIH.
NOTE 2: Outputs terminated with 50Ω to VCC – 2V.
Table 4H. LVPECL DC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum
Units
µA
PCLK, nPCLK
PCLK
VCC = VIN = 2.625V
CC = 2.625V, VIN = 0V
CC = 2.625V, VIN = 0V
150
V
V
-10
µA
IIL
Input Low Current
nPCLK
-150
µA
Peak-to-Peak Input
Voltage
VPP
PCLK, nPCLK
PCLK, nPCLK
0.15
1.3
V
V
Common Mode Input
Voltage; NOTE 1
VCMR
V
EE + 1.2
VCC
VOH
VOL
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
VCC – 1.4
VCC – 2.0
0.4
VCC – 0.9
VCC – 1.5
1.0
V
V
V
VSWING Peak-to-peak Output Voltage Swing
NOTE 1. Common mode voltage is defined as VIH.
NOTE 2: Outputs terminated with 50Ω to VCC – 2V.
Table 4I. LVDS DC Characteristics, VCC = 3.3V 5%, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
Minimum
Typical
Maximum
454
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
∆VOD
VOS
50
1.125
1.375
50
∆VOS
VOS Magnitude Change
mV
Table 4J. LVDS DC Characteristics, VCC = VCC_TAP = 2.5V 5%,TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
Minimum
Typical
Maximum
454
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
∆VOD
VOS
50
1.105
1.375
50
∆VOS
VOS Magnitude Change
mV
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
AC Electrical Characteristics
Table 5A. LVPECL AC Characteristics, VCC = VCC_TAP = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
2
GHz
Propagation Delay, Low-to-High;
NOTE 1
tPD
300
800
ps
tsk(o)
Output Skew; NOTE 2, 3
55
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
250
156.25MHz, Integration Range:
12kHz - 5MHz
0.046
0.083
0.034
0.068
0.065
0.120
0.059
0.094
ps
ps
ps
ps
156.25MHz, Integration Range:
12kHz - 20MHz
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tjit
245.76MHz, Integration Range:
12kHz - 5MHz
245.76MHz, Integration Range:
12kHz - 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
80
45
220
55
ps
%
MUXISOLATION MUX Isolation
@ 100MHz
85
dB
All parameters measured at fOUT ≤ 1GHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Table 5B. LVPECL AC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
2
GHz
Propagation Delay, Low-to-High;
NOTE 1
tPD
300
800
ps
tsk(o)
Output Skew; NOTE 2, 3
55
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
250
156.25MHz, Integration Range:
12kHz - 5MHz
0.054
0.097
0.050
0.099
0.079
0.134
0.067
0.131
ps
ps
ps
ps
156.25MHz, Integration Range:
12kHz - 20MHz
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tjit
245.76MHz, Integration Range:
12kHz - 5MHz
245.76MHz, Integration Range:
12kHz - 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
80
45
210
55
ps
%
MUXISOLATION MUX Isolation
@ 100MHz
85
dB
For NOTES, see Table 5A above.
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Table 5C. LVDS AC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
2
GHz
Propagation Delay, Low-to-High;
NOTE 1
tPD
300
800
ps
tsk(o)
Output Skew; NOTE 2, 3
55
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
250
156.25MHz, Integration Range:
12kHz - 5MHz
0.048
0.096
0.035
0.074
0.074
0.146
0.054
0.097
ps
ps
ps
ps
156.25MHz, Integration Range:
12kHz - 20MHz
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tjit
245.76MHz, Integration Range:
12kHz - 5MHz
245.76MHz, Integration Range:
12kHz - 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
80
45
200
55
ps
%
MUXISOLATION MUX Isolation
@ 100MHz
85
dB
All parameters measured at fOUT ≤ 1GHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Table 5D. LVDS AC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
2
GHz
Propagation Delay, Low-to-High;
NOTE 1
tPD
300
800
ps
tsk(o)
Output Skew; NOTE 2, 3
55
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
250
156.25MHz, Integration Range:
12kHz - 5MHz
0.049
0.098
0.037
0.076
0.074
0.139
0.060
0.102
ps
ps
ps
ps
156.25MHz, Integration Range:
12kHz - 20MHz
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tjit
245.76MHz, Integration Range:
12kHz - 5MHz
245.76MHz, Integration Range:
12kHz - 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
80
45
200
55
ps
%
MUXISOLATION MUX Isolation
@ 100MHz
85
dB
For NOTES, see Table 5C above.
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @
156.25MHz, 12kHz to 20MHz = 0.08ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator used is, “Rhode & Schwarz SMA 100A Signal
Generator, via the clock synthesis as the external input to drive the
input clock.”
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Parameter Measurement Information
2V
2V
SCOPE
SCOPE
V
V
Qx
CC,
V
V
CC,
Qx
CC_TAP
CC_TAP
nQx
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V LVPECL Output Load AC Test Circuit
2.5V LVPECL Output Load AC Test Circuit
Float
SCOPE
SCOPE
Qx
Qx
V
V
CC,
V
CC
2.5V 5%
POWER SUPPLY
3.3V 5%
CC_TAP
POWER SUPPLY
V
+
Float GND –
CC_TAP
+
Float GND –
LVDS
nQx
nQx
3.3V LVDS Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
V
CC
nQx
Qx
nPCLK, nCLK
VPP
VCMR
Cross Points
nQy
PCLK, CLK
Qy
tsk(o)
V
EE
Differential Input Level
Output Skew
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Parameter Measurement Information, continued
nPCLK,
nCLK
Part 1
Part 2
nQx
Qx
nQx
Qx
PCLK,
CLK
nQ[0:4]
Q[0:4]
tPD
tsk(pp)
Propagation Delay
Part-to-Part Skew
nQ[0:4]
nQ[0:4]
80%
tF
80%
tR
80%
tF
80%
tR
VSWING
20%
VOD
20%
20%
20%
Q[0:4]
Q[0:4]
LVPECL Output Rise/Fall Time
LVDS Output Rise/Fall Time
Spectrum of Output Signal Q
MUX selects active
input clock signal
A0
A1
nQ[0:4]
Q[0:4]
tPW
MUX_ISOL = A0 – A1
tPERIOD
MUX selects static input
tPW
odc =
x 100%
tPERIOD
ƒ
Frequency
(fundamental)
Output Duty Cycle/Pulse Width/Period
MUX Isolation
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/∆ VOD
out
➤
VOS/∆ VOS
➤
Differential Output Voltage Setup
Offset Voltage Setup
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
11
©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
PCLK/nPCLK Inputs
LVPECL Outputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVDS Outputs
CLK/nCLK Inputs
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, there should be no trace
attached.
For applications not requiring the use of a differential input, both the
CLK and nCLK pins can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011 12 ©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
3.3V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, LVDS and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
R1
R2
50Ω
50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100Ω
nPCLK
nPCLK
Zo = 50Ω
LVPECL
Input
LVPECL
CML
CML Built-In Pullup
Input
Figure 3A. PCLK/nPCLK Input Driven by an
Open Collector CML Driver
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
3.3V
R3
84
R4
84
Zo = 50Ω
Zo = 50Ω
C1
C2
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL
PCLK
PCLK
nPCLK
nPCLK
LVPECL
Input
LVPECL
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84Ω
R2
84Ω
Figure 3C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
3.3V
Zo = 50Ω
PCLK
R1
100Ω
nPCLK
Zo = 50Ω
LVPECL
Input
LVDS
Figure 3E. PCLK/nPCLK Input Driven by a LVDS Driver
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, LVDS and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 4A to 4E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
2.5V
2.5V
2.5V
2.5V
2.5V
R1
50Ω
R2
50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100Ω
nPCLK
Zo = 50Ω
LVPECL
Input
CML Built-In Pullup
nPCLK
LVPECL
Input
CML
Figure 4B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 4A. PCLK/nPCLK Input Driven by an
Open Collector CML Driver
2.5V
2.5V
2.5V
3.3V
2.5V
R3
R4
R1
100
R3
100Ω
Ω
250Ω
250Ω
C1
C2
Zo = 50
Ω
Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
nPCLK
Zo = 50
nPCLK
LVPECL
Input
LVPECL
3.3V LVPECL Driver
R1
R2
R6
100Ω-180Ω
62.5Ω
62.5Ω
R7
100
R2
100
R4
100
Ω-180Ω
Ω
Ω
Figure 4C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 4D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
2.5V
2.5V
Zo = 50Ω
PCLK
R1
100Ω
nPCLK
Zo = 50Ω
LVPECL
Input
LVDS
Figure 4E. PCLK/nPCLK Input Driven by a LVDS Driver
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 5A to 5E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 5A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
nCLK
LVPECL
Differential
Input
R1
50Ω
R2
50Ω
LVHSTL
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
R2
50Ω
Figure 5A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 5B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
R4
3.3V
125Ω
125Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
nCLK
Differential
Input
Zo = 50Ω
LVPECL
Receiver
R1
84Ω
R2
84Ω
LVDS
Figure 5C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 5D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
3.3V
3.3V
Zo = 50Ω
*R3
*R4
33Ω
33Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
HCSL
R1
50Ω
R2
50Ω
*Optional – R3 and R4 can be 0Ω
Figure 5E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
2.5V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 6A to 6E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 6A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
2.5V
2.5V
2.5V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
nCLK
LVPECL
R1
50Ω
R2
50Ω
Differential
Input
LVHSTL
R1
50Ω
R2
50Ω
IDT Open Emitter
LVHSTL Driver
R3
18Ω
Figure 6A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 6B. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
2.5V
2.5V
2.5V
2.5V
R3
250Ω
R4
250Ω
2.5V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Differential
Input
LVDS
R1
62.5Ω
R2
62.5Ω
Figure 6C. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 6D. CLK/nCLK Input Driven by a 2.5V LVDS Driver
2.5V
2.5V
Zo = 50Ω
*R3
*R4
33Ω
33Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
HCSL
R1
50Ω
R2
50Ω
*Optional – R3 and R4 can be 0Ω
Figure 6E. CLK/nCLK Input Driven by a
2.5V HCSL Driver
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90Ω and 132Ω. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100Ω parallel resistor at the receiver and a 100Ω differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 7A can be used
with either type of output structure. Figure 7B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO • ZT
LVDS
Driver
LVDS
Receiver
ZT
Figure 7A. Standard Termination
ZT
ZO • ZT
LVDS
Driver
2
ZT
2
LVDS
Receiver
C
Figure 7B. Optional Termination
LVDS Termination
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 8A and 8B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
3.3V
R3
R4
3.3V
125Ω
125Ω
3.3V
Z
o = 50Ω
3.3V
+
_
Z
o = 50Ω
+
_
Input
LVPECL
Zo = 50Ω
LVPECL
Input
R1
50Ω
R2
50Ω
Zo = 50Ω
R1
84Ω
R2
84Ω
VCC - 2V
1
RTT =
* Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
Figure 8A. 3.3V LVPECL Output Termination
Figure 8B. 3.3V LVPECL Output Termination
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Termination for 2.5V LVPECL Outputs
Figure 9A and Figure 9B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 9B can be eliminated and the termination is
shown in Figure 9C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
R3
50Ω
250Ω
250Ω
+
50Ω
50Ω
+
–
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
2.5V LVPECL Driver
R2
R4
62.5Ω
62.5Ω
R3
18Ω
Figure 9A. 2.5V LVPECL Driver Termination Example
Figure 9B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
Figure 9C. 2.5V LVPECL Driver Termination Example
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 10. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 10. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
LVPECL Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S015I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S015I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 85mA = 294.53mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30mW = 150mW
Total Power_MAX (3.3V, with all outputs switching) = 294.53mW +150mW = 444.55mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.445W * 49.5°C/W = 107°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 24 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
49.5°C/W
43.3°C/W
38.8°C/W
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 11.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 11. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S015I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S015I-01 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 150mA = 519.75mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.520W * 49.5°C/W = 110.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 24 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
49.5°C/W
43.3°C/W
38.8°C/W
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 24 Lead VFQFN
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
49.5°C/W
43.3°C/W
38.8°C/W
Transistor Count
The transistor count for ICS854S015I-01 is: 521
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
24
©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Package Outline and Package Dimensions
Package Outline - K Suffix for 24 Lead VFQFN
(Ref.)
N & N
Even
Seating Plane
(N -1)x e
(Ref.)
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
1
Singulation
2
or
(N -1)x e
(Ref.)
Sawn
E2
2
Singulation
TopView
D
b
(Ref.)e
N &N
Odd
Thermal
Base
A
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
Bottom View w/Type A ID
Bottom View w/Type C ID
2
1
2
1
CHAMFER
RADIUS
N N-1
N N-1
4
4
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
NOTE: The following package mechanical drawing is a generic
Table 9. K Package Dimensions for 24 Lead VFQFN
All Dimensions in Millimeters
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
Symbol
Minimum
Maximum
N
A
24
0.80
0
1.0
A1
0.05
A3
0.25 Reference
0.18 0.30
b
e
0.50 Basic
4
D, E
D2, E2
L
2.30
0.30
2.55
0.50
ND NE
6
Reference Document: JEDEC Publication 95, MO-220
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
25
©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Ordering Information
Table 10. Ordering Information
Part/Order Number
854S015CKI-01LF
854S015CKI-01LFT
Marking
15CI01L
15CI01L
Package
“Lead-Free” 24 Lead VFQFN
“Lead-Free” 24 Lead VFQFN
Shipping Packaging
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
26
©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
We’ve Got Your Timing Solution
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2011. All rights reserved.
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