8543AG-09LFT [IDT]
Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer;
| 型号： | 8543AG-09LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总17页 (文件大小：996K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-4, Differential-to-
LVDS Fanout Buffer
ICS8543-09
DATA SHEET
General Description
Features
The ICS8543-09 is a low skew, high performance
1-to-4 Differential-to-LVDS Clock Fanout Buffer.
Utilizing Low Voltage Differential Signaling (LVDS) the
ICS8543-09 provides a low power, low noise, solution
for distributing clock signals over controlled
• Four differential LVDS output pairs
• Selectable differential CLK, nCLK or LVPECL clock inputs
S
IC
HiPerClockS™
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
impedances of 100Ω. The ICS8543-09 has two selectable clock
inputs. The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
LVPECL, CML, SSTL
• Maximum output frequency: 800MHz
• Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
• Additive phase jitter, RMS: 0.146ps (typical)
• Output skew: 100ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Propagation delay: 3.3ns (maximum)
• Full 3.3V supply mode
Guaranteed output and part-to-part skew characteristics make the
ICS8543-09 ideal for those applications demanding well defined
performance and repeatability.
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Industrial temperature information available upon request
Pin Assignment
Block Diagram
GND
CLK_EN
CLK_SEL
CLK
1
2
20 Q0
Pullup
CLK_EN
D
19
nQ0
Q
3
4
18
17
VDD
Q1
LE
Pulldown
Pullup
CLK
nCLK
Q0
0
nCLK
PCLK
nPCLK
5
6
7
8
9
16 nQ1
nQ0
15
14
13
Q2
Pulldown
Pullup
PCLK
nPCLK
1
nQ2
GND
Q1
OE
nQ1
GND
12 Q3
11
nQ3
Pulldown
CLK_SEL
VDD 10
Q2
nQ2
ICS8543-09
Q3
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
nQ3
Pullup
OE
G Package
Top View
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 9, 13
GND
Power
Input
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Clock select input. When HIGH, selects PCLK/nPCLK inputs.
When LOW, selects CLK/nCLK input. LVCMOS / LVTTL interface levels.
3
4
CLK_SEL
CLK
Input
Input
Pulldown
Pulldown
Non-inverting differential clock input.
5
6
7
Input
Input
Input
Pullup
Pulldown
Pullup
Inverting differential clock input.
nCLK
PCLK
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
nPCLK
OE
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
8
Input
Pullup
10, 18
11, 12
14, 15
16, 17
19, 20
VDD
Power
Output
Output
Output
Output
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
kΩ
kΩ
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
OE
0
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
nQ0:nQ3
Hi-Impedance
Disabled, High
Disabled, High
Enabled
X
0
0
1
1
X
0
1
0
1
Hi-Impedance
Disabled, Low
Disabled, Low
Enabled
1
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
1
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
nQ0:nQ3
Input to Output Mode
Polarity
CLK or PCLK
nCLK or nPCLK
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
0
1
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
1
0
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
91.1°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum
3.465
50
Units
V
Positive Supply Voltage
Power Supply Current
3.135
3.3
IDD
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
Input High Voltage
Input Low Voltage
2
VDD + 0.3
VIL
-0.3
0.8
150
5
V
CLK_SEL
V
DD = VIN = 3.465V
µA
µA
µA
µA
IIH
Input High Current
Input Low Current
OE, CLK_EN
CLK_SEL
VDD = VIN = 3.465V
V
DD = 3.465V, VIN = 0V
-5
IIL
OE, CLK_EN
VDD = 3.465V, VIN = 0V
-150
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
CLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
IIH Input High Current
nCLK
CLK
V
-5
IIL
Input Low Current
nCLK
VDD = 3.465V, VIN = 0V
-150
0.15
0.5
VPP
Peak-to-Peak Input Voltage; NOTE 1
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
PCLK
V
DD = VIN = 3.465V
150
5
IIH
Input High Current
nPCLK
PCLK
VDD = VIN = 3.465V
V
DD = 3.465V, VIN = 0V
-5
-150
0.3
IIL
Input Low Current
nPCLK
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage; NOTE 1
1.0
VCMR
Common Mode Input Voltage; NOTE 1, 2
1.5
VDD
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4E. LVDS DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
360
40
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
200
280
∆VOD
VOS
1.125
1.25
5
1.375
25
∆VOS
IOz
VOS Magnitude Change
High Impedance Leakage
Power Off Leakage
mV
µA
-10
-20
+10
+20
-5
IOFF
1
µA
IOSD
IOS
Differential Output Short Circuit Current
Output Short Circuit Current
-3.5
-3.5
mA
mA
-5
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum
800
Units
MHz
ns
Output Frequency
Propagation Delay; NOTE 1
tPD
IJ 800MHz
1
2.15
3.3
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
156.25MHz,
Integration Range: 12kHz – 20MHz
tjit(Ø)
0.146
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
100
700
350
55
ps
ps
ps
%
20% to 80% @ 50MHz
150
45
50
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential output crossing points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHz
12kHz to 20MHz = 0.146ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information
V
DD
SCOPE
Qx
V
nQ0:nQ3
Q0:Q3
DD
3.3V 5%
POWER SUPPLY
V
V
Cross Points
PP
CMR
+
Float GND –
LVDS
nQx
GND
3.3V LVDS Output Load AC Test Circuit
Differential Output Level
V
DD
nQx
Qx
nCLK, nPCLK
V
Cross Points
nQy
OD
CLK, PCLK
GND
Qy
V
OS
tsk(o)
Differential Input Level
Output Skew
Part 1
nQx
nCLK, nPCLK
CLK, PCLK
Qx
Part 2
nQy
nQ0:nQ3
Qy
Q0:Q3
tPD
tsk(pp)
Part-to-Part Skew
Propagation Delay
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information, continued
nQ0:nQ3
Q0:Q3
nQ0:nQ3
Q0:Q3
80%
80%
VOD
20%
tPW
tPERIOD
20%
tF
tR
tPW
odc =
x 100%
tPERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
100
V
OD/∆ VOD
DC Input
out
➤
VOS/∆ VOS
➤
Offset Voltage Setup
Differential Output Voltage Setup
out
IOZ
3.3V 5% POWER SUPPLY
Float GND
+
DC Inpu
t
LVDS
_
LVDS
VDD
out
IOFF
IOZ
High Impedance Leakage Current Setup
Power Off Leakage Setup
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information, continued
VDD
VDD
out
IOS
out
DC Input
LVDS
IOSD
DC Input
LVDS
IOSB
out
out
Differential Output Short Circuit Setup
Output Short Circuit Current Setup
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =
VDD
R1
1K
CLK_IN
0.609.
+
-
V_REF
C1
0.1uF
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both differential signals must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100
nPCLK
Zo = 50Ω
nPCLK
LVPECL
LVPECL
Input
CML
CML Built-In Pullup
Input
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
R3
84
R4
84
Zo = 50Ω
Zo = 50Ω
C1
C2
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL
PCLK
PCLK
nPCLK
nPCLK
LVPECL
Input
LVPECL
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
Figure 3C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
2.5V
3.3V
2.5V
R3
120
R4
120
Zo = 60Ω
Zo = 60Ω
PCLK
nPCLK
LVPECL
Input
SSTL
R1
120
R2
120
Figure 3E. PCLK/nPCLK Input Driven by an SSTL Driver
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both differential signals must meet the VPP
and VCMR input requirements. Figures 4A to 4F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 4A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
nCLK
LVPECL
Input
R1
50
R2
50
Differential
LVHSTL
Input
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
Figure 4B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 4A. CLK/nCLK Input Driven by an IDT Open
Emitter HiPerClockS LVHSTL Driver
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
R1
84
R2
84
Figure 4D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
Figure 4C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
2.5V
2.5V
3.3V
3.3V
2.5V
R3
120
R4
120
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
Differential
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 4E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 4F. CLK/nCLK Input Driven by a 2.5V SSTL Driver
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ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVDS Outputs
For applications not requiring the use of the differential input, both
CLK and PCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, there should be no trace
attached.
PCLK/nPCLK Inputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 5. In a 100Ω differential
transmission line environment, LVDS drivers require a matched load
termination of 100Ω across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 5. Typical LVDS Driver Termination
ICS8543AG-09 REVISION A JANUARY 15, 2010
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©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8543-09.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8543-09 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.173W * 91.1°C/W = 85.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
91.1°C/W
86.7°C/W
84.6°C/W
ICS8543AG-09 REVISION A JANUARY 15, 2010
14
©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
91.1°C/W
86.7°C/W
84.6°C/W
Transistor Count
The transistor count for ICS8543-09 is: 636
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS8543AG-09 REVISION A JANUARY 15, 2010
15
©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number
8543AG-09LF
Marking
Package
Shipping Packaging
Tube
Temperature
0°C to 70°C
0°C to 70°C
ICS8543AG09L
ICS8543AG09L
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
8543AG-09LFT
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
ICS8543AG-09 REVISION A JANUARY 15, 2010
16
©2010 Integrated Device Technology, Inc.
ICS8543-09 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
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www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
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