8543BGILFT [RENESAS]
Low Skew Clock Driver, 8543 Series, 8 True Output(s), 0 Inverted Output(s), PDSO20;
| 型号： | 8543BGILFT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Low Skew Clock Driver, 8543 Series, 8 True Output(s), 0 Inverted Output(s), PDSO20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总18页 (文件大小：781K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8543I
Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
DATA SHEET
General Description
Features
The ICS8543I is a low skew, high performance 1-to-4 Differen-
tial-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential
Signaling (LVDS) the ICS8543I provides a low power, low noise, so-
lution for distributing clock signals over controlled impedances of
100. The ICS8543I has two selectable clock inputs. The CLK,
nCLK pair can accept most standard differential input levels. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt pulses
on the outputs during asynchronous assertion/deassertion of the
clock enable pin.
• Four differential LVDS output pairs
• Selectable differential CLK/nCLK or LVPECL clock inputs
• CLK/nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK/nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
• Additive phase Jitter, RMS: 0.164ps (typical)
• Output skew: 40ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Propagation delay: 2.6ns (maximum)
• Full 3.3Vsupply mode
Guaranteed output and part-to-part skew characteristics make the
ICS8543I ideal for those applications demanding well defined perfor-
mance and repeatability.
• -40°C to 85°C ambient operating temperature
• Available in lead-free packages
Block Diagram
Pin Assignment
Pullup
GND
CLK_EN
CLK_SEL
CLK
1
2
20 Q0
CLK_EN
D
19
nQ0
Q
3
4
18
17
VDD
Q1
LE
Pulldown
Pullup
CLK
nCLK
nCLK
PCLK
nPCLK
5
6
7
8
9
16 nQ1
0
Q0
15
14
13
Q2
nQ2
GND
nQ0
Pulldown
Pullup
PCLK
nPCLK
OE
1
Q1
GND
VDD 10
12 Q3
11
nQ3
nQ1
Pulldown
CLK_SEL
Q2
ICS8543I
nQ2
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
Q3
nQ3
Pullup
OE
G Package
Top View
ICS8543BGI REVISION E NOVEMBER 15, 2012
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 9, 13
GND
Power
Input
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Clock select input. When HIGH, selects PCLK/nPCLK inputs.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
3
4
CLK_SEL
CLK
Input
Input
Pulldown
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential LVPECL clock input.
5
6
7
nCLK
PCLK
nPCLK
Input
Input
Input
Pullup
Inverting differential LVPECL clock input.
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
8
OE
Input
Pullup
10, 18
11, 12
14, 15
16, 17
19, 20
VDD
Power
Output
Output
Output
Output
Positive supply pins.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
k
k
ICS8543BGI REVISION E NOVEMBER 15, 2012
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
OE
0
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
Hi-Z
nQ0:nQ3
Hi-Z
X
0
0
1
1
X
0
1
0
1
1
CLK/nCLK
PCLK/nPCLK
CLK/nCLK
Disabled; Low
Disabled; Low
Enabled
Disabled; High
Disabled; High
Enabled
1
1
1
PCLK/nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK or PCLK
nCLK or nPCLK
Q[0:3]
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ[0:3]
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
0
1
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
ICS8543BGI REVISION E NOVEMBER 15, 2012
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
73.2C/W (0 lfpm)
-65C to 150C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
VDD Positive Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
50
Units
V
3.135
3.3
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
VIH
VIL
Input High Voltage
2
VDD + 0.3
Input Low Voltage
-0.3
0.8
5
V
OE, CLK_EN
CLK_SEL
VDD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
µA
µA
µA
µA
IIH
Input High Current
150
OE, CLK_EN
CLK_SEL
V
V
-150
-5
IIL
Input Low Current
Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
CLK
VDD = VIN = 3.465V
150
5
IIH Input High Current
nCLK
CLK
VDD = VIN = 3.465V
V
DD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
nCLK
VDD = 3.465V, VIN = 0V
-150
0.15
VPP
Peak-to-Peak Voltage; NOTE 1
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
ICS8543BGI REVISION E NOVEMBER 15, 2012
Table 4D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
PCLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
IIH
Input High Current
nPCLK
PCLK
V
-5
IIL
Input Low Current
nPCLK
VDD = 3.465V, VIN = 0V
-150
0.3
VPP
Peak-to-Peak Voltage; NOTE 1
1
Common Mode Input Voltage;
NOTE 1, 2
VCMR
1.5
VDD
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4E. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
280
0
Maximum
360
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
200
VOD
VOS
40
1.125
1.25
5
1.375
25
VOS
IOz
VOS Magnitude Change
High Impedance Leakage
Power Off Leakage
mV
µA
-10
-20
+10
IOFF
±1
+20
µA
Differential Output Short Circuit
Current
IOSD
-3.5
-5
mA
IOS
Output Short Circuit Current
Output Voltage High
-3.5
1.34
1.06
-5
mA
V
VOH
VOL
1.6
Output Voltage Low
0.9
V
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Maximum Output Frequency
650
MHz
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
153.6MHz, Integration
Range: 12kHz – 20MHz
tjit
0.164
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
ƒ 650MHz
1.5
2.6
40
ns
ps
ps
ps
%
tsk(o)
tsk(pp)
tR / tF
odc
600
450
55
20% to 80% @ 50MHz
150
45
Output Duty Cycle
odc
50
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential output crosspoints.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS8543BGI REVISION E NOVEMBER 15, 2012
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 153.6MHz
12kHz to 20MHz = 0.164ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
ICS8543BGI REVISION E NOVEMBER 15, 2012
Parameter Measurement Information
V
DD
SCOPE
Qx
V
nCLK,
nPCLK
DD
3.3V±5%
POWER SUPPLY
VPP
VCMR
Cross Points
+
Float GND –
CLK,
PCLK
nQx
GND
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
V
DD
nQx
Qx
nQ[0:3]
VOD
Cross Points
nQy
Q[0:3]
GND
Qy
VOS
tsk(o)
Differential Output Level
Output Skew
nCLK,
nPCLK
Part 1
nQx
CLK,
Qx
PCLK
Part 2
nQ[0:3]
nQy
Q[0:3]
Qy
tPD
tsk(pp)
Part-to-Part Skew
Propagation Delay
ICS8543BGI REVISION E NOVEMBER 15, 2012
Parameter Measurement Information, continued
nQ[0:3]
Q[0:3]
nQ[0:3]
80%
80%
tR
tPW
VOD
20%
tPERIOD
20%
Q[0:3]
tPW
tF
odc =
x 100%
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
VDD
VDD
out
out
out
out
DC Input
LVDS
DC Input
100
LVDS
VOS/Δ VOS
ä
Offset Voltage Setup
Differential Output Voltage Setup
VDD
out
out
out
IOZ
3.3V±5% POWER SUPPLY
Float GND
+
DC Inpu
t
LVDS
_
IOSD
DC Input
LVDS
IOZ
out
High Impedance Leakage Current Setup
Differential Output Short Circuit Setup
ICS8543BGI REVISION E NOVEMBER 15, 2012
8
©2012 Integrated Device Technology, Inc.
Parameter Measurement Information, continued
VDD
out
IOS
DC Input
LVDS
LVDS
VDD
IOSB
out
IOFF
Output Short Circuit Current Setup
Power Off Leakage Setup
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS8543BGI REVISION E NOVEMBER 15, 2012
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the VPP and VCMR
input requirements. Figures 3A to 3F show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 3A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
Zo = 50Ω
nCLK
Differential
Input
nCLK
LVPECL
Differential
R1
R2
LVHSTL
50Ω
50Ω
Input
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
R2
50Ω
Figure 3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
R1
R2
84Ω
84Ω
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
Zo = 50Ω
*R3
*R4
33Ω
33Ω
Zo = 60Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
Differential
Input
SSTL
HCSL
R1
50Ω
R2
50Ω
R1
120Ω
R2
120Ω
*Optional – R3 and R4 can be 0Ω
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 3F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
ICS8543BGI REVISION E NOVEMBER 15, 2012
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 4A to 4F show interface examples for the S
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
R1
R2
50Ω
50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100Ω
nPCLK
Zo = 50Ω
nPCLK
LVPECL
CML Built-In Pullup
Input
LVPECL
Input
CML
Figure 4A. PCLK/nPCLK Input Driven by a
CML Driver
Figure 4B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
3.3V
R3
84
R4
84
Zo = 50Ω
Zo = 50Ω
C1
C2
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL
PCLK
PCLK
nPCLK
nPCLK
LVPECL
Input
LVPECL
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84Ω
R2
84Ω
Figure 4C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 4D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
2.5V
3.3V
3.3V
2.5V
R3
120
R4
120
3.3V
Zo = 50Ω
Zo = 60Ω
Zo = 60Ω
PCLK
PCLK
R1
100Ω
nPCLK
nPCLK
LVPECL
Input
Zo = 50Ω
SSTL
LVPECL
Input
R1
120
R2
120
LVDS
Figure 4E. PCLK/nPCLK Input Driven by an
SSTL Driver
Figure 4F. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
ICS8543BGI REVISION E NOVEMBER 15, 2012
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVDS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from PCLK to
ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 5A can be used
with either type of output structure. Figure 5B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
LVDS
Receiver
LVDS
Driver
ZT
Figure 5A. Standard Termination
ZT
ZO ZT
LVDS
Driver
2
ZT
2
LVDS
Receiver
C
Figure 5B. Optional Termination
LVDS Termination
ICS8543BGI REVISION E NOVEMBER 15, 2012
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8543I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8543I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.173W * 73.2°C/W = 97.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6. Thermal Resitance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
ICS8543BGI REVISION E NOVEMBER 15, 2012
Reliability Information
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
Transistor Count
The transistor count for ICS8543I is: 636
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
0.65 Basic
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS8543BGI REVISION E NOVEMBER 15, 2012
14
©2012 Integrated Device Technology, Inc.
Ordering Information
Table 9. Ordering Information
Part/Order Number
8543BGILF
8543BGILFT
Marking
ICS8543BGILF
ICS8543BGILF
Package
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
Shipping Packaging
Tube
Temperature
-40C to 85C
-40C to 85C
Tape & Reel
NOTE: "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS8543BGI REVISION E NOVEMBER 15, 2012
Revision History Sheet
Rev
A
Table
Page
Description of Change
Date
3
3
Updated Figure 1, CLK_EN Timing Diagram.
Updated Figure 1, CLK_EN Timing Diagram.
10/17/01
11/2/01
A
1
Features section, Bullet 6 to read 3.3V LVDS levels instead of LVPECL.
Updated Parameter Measurement Information figures.
A
B
5/6/02
6 - 10
1
Features - deleted bullet "Designed to meet or exceed the requirements of
ANSI TIA/EIA-644".
9/19/02
4E
T2
5
LVDS Table - changed VOD typical value from 350mV to 280mV.
2
4
Pin Characteristics - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - changed Output rating.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Added LVDS Driver Termination section.
9
C
1/5/04
10
11
Updated format throughout data sheet.
1
3
4
Features section - added lead-free bullet.
Updated Figure 1, CLK_EN Timing Diagram.
T4B
LVCMOS DC Characteristics Table - corrected typo in VIH max. from
VDD - 0.3V to VDD + 0.3V.
Updated Differential Clock Input Interface section.
10
11
12
13
15
D
2/27/08
Updated LVPECL Clock Input Interface section.
Added Recommendation for Unused Input and Output Pins section.
Added Power Considerations section.
Ordering Information Table - added lead-free Part/Order Number, Marking and note.
Updated format throughout the datasheet.
T9
T5
1
6
7
9
Features Section - added Additive Phase Jitter bullet.
AC Characteristics Table - added Additive Phase Jitter spec.
Added Additive Phase Jitter Plot.
E
9/9/08
Parameter Measurement Information - updated Output Rise/Fall Time diagram.
All
Updated format throughout the datasheet.
1, 10, 11 Deleted HiPerClockS references throughout.
E
E
11
12
15
Updated figure 4D.
10/8/12
Updated LVDS Driver Termination section.
Deleted quantity from Tape & Reel.
T9
T9
15
Removed leaded orderable parts from the Ordering Information table
11/15/12
ICS8543BGI REVISION E NOVEMBER 15, 2012
16
©2012 Integrated Device Technology, Inc.
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