8543BGI [IDT]
Low Skew Clock Driver, 8543 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 X 6.50 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | 8543BGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 8543 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 X 6.50 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20 光电二极管 |
| 文件： | 总18页 (文件大小：855K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS
FANOUT BUFFER
ICS8543I
General Description
Features
The ICS8543I is a low skew, high performance
• Four differential LVDS output pairs
S
IC
1-to-4 Differential-to-LVDS Clock Fanout Buffer and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. Utilizing Low
Voltage Differential Signaling (LVDS) the ICS8543I
• Selectable differential CLK/nCLK or LVPECL clock inputs
HiPerClockS™
• CLK/nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK/nPCLK pair can accept the following differential input
provides a low power, low noise, solution for distributing clock
signals over controlled impedances of 100Ω. The ICS8543I has
two selectable clock inputs. The CLK, nCLK pair can accept most
standard differential input levels. The PCLK, nPCLK pair can
accept LVPECL, CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin.
levels: LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
• Additive phase Jitter, RMS: 0.164ps (typical)
• Output skew: 40ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Propagation delay: 2.6ns (maximum)
• Full 3.3Vsupply mode
Guaranteed output and part-to-part skew characteristics make the
ICS8543I ideal for those applications demanding well defined
performance and repeatability.
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
GND
CLK_EN
CLK_SEL
CLK
1
2
20 Q0
Pullup
CLK_EN
D
19
nQ0
Q
3
4
18
17
VDD
Q1
LE
Pulldown
Pullup
CLK
nCLK
0
nCLK
PCLK
nPCLK
5
6
7
8
9
16 nQ1
Q0
15
14
13
Q2
nQ2
GND
nQ0
Pulldown
Pullup
PCLK
nPCLK
1
Q1
nQ1
OE
GND
VDD 10
12 Q3
11
nQ3
Pulldown
CLK_SEL
Q2
nQ2
ICS8543I
Q3
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
nQ3
Pullup
OE
G Package
Top View
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Table 1. Pin Descriptions
Number
Name
Type
Description
1, 9, 13
GND
Power
Input
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Clock select input. When HIGH, selects PCLK/nPCLK inputs.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
3
4
CLK_SEL
CLK
Input
Input
Pulldown
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential LVPECL clock input.
5
6
7
nCLK
PCLK
nPCLK
Input
Input
Input
Pullup
Inverting differential LVPECL clock input.
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
8
OE
Input
Pullup
10, 18
11, 12
14, 15
16, 17
19, 20
VDD
Power
Output
Output
Output
Output
Positive supply pins.
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
kΩ
kΩ
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Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
OE
0
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
Hi-Z
nQ0:nQ3
Hi-Z
X
0
0
1
1
X
0
1
0
1
1
CLK/nCLK
PCLK/nPCLK
CLK/nCLK
Disabled; Low
Disabled; Low
Enabled
Disabled; High
Disabled; High
Enabled
1
1
1
PCLK/nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK or PCLK
nCLK or nPCLK
Q[0:3]
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ[0:3]
HIGH
LOW
Input to Output Mode
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
0
1
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
VDD Positive Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
50
Units
V
3.135
3.3
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
VIH
VIL
Input High Voltage
2
VDD + 0.3
Input Low Voltage
-0.3
0.8
5
V
OE, CLK_EN
CLK_SEL
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
µA
µA
µA
µA
IIH
Input High Current
150
OE, CLK_EN
CLK_SEL
V
-150
-5
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
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Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
CLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
IIH Input High Current
nCLK
CLK
V
-5
IIL
Input Low Current
nCLK
VDD = 3.465V, VIN = 0V
-150
0.15
VPP
Peak-to-Peak Voltage; NOTE 1
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
PCLK
150
5
IIH Input High Current
nPCLK
PCLK
V
V
-5
IIL
Input Low Current
nPCLK
-150
0.3
VPP
Peak-to-Peak Voltage; NOTE 1
1
Common Mode Input Voltage;
NOTE 1, 2
VCMR
1.5
VDD
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4E. LVDS DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
200
280
0
360
40
∆VOD
VOS
1.125
1.25
5
1.375
25
∆VOS
IOz
VOS Magnitude Change
High Impedance Leakage
Power Off Leakage
mV
µA
µA
mA
mA
V
-10
-20
+10
+20
-5
IOFF
IOSD
IOS
1
Differential Output Short Circuit Current
Output Short Circuit Current
Output Voltage High
-3.5
-3.5
1.34
1.06
-5
VOH
1.6
VOL
Output Voltage Low
0.9
V
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AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Parameter
Symbol
Test Conditions
Minimum Typical
Maximum
Units
fMAX
Maximum Output Frequency
650
MHz
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
153.6MHz, Integration Range:
12kHz – 20MHz
tjit
0.164
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 650MHz
1.5
2.6
40
ns
ps
ps
ps
%
tsk(o)
tsk(pp)
tR / tF
odc
600
450
55
20% to 80% @ 50MHz
150
Output Duty Cycle
odc
45
50
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential output cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
Additive Phase Jitter @ 153.6MHz
12kHz to 20MHz = 0.164ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
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Parameter Measurement Information
V
DD
SCOPE
Qx
nCLK,
nPCLK
V
DD
3.3V 5%
POWER SUPPLY
VPP
VCMR
Cross Points
+
Float GND –
LVDS
CLK,
PCLK
nQx
GND
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
V
DD
nQx
Qx
nQ[0:3]
VOD
Cross Points
nQy
Q[0:3]
GND
Qy
VOS
tsk(o)
Differential Output Level
Output Skew
Part 1
nQx
nCLK,
nPCLK
Qx
CLK,
PCLK
Part 2
nQy
nQ[0:3]
Qy
Q[0:3]
tsk(pp)
tPD
Part-to-Part Skew
Propagation Delay
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Parameter Measurement Information, continued
nQ[0:3]
Q[0:3]
nQ[0:3]
Q[0:3]
80%
tF
80%
tR
VOD
tPW
20%
20%
tPERIOD
VOS
GND
tPW
odc =
x 100%
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
V
OD/∆ VOD
DC Input
100
out
➤
VOS/∆ VOS
➤
Offset Voltage Setup
Differential Output Voltage Setup
VDD
out
out
IOZ
3.3V 5% POWER SUPPLY
Float GND
DC Inpu
t
LVDS
_
+
IOSD
DC Input
LVDS
out
out
IOZ
High Impedance Leakage Current Setup
Differential Output Short Circuit Setup
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Parameter Measurement Information, continued
VDD
out
IOS
DC Input
LVDS
LVDS
VDD
IOSB
IOFF
out
Power Off Leakage Setup
Output Short Circuit Current Setup
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
-
V_REF
C1
0.1uF
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
HiPerClockS
Input
nCLK
LVPECL
HiPerClockS
LVHSTL
R1
50
R2
50
Input
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
HiPerClockS
Input
LVPECL
Receiver
LVDS
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
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LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 4A to 4F show interface examples for the
HiPerClockS PCLK/nPCLK input driven by the most common
driver types. The input interfaces suggested here are examples
only. If the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
R1
50
R2
50
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100
nPCLK
Zo = 50Ω
nPCLK
HiPerClockS
CML Built-In Pullup
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
CML
Figure 4A. HiPerClockS PCLK/nPCLK Input
Driven by a CML Driver
Figure 4B. HiPerClockS PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
R3
84
R4
84
Zo = 50Ω
Zo = 50Ω
C1
C2
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL
PCLK
PCLK
nPCLK
nPCLK
HiPerClockS
PCLK/nPCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
Figure 4C. HiPerClockS PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
Figure 4D. HiPerClockS PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
2.5V
3.3V
2.5V
R3
R4
120
120
3.3V
3.3V
Zo = 60Ω
Zo = 60Ω
Zo = 50Ω
PCLK
PCLK
nPCLK
R1
HiPerClockS
PCLK/nPCLK
100
SSTL
nPCLK
R1
120
R2
120
Zo = 50Ω
HiPerClockS
LVDS
Figure 4E. HiPerClockS PCLK/nPCLK Input
Driven by an SSTL Driver
Figure 4F. HiPerClockS PCLK/nPCLK Input Driven by
a 3.3V LVDS Driver
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Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVDS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 5. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 5. Typical LVDS Driver Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8543I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8543I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.173W * 73.2°C/W = 97.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
Transistor Count
The transistor count for ICS8543I is: 636
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number
8543BGI
8543BGIT
8543BGILF
8543BGILFT
Marking
Package
20 Lead TSSOP
20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS8543BGI
ICS8543BGI
ICS8543BGILF
ICS8543BGILF
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
A
Table
Page
Description of Change
Date
3
3
Updated Figure 1, CLK_EN Timing Diagram.
Updated Figure 1, CLK_EN Timing Diagram.
10/17/01
11/2/01
A
1
Features section, Bullet 6 to read 3.3V LVDS levels instead of LVPECL.
Updated Parameter Measurement Information figures.
A
B
5/6/02
6 - 10
1
Features - deleted bullet ""Designed to meet or exceed the requirements of
ANSI TIA/EIA-644"".
9/19/02
4E
T2
5
LVDS Table - changed VOD typical value from 350mV to 280mV.
2
4
Pin Characteristics - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - changed Output rating.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Added LVDS Driver Termination section.
9
C
1/5/04
10
11
Updated format throughout data sheet.
1
3
4
Features section - added lead-free bullet.
Updated Figure 1, CLK_EN Timing Diagram.
T4B
LVCMOS DC Characteristics Table - corrected typo in VIH max. from VDD - 0.3V to
VDD + 0.3V.
Updated Differential Clock Input Interface section.
10
11
12
13
15
D
2/27/08
Updated LVPECL Clock Input Interface section.
Added Recommendation for Unused Input and Output Pins section.
Added Power Considerations section.
Ordering Information Table - added lead-free Part/Order Number, Marking and note.
Updated format throughout the datasheet.
T9
T5
1
6
7
9
Features Section - added Additive Phase Jitter bullet.
AC Characteristics Table - added Additive Phase Jitter spec.
Added Additive Phase Jitter Plot.
E
9/9/08
Parameter Measurement Information - updated Output Rise/Fall Time diagram.
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Contact Information:
www.IDT.com
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Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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