72V7290L15BB [IDT]
PBGA-256, Tray;型号: | 72V7290L15BB |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | PBGA-256, Tray 时钟 先进先出芯片 内存集成电路 |
文件: | 总42页 (文件大小:320K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3 VOLTHIGH-DENSITYSUPERSYNCII™72-BITFIFO
512 x 72, 1,024 x 72
2,048 x 72, 4,096 x 72
8,192 x 72, 16,384 x 72
32,768 x 72, 65,536 x 72
PRELIMINARY
IDT72V7230, IDT72V7240
IDT72V7250, IDT72V7260
IDT72V7270, IDT72V7280
IDT72V7290,IDT72V72100
• Master Reset clears entire FIFO
FEATURES:
•
Partial Reset clears data, but retains programmable settings
• Choose among the following memory organizations:
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
IDT72V7230
IDT72V7240
IDT72V7250
IDT72V7260
IDT72V7270
IDT72V7280
IDT72V7290
IDT72V72100
512 x 72
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
16,384 x 72
32,768 x 72
65,536 x 72
• 100 MHz operation (10 ns read/write cycle time)
• User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
•
Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Asynchronous operation of Output Enable, OE
• Read Chip Select ( RCS ) on Read Side
• Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)
• Features JTAG (Boundary Scan)
•
Big-Endian/Little-Endian user selectable word representation
• Fixed, low first word latency
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Zero latency retransmit
• Auto power down minimizes standby power consumption
FUNCTIONALBLOCKDIAGRAM
D0 -Dn (x72, x36 or x18)
LD SEN
SCLK
WEN
WCLK
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
RAM ARRAY
512 x 72
HF
FWFT/SI
PFM
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
16,384 x 72
32,768 x 72
65,536 x 72
FSEL0
FSEL1
WRITE POINTER
READ POINTER
BE
CONTROL
LOGIC
IP
READ
CONTROL
LOGIC
RT
BM
IW
OW
BUS
OUTPUT REGISTER
RM
CONFIGURATION
MRS
PRS
RESET
LOGIC
RCLK
TCK
TRST
TMS
TDO
TDI
REN
RCS
JTAG
CONTROL
(BOUNDARY SCAN)
OE
4680 drw01
Q0 -Qn (x72, x36 or x18)
The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
NOVEMBER 2000
COMMERCIAL TEMPERATURE RANGE
1
2000 Integrated Device Technology, Inc.
DSC-4680/1
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
Bus-MatchingSyncFIFOsareparticularlyappropriatefornetwork,video,
telecommunications,datacommunicationsandotherapplicationsthatneedto
bufferlargeamountsofdataandmatchbussesofunequalsizes.
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeithera72-bit, 36-bitora18-bitwidthasdeterminedbythe
stateofexternalcontrolpinsInputWidth(IW),OutputWidth(OW),andBus-
Matching(BM)pinduringtheMasterResetcycle.
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WENisasserted. TheoutputportiscontrolledbyaReadClock(RCLK)input
DESCRIPTION:
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100areexceptionallydeep,highspeed,CMOSFirst-In-First-
Out(FIFO)memorieswithclockedreadandwritecontrolsandaflexibleBus-
Matchingx72/x36/x18dataflow. TheseFIFOsofferseveralkeyuserbenefits:
• Flexible x72/x36/x18 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothe time itcanbe read, is fixedandshort.
• Highdensityofferingsupto4Mbit
PINCONFIGURATION
A1 BALL PAD CORNER
A
Q33 Q35 Q47 Q50
Q32 Q34 Q46 Q49
D50
D33
Q53 Q65 Q68 Q71 D71 D68
D65 D53
D64 D52
D47
D35
B
C
D
E
F
D67
D49 D46 D34 D32
Q52 Q64 Q67 Q70 D70
Q51 Q63 Q66 Q69 D69
Q30 Q45 Q48
D48
Q31
D66 D63 D51
D45
D30 D31
TRST
Q29 Q28 Q27 VCC GND VCC GND TCK TDI
GND VCC GND VCC GND VCC
TDO TMS GND D27 D28 D29
VCC
Q17 Q16 Q15 VCC
Q14 Q13 Q12 VCC GND
GND
GND
GND D15 D16 D17
D12 D13 D14
VCC GND VCC GND VCC
VCC GND
G
H
J
Q11 Q10 Q9
VCC
GND D9
D10 D11
GND VCC GND VCC GND VCC GND VCC
Q62 Q61 Q60 VCC GND VCC GND VCC GND VCC GND VCC GND D60 D61 D62
Q59 Q58 Q57 VCC GND VCC GND VCC GND VCC GND VCC GND D57 D58 D59
K
L
Q56 Q55 Q54 VCC GND VCC GND VCC GND VCC
Q44 Q43 Q42 VCC
VCC GND D54 D55 D56
D42 D43 D44
GND
GND
GND VCC GND VCC GND VCC
GND IW
GND SCLK D39 D40 D41
M
N
P
R
T
Q41 Q40 Q39 VCC GND VCC GND GND FS1 FS0 OW
FWFT/
SI
RT
Q6
Q7
BE
HF
LD
D3
D4
SEN
D6
Q38 Q37 Q36
Q26 Q25 Q18
Q24 Q21 Q19
Q23 Q22 Q20
RM PFM
BM
IP
D36 D37 D38
Q3
Q4
Q0
Q1
D0
D1
D18 D25
D26
RCS PAE MRS PRS
D7
D19 D21 D24
OE
REN
7
EF
RCLK
8
PAF WEN
WCLK
D20 D22
14 15
D23
FF
Q8
Q5
Q2
D2
D5
D8
1
2
3
4
5
6
9
10
11
12
13
16
4680 drw02
PBGA (BB256-1, order code: BB)
TOP VIEW
2
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
DESCRIPTION(Continued)
andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge
ofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovidedfor
three-statecontroloftheoutputs.
AReadChipSelect(RCS)inputisalsoprovidedforsynchronousenable
anddisableofthereadportcontrolinput,REN. TheRCSinputissynchronized
tothereadclock,andalsoprovidesthree-statecontroloftheQnoutputs.When
RCSisdisable,RENwillbedisabledinternallyandoutputwillbethree-state.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed. Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal. ARENdoes
not have to be asserted for accessing the first word. However, subsequent
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
SCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standardmode orFWFTmode.
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
READ ENABLE (REN)
READ CHIP SELECT (RCS)
OUTPUT ENABLE (OE)
WRITE ENABLE (WEN)
LOAD (LD)
IDT
(x72, x36, x18) DATA IN (D0 - Dn)
(x72, x36, x18) DATA OUT (Q0 - Qn)
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
RETRANSMIT (RT)
SERIAL IN CLOCK(SCLK)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
HALF-FULL FLAG (HF)
FULL FLAG/INPUT READY (FF/IR)
JTAG CLOCK (TCLK)
PROGRAMMABLE ALMOST-FULL (PAF)
JTAG RESET (TRST)
JTAG MODE (TMS)
(TDO)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
(TDI)
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
BUS-
4680 drw03
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
3
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
The Partial Reset (PRS) also sets the read and write pointers to the first
ABig-Endian/Little-Endiandatawordformatisprovided. Thisfunctionis
location of the memory. However, the timing mode, programmable flag usefulwhentheFIFOisusedinBus-Matchingmode,todetermineorderofthe
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore words. Asanexample,ifBig-Endianmodeisselected,thenthemostsignificant
PartialResetremainunchanged. Theflagsareupdatedaccordingtothetiming word of the long word written into the FIFO will be read out of the FIFO first,
modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation, followedbytheleastsignificantword. IfLittle-Endianformatisselected,thenthe
whenreprogrammingprogrammableflagswouldbeundesirable.
leastsignificantwordofthelongwordwrittenintotheFIFOwillbereadoutfirst,
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost- followedbythemostsignificantword. Themodedesiredisconfiguredduring
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing masterresetbythestateoftheBig-Endian(BE)pin.
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted programmingtheflagoffsets. IfInterspersedParitymodeisselected,thenthe
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW- FIFOwillassumethattheparitybitislocatedinbitpositionD8duringtheparallel
to-HIGHtransitionofWCLK. Similarly,thePAFisassertedLOWontheLOW- programmingoftheflagoffsets. IfNon-InterspersedParitymodeisselected,
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH thenD8is assumedtobe a validbitandD16andD17are ignored. IPmode
transitionofRCLK.
is selectedduring MasterResetbythestateoftheIPinputpin.
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is automaticallypowerdown. Onceinthepowerdownstate,thestandbysupply
asserted and updated on the rising edge of WCLK only and not RCLK. The currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
modedesiredisconfiguredduringmasterresetbythestateoftheProgrammable inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
Flag Mode (PFM) pin.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read
once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit ChipSelect issynchronizedtotheRCLK. Boththeoutputenableandreadchip
operationbysettingthereadpointertothefirstlocationofthememoryarray. selectcontroltheoutputbufferoftheFIFO,causingthebuffertobeeitherHIGH
Azero-latencyretransmittimingmodecanbeselectedusingtheRetransmit impedanceorLOWimpedance. WhenusingRCS theOEpinshouldbetied
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero LOW. TheRCSinputalsoenablesordisablestheReadControlInputs,REN
latency retransmit. A HIGH on RM during Master Reset will select normal and RCLK.
latency.
JTAGtestpinsarealsoprovided,theFIFOhasfullyfunctionalBoundary
If zero latency retransmit operation is selected, the first data word to be Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK BoundaryScanArchitecture.
edgethatinitiatedtheretransmitbasedonRTbeingLOW. The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
RefertoFigure16and17forRetransmitTimingwithnormallatency. Refer 72V7290/72V72100arefabricatedusingIDT’shighspeedsubmicronCMOS
to Figure 18 and 19 for Zero Latency Retransmit Timing.
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas
shown in Table 1.
technology.
TABLE 1 BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
H
H
H
H
X
H
H
L
X
L
x72
x36
x18
x72
x72
x72
x72
x72
x36
x18
H
L
L
H
4
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION
Symbol
Name
DataInputs
I/O
Description
D0–D71
I
Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins should be tied
LOW.
MRS
MasterReset
I
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes. DuringMasterReset,
theFIFOis configuredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,oneofeight
programmableflagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endian
format,zerolatencytimingmode,interspersedparity,andsynchronousversusasynchronousprogrammable
flagtimingmodes.
PRS
RT
PartialReset
Retransmit
I
I
I
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes. DuringPartialReset,
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings
are allretained.
RT assertedontherisingedgeofRCLKinitializes theREADpointertozero,sets theEFflagtoLOW(OR to
HIGHinFWFTmode)anddoesnotdisturbthewritepointer,programmingmethod,existingtimingmodeor
programmableflagsettings.RTisusefultorereaddatafromthefirstphysicallocationoftheFIFO.
DuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.AfterMasterReset,thispinfunctions
asaserialinputforloadingoffsetregisters.
FWFT/SI FirstWordFall
Through/Serial In
OW
IW
OutputWidth
InputWidth
I
I
I
Thispin,alongwithIWandBM,selectsthebuswidthofthereadport.SeeTable1forbussizeconfiguration.
Thispin,alongwithOWandBM, selectsthebuswidthofthewriteport.SeeTable1forbussizeconfiguration.
BM
Bus-Matching
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
configuration.
BE
Big-Endian/
Little-Endian
I
I
I
I
I
I
I
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
willselectLittle-Endianformat.
RM
RetransmitTiming
Mode
DuringMasterReset,aLOWonRMwillselectzerolatencyRetransmittimingMode.AHIGHonRMwillselect
normallatencymode.
PFM
IP
Programmable
Flag Mode
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgrammableflagtimingmode.AHIGHon
PFM willselectSynchronousProgrammableflagtimingmode.
InterspersedParity
FlagSelectBit0
FlagSelectBit1
WriteClock
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.A HIGHwillselectInterspersed
Paritymode.
FSEL0
FSEL1
WCLK
DuringMasterReset,thisinputalongwithFSEL1andthe LDpin,willselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andthe LDpinwillselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheFIFOandoffsetsintotheprogrammable
registersforparallelprogramming.
WEN
RCLK
WriteEnable
ReadClock
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
Whenenabledby REN, the risingedge ofRCLKreads data fromthe FIFOmemoryandoffsets fromthe
programmableregisters.(RCSmustbeactive).
REN
OE
RCS
ReadEnable
I
I
I
REN enables RCLKforreadingdata fromthe FIFOmemoryandoffsetregisters. (RCSmustbe active).
OE provides asynchronous controlof theoutputimpedanceofQn.
RCSprovidessynchronouscontrolof thereadportandoutputimpedanceofQn,synchronoustoRCLK.When
using RCSthe OE pin mustbe tiedLOW.
OutputEnable
ReadChipSelect
SCLK
SerialInputClock
I
when enabled by SEN, the rising edge of SCLK writes one bit of data (present on the SI input), into the
programmableregisterforserialprogramming.
SEN
LD
SerialEnable
Load
I
I
SENenablesserialloadingofprogrammableflagoffsets.
This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
determinesoneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichthese
offsetregisterscanbeprogrammed,parallelorserial(seeTable2). AfterMasterReset,thispinenableswriting
toandreadingfromtheoffsetregisters.
FF/IR
Full Flag/
Input Ready
O
Inthe IDTStandardmode, theFF functionis selected. FF indicates whetherornottheFIFOmemoryis full.
IntheFWFTmode,theIRfunctionisselected. IRindicateswhetherornotthereisspaceavailableforwriting
totheFIFOmemory.
5
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(Continued)
Symbol
Name
I/O
Description
EF/OR
EmptyFlag/
OutputReady
O
IntheIDTStandardmode,theEFfunctionisselected. EFindicateswhetherornottheFIFOmemoryisempty.
InFWFTmode,theOR functionisselected. ORindicateswhetherornotthereisvaliddataavailableattheoutputs.
PAF
PAE
Programmable
Almost-FullFlag
O
O
PAF goes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedin
theFullOffsetregister. PAF goes LOWifthenumberof freelocations intheFIFOmemoryis less thanor
equaltom.
Programmable
Almost-Empty
PAEgoes LOWifthenumberofwords intheFIFOmemoryis less thanoffsetn,whichis storedintheEmpty
Offset register. PAE goes HIGH if the numberofFlagwords inthe FIFO memory is greater thanorequalto
offsetn.
HF
Q0–Q71
Half-FullFlag
DataOutputs
O
O
HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused output pins should not
beconnected. DataOutputs arenot5Vtolerantregardless ofthestateofthe OEandRCS.
Clock input for JTAG function. TMS and TDI are sampled on the rising edge. TDO is output on the falling
edge.
(1)
TCK
JTAGClock
I
(1)
TRST
TMS
JTAGReset
I
I
TRST is the asynchronous reset pin for the JTAG controller.
TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modesof
operationforthe JTAGboundaryscan.
JTAGModeSelect
TDI
TestDataInput
TestDataOutput
I
During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK. This
isalsothedatafortheInstructionRegister,IDRegisterandBypassRegister.
TDO
O
During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK. This
outputis inHigh-Zexceptwhenshiftingwhile inSHIFT-DRandSHIFT-IRcontrollerstates.
NOTE:
1. If the JTAG feature is not being used, TCK and TRST should be tied LOW.
6
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Commercial
Unit
VTERM
TerminalVoltage
with respect to GND
–0.5to+4.5
V
Symbol
Parameter
SupplyVoltage
Min.
Typ.
Max.
Unit
VCC
3.15
3.3
3.45
V
TSTG
IOUT
Storage
Temperature
–55 to +125
–50 to +50
°C
GND
VIH
SupplyVoltage
0
2.0
—
0
0
0
VCC+0.3
0.8
V
V
InputHighVoltage
InputLowVoltage
—
—
—
DCOutputCurrent
mA
(1)
VIL
V
NOTE:
TA
OperatingTemperature
Commercial
70
°C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTES:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; JEDEC JESD8-A compliant)
IDT72V7230L
IDT72V7240L
IDT72V7250L
IDT72V7260L
IDT72V7270L
IDT72V7280L
IDT72V7290L
IDT72V72100L
Commercial
tCLK = 10, 15 ns
Symbol
Parameter
Min.
Max.
Unit
(1)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
–10
2.4
—
1
µ A
µA
V
(2)
ILO
10
—
0.4
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 4 mA
V
(3,4,5)
ICC1
Active Power Supply Current
StandbyCurrent
—
—
75
15
mA
mA
(3,6)
ICC2
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 15.5 + 2.275*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
7
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; JEDEC JESD8-A compliant)
Commercial
IDT72V7230L10
IDT72V7240L10
IDT72V7250L10
IDT72V7260L10
IDT72V7270L10
IDT72V7280L10
IDT72V7290L10
IDT72V72100L10
IDT72V7230L15
IDT72V7240L15
IDT72V7250L15
IDT72V7260L15
IDT72V7270L15
IDT72V7280L15
IDT72V7290L15
IDT72V72100L15
Symbol
fS
Parameter
Min.
—
1
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
Min.
Max.
66.7
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Frequency
DataAccessTime
Clock Cycle Time
Clock High Time
Clock Low Time
DataSetupTime
DataHoldTime
—
1
tA
tCLK
10
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
10
10
—
0
15
6
—
—
—
—
—
—
—
—
—
—
—
—
15
tCLKH
tCLKL
tDS
6
4
tDH
1
tENS
EnableSetupTime
EnableHoldTime
LoadSetupTime
LoadHoldTime
4
tENH
tLDS
1
4
tLDH
1
(2)
tRS
ResetPulseWidth
15
15
15
—
0
tRSS
ResetSetupTime
tRSR
ResetRecoveryTime
ResettoFlagandOutputTime
ModeSelectTime
tRSF
tFWFT
tRTS
—
—
—
6
—
—
—
8
RetransmitSetupTime
3.5
1
4
(3)
tOLZ
tOE
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid
1
1
1
(3)
tOHZ
tWFF
tREF
OutputEnabletoOutputinHighZ
Write Clock to FF or IR
Read Clock to EF or OR
ClocktoAsynchronousProgrammableAlmost-FullFlag
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
Clock to HF
1
6
1
8
—
—
—
—
—
—
—
3.5
0.5
1
6.5
6.5
16
—
—
—
—
—
—
—
5
10
10
tPAFA
tPAFS
tPAEA
tPAES
tHF
20
6.5
16
10
20
6.5
16
10
20
tRCSS
tRCSH
tRCSLZ
tRCSHZ
tSKEW1
tSKEW2
RCSSetupTime
RCS Hold Time
RCLK to Active from High-Z
—
—
6.5
6.5
—
—
—
—
10
1
(3)
1
(3)
RCLK to High-Z
1
1
10
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
7
9
—
—
10
14
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3.3V
3. Values guaranteed by design, not currently tested.
4. Data Sheet slow conditions: 85°c, 3.0V. Data Sheet fast conditions: -40°c, 3.6V.
330Ω
ACTESTCONDITIONS
D.U.T.
InputPulseLevels
GND to 3.0V
3ns
30pF*
510Ω
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1.5V
4680 drw04
1.5V
Figure 2. Output Load
* Includes jig and scope capacitances
SeeFigure2
8
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
FUNCTIONALDESCRIPTION
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable3. Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue. ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100 support two different timing modes of operation: IDT
Standardmode orFirstWordFallThrough(FWFT)mode. The selectionof
whichmodewilloperateisdeterminedduringMasterReset,bythestateofthe
FWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
notthereareanywordspresentintheFIFO. ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOhasanyfreespaceforwriting. InIDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,REN=LOWisnotnecessary. Subsequentwordsmustbeaccessed
using the Read Enable (REN) and RCLK.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
10,11,12,16 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable4. TowritedataintototheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK. Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW. SubsequentwriteswillcontinuetofilluptheFIFO. PAEwill
goHIGHaftern+2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue. ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2. Thisparameterisalsouserprogrammable. SeesectiononProgrammable
FlagOffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHFwouldtoggletoLOWoncethe258thword
for the IDT72V7230, 514th word for the IDT72V7240, 1,026th word for the
IDT72V7250, 2,050th word for the IDT72V7260, 4,098th word for the
IDT72V7270, 8,194th word for the IDT72V7280, 16,386th word for the
IDT72V7290 and 32,770th word for the IDT72V72100, respectively was
writtenintotheFIFO. ContinuingtowritedataintotheFIFOwillcausethePAF
togoLOW. Again,ifnoreadsareperformed,thePAFwillgoLOWafter(513-m)
writesfortheIDT72V7230,(1,025-m)writesfortheIDT72V7240,(2,049-m)
writesfortheIDT72V7250,(4,097-m)writesfortheIDT72V7260and(8,193-m)
writesfortheIDT72V7270,16,385writesfortheIDT72V7280,32,769writes
fortheIDT72V7290and65,537writes fortheIDT72V72100,wheremis the
fulloffsetvalue. Thedefaultsettingforthesevaluesarestatedinthefootnote
of Table 2.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable3. TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW. DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH. Subsequentwriteswillcontinue
tofilluptheFIFO. TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern+1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value. ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2. Thisparameterisalsouserprogrammable. SeesectiononProgrammable
FlagOffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
the 257thwordforIDT72V7230, 513rdwordforIDT72V7240, 1,025thword
forIDT72V7250,2,049thwordforIDT72V7260,4,097thwordforIDT72V7270,
8,193th word for the IDT72V7280, 16,385th word for the IDT72V7290 and
32,769thwordfortheIDT72V72100,respectivelywaswrittenintotheFIFO.
ContinuingtowritedataintotheFIFOwillcausetheProgrammableAlmost-Full
flag(PAF)togoLOW. Again,ifnoreadsareperformed, the PAFwillgoLOW
after(512-m)writesfortheIDT72V7230,(1,024-m)writesfortheIDT72V7240,
(2,048-m)writesfortheIDT72V7250,(4,096-m)writesfortheIDT72V7260,
(8,192-m)writesfortheIDT72V7270,(16,384-m)writesfortheIDT72V7280,
(32,768-m) writes for the IDT72V7290 and (65,536-m) writes for the
IDT72V72100. Theoffset“m”isthefulloffsetvalue. Thedefaultsettingforthese
values are stated in the footnote of Table 2. This parameter is also user
programmable. SeesectiononProgrammableFlagOffsetLoading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
to the FIFO. D = 512 writes for the IDT72V7230, 1,024 writes for the
IDT72V7240,2,048writesfortheIDT72V7250,4,096writesfortheIDT72V7260,
8,192writesfortheIDT72V7270,16,384writesfortheIDT72V7280,32,768
writesfortheIDT72V7290,65,536writesfortheIDT72V72100,respectively.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations. Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
DwritestotheFIFO. D=513writesfortheIDT72V7230,1,025writesforthe
IDT72V7240,2,049writesfortheIDT72V7250,4,097writesfortheIDT72V7260
and 8,193 writes for the IDT72V7270, 16,385 writes for the IDT72V7280,
32,769 writes for the IDT72V7290, 65,537 writes for the IDT72V72100,
respectively. NotethattheadditionalwordinFWFTmodeisduetothecapacity
ofthememoryplusoutputregister.
IftheFIFOisfull,thefirstreadoperationwillcausethe IRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditionsdescribedinTable4. Iffurtherreadoperationsoccur,withoutwrite
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
nistheemptyoffsetvalue. ContinuingreadoperationswillcausetheFIFOto
becomeempty. WhenthelastwordhasbeenreadfromtheFIFO,ORwillgo
HIGH inhibiting further read operations. REN is ignored when the FIFO is
empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered,andtheIRflagoutputisdoubleregister-buffered.
RelevanttimingdiagramsforFWFTmodecanbefoundinFigure13,14,15,
17, and 19.
9
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
PROGRAMMING FLAG OFFSETS
TABLE 2 DEFAULT PROGRAM-
MABLE FLAG OFFSETS
IDT72V7230, 72V7240
FullandEmptyFlagoffsetvaluesareuserprogrammable. TheIDT72V7230/
72V7240/72V7250/72V7260/72V7270/72V7280/72V7290/72V72100have
internalregistersfortheseoffsets. Thereareeightdefaultoffsetvaluesselectable
duringMasterReset. TheseoffsetvaluesareshowninTable2. Offsetvalues
can also be programmed into the FIFO in one of two ways; serial or parallel
loadingmethod. TheselectionoftheloadingmethodisdoneusingtheLD(Load)
pin. DuringMasterReset,thestateoftheLDinputdetermineswhetherserial
orparallelflagoffsetprogrammingis enabled. AHIGHonLD duringMaster
Resetselectsserialloadingofoffsetvalues. ALOWonLDduringMasterReset
selectsparallelloadingofoffsetvalues.
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
thecurrentoffsetvalues. Offsetvaluescanbereadviatheparalleloutputport
Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel). Itis
notpossibletoreadtheoffsetvaluesinserialfashion.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
Foramoredetaileddescription,seediscussionthatfollows.
LD
L
L
L
L
H
H
H
H
FSEL1
FSEL0
Offsets n,m
H
L
L
H
L
H
L
H
L
H
L
H
L
L
H
H
511
255
127
63
31
15
7
3
LD
FSEL1
FSEL0
Program Mode
(3)
H
X
X
Serial
(4)
L
X
X
Parallel
IDT72V7250, 72V7260, 72V7270, 72V7280
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
MasterReset,regardlessofwhetherserialorparallelprogramminghasbeen
selected. Validprogrammingranges are from0toD-1.
LD
H
L
L
L
FSEL1
FSEL0
Offsets n,m
L
H
L
L
L
H
L
H
L
H
H
1,023
511
255
127
63
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100 can be configured during the Master Reset cycle with
either synchronousorasynchronoustimingforPAFandPAEflagsbyuseof
the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
notRCLK. Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK. Fordetailtimingdiagrams,seeFigure23forsynchronous
PAF timingandFigure24forsynchronous PAEtiming.
L
L
H
H
L
H
H
H
31
15
7
H
LD
H
L
FSEL1
FSEL0
Program Mode
(3)
X
X
X
X
Serial
Parallel
(4)
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK. PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK. Fordetailtimingdiagrams,seeFigure
25forasynchronousPAFtimingandFigure26forasynchronousPAEtiming.
IDT72V7290, 72V72100
LD
L
L
FSEL1
FSEL0
Offsets n,m
16,383
8,191
4,095
2,047
1,023
511
H
L
H
H
L
L
H
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
255
127
LD
H
L
FSEL1
FSEL0
Program Mode
(3)
X
X
X
X
Serial
(4)
Parallel
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
10
TABLE 3
STATUS FLAGS FOR IDT STANDARD MODE
IDT72V7230
IDT72V7240
IDT72V7250
IDT72V7260
HF
FF PAF
PAE EF
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
0
0
0
0
1 to n (1)
1 to n(1)
1 to n (1)
1 to n(1)
Number of
Words in
FIFO
H
H
H
H
H
(n+1) to 256
(n+1) to 512
(n+1) to 1,024
(n+1) to 2,048
257 to (512-(m+1))
513 to (1,024-(m+1))
1,025 to (2048-(m+1))
2,049 to (4,096-(m+1))
L
L
H
H
H
H
to 2,047
L
L
(512-m) to 511
512
(1024-m) to 1,023
1,024
(2048-m)
(4,096-m) to 4,095
4,096
2,048
IDT72V7290
IDT72V72100
IDT72V7270
IDT72V7280
FF PAF
PAE EF
HF
H
H
H
L
L
L
L
0
H
H
H
H
H
H
H
H
H
0
0
0
1 to n(1)
1 to n (1)
1 to n
1 to n(1)
Number of
Words in
FIFO
(1)
H
H
H
H
H
H
(n+1) to 4,096
(n+1) to 8,192
(n+1) to 16,384
(n+1) to 32,768
32,769 to (65,536-(m+1))
4,097 to (8,192-(m+1))
H
H
H
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1))
L
(8,192-m)
L
to 8,191
to 16,383
(16,384-m)
(32,768-m) to 32,767
32,768
to 65,535
(65,536-m)
L
L
L
8,192
16,384
65,536
NOTE:
1. See table 2 for values for n, m.
TABLE 4
STATUS FLAGS FOR FWFT MODE
IDT72V7240
IDT72V7230
IDT72V7250
IDT72V7260
HF
IR PAF
PAE OR
L
L
L
L
L
H
H
H
H
H
L
H
L
0
0
0
0
Number of
Words in
FIFO
1 to n+1
1 to n+1
L
1 to n+1
1 to n+1
H
L
L
L
L
H
L
(n+2) to 513
(n+2) to 1,025
(n+2) to 2,049
(n+2) to 257
H
H
H
H
258 to (513-(m+1))
514 to (1,025-(m+1))
1,026 to (2,049-(m+1))
(2,049-m) to 2,048
2,049
2,050 to (4,097-(m+1))
L
L
L
L
(513-m)
to 512
to 4,096
(4,097-m)
(1,025-m)
to 1,024
H
513
1,025
4,097
IDT72V7290
IDT72V72100
IDT72V7270
IDT72V7280
HF
IR PAF
PAE OR
0
H
H
H
L
L
L
H
0
0
0
L
L
L
L
H
H
H
H
L
1 to n+1
1 to n+1
1 to n+1
Number of
Words in
FIFO
1 to n+1
L
(n+2) to 4,097
H
H
H
H
L
(n+2) to 8,193
8,194 to (16,385-(m+1))
(n+2) to 16,385
(n+2) to 32,769
32,770 to (65,537-(m+1))
(65,537-m) to 65,536
65,537
4,098 to (8,193-(m+1))
L
16,386 to (32,769-(m+1))
(8,193-m)
to 8,192
L
L
L
L
(16,385-m)
(32,769-m)
to 16,384
to 32,768
32,769
H
L
8,193
L
16,385
4680 drw 05
NOTE:
1. See table 2 for values for n, m.
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
IDT72V7230
IDT72V7240
IDT72V7250
IDT72V7260
IDT72V7270
IDT72V7280
IDT72V7290
IDT72V72100
WCLK RCLK
SCLK
LD
WEN
REN
SEN
Parallel write to registers:
Empty Offset
Full Offset
X
X
0
0
1
1
Parallel read from registers:
Empty Offset
Full Offset
X
X
0
0
1
1
0
1
1
0
Serial shift into registers:
X
X
18 bits for the IDT72V7230
20 bits for the IDT72V7240
22 bits for the IDT72V7250
24 bits for the IDT72V7260
26 bits for the IDT72V7270
28 bits for the IDT72V7280
30 bits for the IDT72V7290
32 bits for the IDT72V72100
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
X
X
1
1
1
No Operation
Write Memory
X
1
1
0
X
0
X
X
X
X
X
Read Memory
X
X
1
1
1
X
No Operation
4680 drw06
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
12
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
1st Parallel Offset Write/Read Cycle
D/Q71
D/Q19
D/Q0
D/Q17
D/Q8
EMPTY OFFSET REGISTER (PAE)
Non-Interspersed
Parity
16
13 12 11 10
8 7
6
6
5
5
1
1
15 14
9
4 3 2
4 3 2
Interspersed
Parity
14
7
8
16 15
13 12 11 10 9
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q71
D/Q19
D/Q0
D/Q17
D/Q8
FULL OFFSET REGISTER (PAF)
Non-Interspersed
Parity
16
15
13 12 11 10
8
8
7
7
6
6
5
5
15 14
9
1
1
4 3 2
4 3 2
Interspersed
Parity
14
13 12 11 10 9
16
# of Bits Used
x72 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q35
D/Q35
D/Q19
D/Q19
D/Q0
D/Q17
D/Q8
EMPTY OFFSET REGISTER (PAE)
Non-Interspersed
Parity
16
13 12 11 10
8 7
6
6
5
5
1
1
15 14
9
4 3 2
4 3 2
Interspersed
Parity
14
7
8
16 15
13 1211 10 9
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q0
D/Q17
D/Q8
FULL OFFSET REGISTER (PAF)
Non-Interspersed
Parity
16
15
13 12 11 10
8
8
7
7
6
6
5
5
15 14
9
1
1
4 3 2
4 3 2
Interspersed
Parity
14
13 12 11 10 9
16
# of Bits Used
x36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
D/Q0
EMPTY OFFSET (LSB) REGISTER (PAE)
Non-Interspersed
Parity
16 15 14 13 12 11 10 9 8 7
13 12 10
6
6
5
5
4
4
3 2 1
3 2 1
16
Interspersed
Parity
15 14
11
9
8 7
# of Bits Used:
D/Q8
# of Bits Used
09 bits for the IDT72V7230
10 bits for the IDT72V7240
11 bits for the IDT72V7250
12 bits for the IDT72V7260
13 bits for the IDT72V7270
14 bits for the IDT72V7280
15 bits for the IDT72V7290
16 bits for the IDT72V72100
Note: All unused input bits
are don’t care.
2nd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q0
D/Q16
FULL OFFSET (LSB) REGISTER (PAF)
13
10 9 8 7
12 11
6
5
4
3 2
3 2
1
1
16 15 14
14 13 12 11 10 9
16 15
8 7
D/Q8
6
5
4
x18 Bus Width
4680 drw07
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
13
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
WhenLDissetLOWagain,andWENisLOW,thenextoffsetregisterinsequence
iswrittento. AsanalternativetoholdingWENLOWandtogglingLD,parallel
programmingcanalsobeinterruptedbysettingLDLOWandtogglingWEN.
Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid
during the programming process. From the time parallel programming has
begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset
wordhasbeenwrittentotheregisterpertainingtothatflag. Measuringfromthe
risingWCLKedgethatachievestheabovecriteria;PAFwillbevalidaftertwo
morerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
registerpointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Q16
pinswhenLDissetLOWandRENissetLOW. Forx72,x36orx18outputbus
width, data are read via Q0-Q16 from the Empty Offset Register on the first
LOW-to-HIGHtransitionofRCLK. UponthesecondLOW-to-HIGHtransition
ofRCLK,dataarereadfromtheFullOffsetRegister. ThethirdtransitionofRCLK
reads,onceagain,fromtheEmptyOffsetRegister. SeeFigure3, Program-
mableFlagOffsetProgrammingSequence. SeeFigure22,ParallelReadof
ProgrammableFlagRegisters,forthetimingdiagramforthismode.
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,
orbothtogether. WhenRENandLD arerestoredtoaLOW level,readingof
theoffsetregisterscontinueswhereitleftoff. Itshouldbenoted,andcareshould
betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
Parallelreadingofthe offsetregisters is always permittedregardless of
whichtimingmode (IDTStandardorFWFTmodes)has beenselected.
FUNCTIONALDESCRIPTION
(Continued)
SERIAL PROGRAMMING MODE
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then
programmingofPAEandPAFvaluescanbeachievedbyusingacombination
oftheLD,SEN,SCLKandSIinputpins. ProgrammingPAEandPAFproceeds
asfollows:whenLDandSENaresetLOW,dataontheSIinputarewritten,one
bitforeachSCLKrisingedge,startingwiththeEmptyOffsetLSBandending
withtheFullOffsetMSB. Atotalof18bitsfortheIDT72V7230,20bitsforthe
IDT72V7240,22bitsfortheIDT72V7250,24bitsfortheIDT72V7260,26bits
fortheIDT72V7270,28bitsfortheIDT72V7280,30bitsfortheIDT72V7290
and 32 bits for the IDT72V72100. See Figure 20, Serial Loading of
ProgrammableFlagRegisters,forthetimingdiagramforthismode.
Using the serial method, individual registers cannot be programmed
selectively. PAEandPAFcanshowavalidstatusonlyafterthecompleteset
of bits (for all offset registers) has been entered. The registers can be
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot
havetooccuratonce. AselectnumberofbitscanbewrittentotheSIinputand
then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia
DnbytogglingWEN. WhenWENisbroughtHIGHwithLDandSENrestored
toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI. Ifan
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW
anddeactivateSENortosetSENLOWanddeactivateLD. OnceLDandSEN
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen
written. MeasuringfromtherisingSCLKedgethatachievestheabovecriteria;
PAFwillbevalidafterthreemorerisingWCLKedgesplustPAF,PAEwillbevalid
afterthe nextthree risingRCLKedges plus tPAE.
RETRANSMITOPERATION
The Retransmit operation allows data that has already been read to be
accessedagain. Thereare2modesofRetransmitoperation,normallatency
andzerolatency. TherearetwostagestoRetransmit:first,asetupprocedure
that resets the read pointer to the first location of memory, then the actual
retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
beginningofmemory.
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn.
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
RENandWENmustbeHIGHbeforebringingRTLOW. Whenzerolatencyis
utilized,RENdoesnotneedtobeHIGHbeforebringingRTLOW. Atleasttwowords,
butnomorethanD-2wordsshouldhavebeenwrittenintotheFIFO,andread
fromtheFIFO,betweenReset(MasterorPartial)andthetimeofRetransmit
setup. D=512fortheIDT72V7230,1,024fortheIDT72V7240,2,048forthe
IDT72V7250,4,096fortheIDT72V7260,8,192fortheIDT72V7270,16,384
for the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the
IDT72V72100. In FWFT mode, D = 513 for the IDT72V7230, 1,025 for the
IDT72V7240,2,049fortheIDT72V7250,4,097fortheIDT72V7260,8,193for
theIDT72V7270,16,385fortheIDT72V7280,32,769fortheIDT72V7290and
65,537 for the IDT72V72100.
PARALLELMODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programmingofPAEandPAFvaluescanbeachievedbyusingacombination
of the LD, WCLK, WEN and Dn input pins. Programming PAE and PAF
proceeds as follows:LD andWEN mustbe setLOW. Forx72,x36orx18bit
inputbuswidths,dataontheinputsDnarewrittenintotheEmptyOffsetRegister
onthefirstLOW-to-HIGHtransitionofWCLK. UponthesecondLOW-to-HIGH
transition of WCLK, data are written into the Full Offset Register. The third
transitionofWCLKwrites,onceagain,totheEmptyOffsetRegister. SeeFigure
3, Programmable Flag Offset Programming Sequence. See Figure 21,
ParallelLoadingofProgrammableFlagRegisters,forthetimingdiagramfor
thismode.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
if EF was HIGH before setup. Duringthis period, the internalreadpointeris
initializedtothefirstlocationoftheRAMarray.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 16,
Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer. Thetwopointersoperateindependently;however,areadandawrite
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializesbothpointerstotheEmptyOffsetregister. APartialResethasnoeffect
onthepositionofthesepointers.
Write operations to the FIFO are allowed before and during the parallel
programmingsequence. Inthiscase,theprogrammingofalloffsetregistersdoes
nothavetooccuratonetime. Oneoffsetregistercanbewrittenandthenby
bringing LD HIGH, write operations can be redirected to the FIFO memory.
14
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setupbysettingORHIGH. Duringthisperiod,theinternalreadpointerisset
tothefirstlocationoftheRAMarray.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. SeeFigure17,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafterRTissetup,
thePAEflagwillbeupdated. HFisasynchronous,thustherisingedgeofRCLK
thatRTissetupwillupdateHF. PAFissynchronizedtoWCLK,thusthesecond
risingedgeofWCLKthatoccurstSKEW aftertherisingedgeofRCLKthatRT
is setup will update PAF. RT is synchronized to RCLK.
TheRetransmitfunctionhastheoptionoftwomodesofoperation,either
“normal latency” or “zero latency”. Figure 16 and Figure 17 mentioned
previously, relate to “normal latency”. Figure 18 and Figure 19 show “zero
latency”retransmitoperation. Zerolatencybasicallymeansthatthefirstdata
wordtoberetransmitted,isplacedontotheoutputregisterwithrespecttothe
RCLKpulsethatinitiatedtheretransmit.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
15
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 16,
Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setupbysettingORHIGH. Duringthisperiod,theinternalreadpointerisset
tothefirstlocationoftheRAMarray.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. SeeFigure17,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
SIGNALDESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
Datainputsfor72-bitwidedata(D0-D71),datainputsfor36-bitwidedata
(D0 - D35) or data inputs for 18-bit wide data (D0 - D17).
CONTROLS:
MASTER RESET ( MRS )
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state. Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray. PAEwill goLOW, PAFwillgoHIGH,and HFwillgoHIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,BM,BE,RM,PFMandIParedefined
duringtheMasterResetcycle.
In Retransmit operation, zero latency mode can be selected using the
RetransmitMode(RM)pinduringaMasterReset. Thiscanbeappliedtoboth
IDT Standard mode and FWFT mode.
Note,theReadChipSelect(RCS)inputmustbeLOWduringRetransmit.
TheRCSinputenables/disablestheRENinput.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes. AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace. MRS
isasynchronous.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is adualpurposepin. DuringMasterReset,thestateoftheFWFT/
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor
First Word Fall Through (FWFT) mode.
See Figure 8, Master Reset Timing, forthe relevanttimingdiagram.
PARTIAL RESET ( PRS )
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
notthereareanywordspresentintheFIFOmemory. ItalsousestheFullFlag
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
whetherornottheFIFOmemoryhasanyfreespaceforwriting. IntheFWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW
state. AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW, PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
modeisactive,thenFFwillgoHIGHandEFwillgoLOW. IftheFirstWordFall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. Theprogrammingmethod(parallelorserial)currentlyactiveat
thetimeofPartialResetisalsoretained. Theoutputregisterisinitializedtoall
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF
offsetsintotheprogrammableregisters. Theserialinputfunctioncanonlybe
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT
StandardandFWFTmodes.
See Figure 9, PartialResetTiming, forthe relevanttimingdiagram.
RETRANSMIT ( RT )
The Retransmit operation allows data that has already been read to be
accessedagain. Thereare2modesofRetransmitoperation,normallatency
andzerolatency. TherearetwostagestoRetransmit:first,asetupprocedure
that resets the read pointer to the first location of memory, then the actual
retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
beginningofthememory.
RetransmitsetupisinitiatedbyholdingRTLOWduringarising RCLKedge.
RENandWENmustbeHIGHbeforebringingRTLOW. Whenzerolatencyis
utilized, RENdoesnotneedtobeHIGHbeforebringingRT LOW.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
if EF was HIGHbefore setup. During this period, the internal readpointeris
initializedtothefirstlocationoftheRAMarray.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontherisingedgeoftheWCLKinput. Datasetup
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe
WCLK. ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof
updating HF flag to LOW.) The Write and Read Clocks can either be
independentorcoincident.
WRITE ENABLE ( WEN )
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
16
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
into a high impedance state. The OE input is Asynchronous and should be
enabled (held LOW) when using the RCS input.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles +tSKEW afterthe RCLKcycle.
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo
LOWallowingawritetooccur. TheIRflagis updatedbytwoWCLKcycles +
tSKEW afterthe validRCLKcycle.
READ CHIP SELECT ( RCS )
The Read Chip Select input provides synchronous control of the Read
outputport. WhenRCSgoesLOW,thenextrisingedgeofRCLKcausesthe
QnoutputstogototheLOWZstate. WhenRCSgoesHIGH,thenextRCLK
risingedge causes the Qnoutputs toreturntoHIGHZ.
During the time while RCS is HIGH (disabled) all read operations are
ignored. Thatis,theRENinputisdisabledanddataisnotclockedfromtheRAM
arraytotheoutputregister.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
TheRCSinputdoesnoteffecttheoperationoftheflags. Forexample,when
thefirstwordiswrittentoanemptyFIFO,theEFwillstillgofromLOWtoHIGH
basedon a rising edge of RCLK, regardless of the state of theRCS input.
Also,whenoperatingtheFIFOinFWFTmodethefirstwordwrittentoan
emptyFIFOwillstillbeclockedthroughtotheoutputregisterbasedonRCLK,
regardlessofthestateofRCS. TheRCSpinmustalsobeactive(LOW)inorder
toperformaRetransmit. Seefigure12forReadCycleandReadChipSelect
Timing (IDT Standard Mode). See figure 15 for Read Cycle and Read Chip
Select Timing (First Word Fall Through Mode).
READ CLOCK (RCLK)
AreadcycleisinitiatedontherisingedgeoftheRCLKinput. Datacanbe
readontheoutputs,ontherisingedgeoftheRCLKinput. Itispermissibleto
stoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAEandHFflagswill
not be updated. (Note that RCLK is only capable of updating the HF flag to
HIGH.) The Write and Read Clocks can be independent or coincident.
READ ENABLE ( REN )
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
andnonewdata is loadedintothe outputregister. The data outputs Q0-Qn
maintainthepreviousdatavalue.
LOAD ( LD )
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
canbeprogrammed,parallelorserial(seeTable2). AfterMasterReset, LD
enableswriteoperationstoandreadoperationsfromtheoffsetregisters. Only
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offsetregisters canbereadonlyinparallel.
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvaluesPAEandPAF. PullingLDLOWwillbeginaserialloading
orparallelloadorreadofthese offsetvalues.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
wordwrittentoanemptyFIFO,mustberequestedusingRENprovidedthatRCS
isLOW. WhenthelastwordhasbeenreadfromtheFIFO,theEmptyFlag(EF)
willgoLOW,inhibitingfurtherreadoperations. RENisignoredwhentheFIFO
isempty. Onceawriteisperformed,EFwillgoHIGHallowingareadtooccur.
TheEFflagisupdatedbytwoRCLKcycles+tSKEW afterthevalidWCLKcycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW
afterthefirstwrite. RENandRCSdonotneedtobeassertedLOW. Inorder
toaccessallotherwords,areadmustbeexecutedusingRENandRCS must
beenabledLOW. TheRCLKLOW-to-HIGHtransitionafterthelastword has
been read from the FIFO, Output Ready (OR) will go HIGH with a true read
(RCLKwithREN=LOW;RCS=LOW),inhibitingfurtherreadoperations. REN
is ignored when the FIFO is empty.
BUS-MATCHING (BM, IW, OW)
ThepinsBM,IWandOWareusedtodefinetheinputandoutputbuswidths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
sizes. SeeTable1forcontrolsettings. Allflagswilloperateontheword/byte
sizeboundaryasdefinedbytheselectionofbuswidth. SeeFigure4forBus-
MatchingByteArrangement.
SERIAL CLOCK ( SCLK )
BIG-ENDIAN/LITTLE-ENDIAN ( BE )
Duringserialloadingoftheprogrammableflagoffsetregisters,arisingedge
ontheSCLKinputisusedtoloadserialdatapresentontheSIinputprovided
thattheSENinputisLOW.
During Master Reset, a LOW on BE will select Big-Endian operation. A
HIGHonBEduringMasterResetwillselectLittle-Endianformat. Thisfunction
isusefulwhenthefollowinginputtooutputbuswidthsareimplemented:x72to
x36, x72 to x18, x36 to x72 and x18 to x72. If Big-Endian mode is selected,
thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill
bereadoutoftheFIFOfirst,followedbytheleastsignificantlongword. IfLittle-
Endianformatisselected,thentheleastsignificantwordofthelongwordwritten
intotheFIFOwillbereadoutfirst,followedbythemostsignificantword. The
modedesiredisconfiguredduringmasterresetbythestateoftheBig-Endian
(BE) pin. See Figure 4 for Bus-Matching Byte Arrangement.
SERIAL ENABLE ( SEN )
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofSCLK.
When SEN is HIGH, the programmable registers retains the previous
settings andnooffsets areloaded. SEN functions thesamewayinbothIDT
StandardandFWFTmodes.
PROGRAMMABLEFLAGMODE(PFM)
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram-
mableflagtimingmode. AHIGHonPFMwillselectSynchronousProgrammable
flagtimingmode. IfasynchronousPAF/PAEconfigurationisselected(PFM,
LOWduringMRS),thePAEisassertedLOWontheLOW-to-HIGHtransition
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
OUTPUT ENABLE ( OE )
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
17
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand indicatingthelastwordwasread. FurtherdatareadsareinhibiteduntilORgoes
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. LOWagain. SeeFigure10,ReadTiming(FWFTMode),fortherelevanttiming
If synchronous PAE/PAF configuration is selected (PFM, HIGH during information.
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand
notWCLK. Similarly,PAFisassertedandupdatedontherisingedgeofWCLK
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode,EFisadoubleregister-bufferedoutput. InFWFT
onlyandnotRCLK. The mode desiredis configuredduringmasterresetby mode,ORisatripleregister-bufferedoutput.
thestateoftheProgrammableFlagMode(PFM)pin.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
INTERSPERSED PARITY (IP)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode. reaches the almost-full condition. In IDT Standard mode, if no reads are
A HIGHwillselectInterspersedParitymode. TheIPbitfunctionallowstheuser performedafterreset(MRS),PAFwillgoLOWafter(D-m)wordsarewritten
toselecttheparitybitinthelongwordloadedintotheparallelport(D0-Dn)when tothe FIFO. The PAF willgoLOWafter(512-m)writes forthe IDT72V7230,
programmingtheflagoffsets. IfInterspersedParitymodeisselected,thenthe (1,024-m)writesfortheIDT72V7240,(2,048-m)writesfortheIDT72V7250,
FIFOwillassumethattheparitybitsarelocatedinbitpositionD8,D17,D26,D35, (4,096-m)writesfortheIDT72V7260,(8,192-m)writesfortheIDT72V7270,
D44, D53, D62 andD71 duringthe parallelprogrammingofthe flagoffsets. If (16,384-m)writesfortheIDT72V7280,(32,768-m)writesfortheIDT72V7290,
Non-InterspersedParitymodeisselected,thenD8,D17andD28areisassumed and(65,536-m)writesfortheIDT72V72100. Theoffset“m”isthefulloffsetvalue.
to be valid bits and D64, D65, D66, D67, D68, D69, D70 and D71 are ignored. ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
IPmode is selectedduring MasterResetbythe state ofthe IPinputpin.
InFWFTmode,thePAFwillgoLOWafter(513-m)writesfortheIDT72V7230,
(1,025-m)writesfortheIDT72V7240,(2,049-m)writesfortheIDT72V7250,
(4,097-m)writesfortheIDT72V7260and(8,193-m)writesfortheIDT72V7270,
(16,385-m)writesfortheIDT72V7280,(32,769-m)writesfortheIDT72V7290
and(65,537-m)writesfortheIDT72V72100,where“m”isthefulloffsetvalue.
ThedefaultsettingforthisvalueisstatedinTable2.
SeeFigure23,SynchronousProgrammableAlmost-FullFlagTiming(IDT
StandardandFWFTModes),fortherelevanttiminginformation.
IfasynchronousPAFconfigurationisselected,the PAFisassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). IfsynchronousPAF
configurationisselected,thePAFisupdatedontherisingedgeofWCLK. See
Figure25,AsynchronousAlmost-FullFlagTiming(IDTStandardandFWFT
Modes).
OUTPUTS:
FULL FLAG ( FF/IR )
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFF isHIGH,theFIFOisnotfull. Ifnoreadsareperformed
after a reset (eitherMRS orPRS), FF willgoLOWafterDwrites tothe FIFO
(D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the
IDT72V7250,4,096fortheIDT72V7260,8,192fortheIDT72V7270,16,384
for the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the
IDT72V72100). See Figure10, Write Cycle and Full Flag Timing (IDT
StandardMode),fortherelevanttiminginformation.
InFWFTmode, the InputReady(IR)functionis selected. IR goes LOW
whenmemoryspaceis availableforwritingindata. Whenthereis nolonger
anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterDwrites
tothe FIFO(D=513forthe IDT72V7230, 1,025forthe IDT72V7240, 2,049
for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270,
16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the
IDT72V72100). SeeFigure13,WriteTiming(FWFTMode),fortherelevant
timinginformation.
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
reachesthealmost-emptycondition. InIDTStandardmode,PAEwillgoLOW
whentherearenwords orless intheFIFO. Theoffset“n”is theemptyoffset
value. ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
inthe FIFO. The defaultsettingforthis value is statedinTable 2.
See Figure 24, Synchronous Programmable Almost-EmptyFlagTiming
(IDTStandardandFWFTModes), forthe relevanttiminginformation.
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). IfsynchronousPAE
configurationisselected,thePAEisupdatedontherisingedgeofRCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Modes).
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
countsthepresenceofawordintheoutputregister. Thus,inFWFTmode,the
totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
assert FF in IDT Standard mode.
FF/IRissynchronousandupdatedontherisingedgeofWCLK. FF/IRare
doubleregister-bufferedoutputs.
EMPTY FLAG (EF/OR )
Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF)
functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
read operations. When EF is HIGH, the FIFO is not empty. See Figure 11,
ReadCycle,OutputEnable,EmptyFlagandFirstWordLatencyTiming(IDT
StandardMode),fortherelevanttiminginformation.
InFWFTmode,theOutputReady(OR)functionisselected. ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
thelastwordfromtheFIFOmemorytotheoutputs. ORgoesHIGHonlywith
atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs,
HALF-FULL FLAG ( HF )
Thisoutputindicatesahalf-fullFIFO. TherisingWCLKedgethatfillstheFIFO
beyondhalf-fullsetsHFLOW. TheflagremainsLOWuntilthedifferencebetween
thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 512 for the
IDT72V7230,1,024fortheIDT72V7240,2,048fortheIDT72V7250,4,096for
18
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
the IDT72V7260, 8,192 for the IDT72V7270, 16,384 for the IDT72V7280,
32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes),
fortherelevanttiminginformation. BecauseHFisupdatedbybothRCLKand
In FWFT mode, if no reads are performed after reset (MRS orPRS), HF WCLK,itisconsideredasynchronous.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 513 for the
IDT72V7230,1,025fortheIDT72V7240,2,049fortheIDT72V7250,4,097for DATAOUTPUTS(Q0-Qn)
the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280,
32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
(Q0-Q71)aredataoutputsfor72-bitwidedata,(Q0-Q35)aredataoutputs
for 36-bit wide data or (Q0-Q17) are data outputs for 18-bit wide data.
19
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
D71-D54
D53-D36
D35-D18
D17-D0
BYTE ORDER ON INPUT PORT:
Write to FIFO
A
B
C
D
BYTE ORDER ON OUTPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM
IW
X
OW
X
A
B
C
D
Read from FIFO
X
L
(a) x72 INPUT to x72 OUTPUT
Q71-Q54
Q71-Q54
Q53-Q36
Q53-Q36
Q35-Q18
Q17-Q0
BE BM
IW
L
OW
L
1st: Read from FIFO
2nd: Read from FIFO
A
B
L
H
Q35-Q18
Q17-Q0
C
D
(b) x72 INPUT to x36 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM
IW
L
OW
L
1st: Read from FIFO
2nd: Read from FIFO
C
D
H
H
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
A
B
(c) x72 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Q71-Q54
Q71-Q54
Q71-Q54
Q71-Q54
Q53-Q36
Q53-Q36
Q53-Q36
Q53-Q36
Q35-Q18
Q35-Q18
Q35-Q18
Q35-Q18
Q17-Q0
BE BM
IW
L
OW
H
A
1st: Read from FIFO
2nd: Read from FIFO
L
H
Q17-Q0
B
Q17-Q0
C
3rd: Read from FIFO
4th: Read from FIFO
Q17-Q0
D
(d) x72 INPUT to x18 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM
IW
L
OW
H
D
1st: Read from FIFO
H
H
Q71-Q54
Q71-Q54
Q71-Q54
Q53-Q36
Q53-Q36
Q53-Q36
Q35-Q18
Q35-Q18
Q35-Q18
Q17-Q0
2nd: Read from FIFO
3rd: Read from FIFO
C
Q17-Q0
B
Q17-Q0
A
4th: Read from FIFO
(e) x72 INPUT to x18 OUTPUT - LITTLE-ENDIAN
4680 drw08
Figure 4. Bus-Matching Byte Arrangement
20
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
BYTE ORDER ON INPUT PORT:
D71-D54
D53-D36
D35-D18
D17-D0
A
1st: Write to FIFO
2nd: Write to FIFO
B
D71-D54
D53-D36
D35-D18
D17-D0
C
D
BYTE ORDER ON OUTPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
L
B
D
A
C
Read from FIFO
Read from FIFO
L
H
H
(a) x36 INPUT to x72 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
L
D
B
C
A
H
H
H
(b) x36 INPUT to x72 OUTPUT - LITTLE-ENDIAN
BYTE ORDER ON INPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
A
1st: Write to FIFO
2nd: Write to FIFO
Q71-Q54
Q71-Q54
Q53-Q36
Q53-Q36
Q35-Q18
Q35-Q18
Q17-Q0
B
Q17-Q0
C
3rd: Write to FIFO
4th: Write to FIFO
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
D
BYTE ORDER ON OUTPUT PORT:
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
H
A
B
C
D
Read from FIFO
L
H
H
(a) x18 INPUT to x72 OUTPUT - BIG-ENDIAN
Q71-Q54
Q53-Q36
Q35-Q18
Q17-Q0
BE BM IW
OW
H
C
A
D
B
Read from FIFO
H
H
H
(b) x18 INPUT to x72 OUTPUT - LITTLE-ENDIAN
4680 drw09
Figure 4. Bus-Matching Byte Arrangement (Continued)
21
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
JTAGTIMINGSPECIFICATION
tTCK
t
4
t
3
t
1
t
2
TCK
TDI/
TMS
tDS
tDH
TDO
TDO
t
6
tDO
TRST
Notes to diagram:
t1 = tTCKLOW
4680 drw10
t2 = tTCKHIGH
t
5
t3 = tTCKFALL
t4 = tTCKRise
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 5. Standard JTAG Timing
JTAGACELECTRICAL
CHARACTERISTICS
(vcc = 3.3V ± 5%; Tcase = 0°C to +85°C)
SYSTEMINTERFACEPARAMETERS
IDT72V7230
IDT72V7240
IDT72V7250
IDT72V7260
IDT72V7270
IDT72V7280
IDT72V7290
IDT72V72100
Parameter
Symbol
Test
Conditions
Min. Max. Units
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRise
tTCKFall
tRST
-
Parameter
DataOutput
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
tDO = Max
5(1)
5
50
-
ns
ns
ns
-
2
DataOutputHold
DataInput
tDOH
50
50
tDS
tDH
trise=3ns
tfall=3ns
30
30
-
-
JTAG Reset Recovery
tRSR
-
NOTES:
1. Guaranteed by design.
2. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
22
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAG Interface
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V7230/72V7240/
72V7250/72V7260/72V7270/72V7280/72V7290/72V72100 incorporates
thenecessarytapcontrollerandmodifiedpadcellstoimplementtheJTAG facility.
The JTAG boundary scan should only be used when the IDT72V7230/
72V7240/72V7250/72V7260/72V7270/72V7280/72V7290/72V72100 is in
theresetmode.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
ThefigurebelowshowsthestandardBoundary-ScanArchitecture
StandardJTAGinterface is usedforBoundaryScanpurposes while the
IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/72V7290/
72V72100is heldinthe resetmode.
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
4680 drw11
Figure 6. Boundary Scan Architecture
TEST ACCESS PORT (TAP)
THETAPCONTROLLER
The Tap interface is a general-purpose port that provides access to the
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST) TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
and one output port (TDO).
andDataRegisters forcaptureandupdateofdata.
23
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-DR
Pause-IR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
4680 drw12
Figure 7. TAP Controller State Diagram
EXIT1-DR / EXIT2-DR
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determines thestateprogression
that occurs on each TCLK rising edge.
Thisisatemporarycontrollerstate. IfTMSisheldhigh,arisingedgeapplied
toTCKwhileinthisstatecausesthecontrollertoentertheUpdate-DRstate. This
terminatesthescanningprocess. Alltestdataregistersselectedbythecurrent
instructionretaintheirpreviousstateunchanged.
PAUSE-DR
CAPTURE-DR
Thiscontrollerstateallowsshiftingofthetestdataregisterintheserialpath
betweenTDIandTDOtobetemporarilyhalted. Alltestdataregistersselected
bythecurrentinstructionretaintheirpreviousstateunchanged.
Data is loaded from the parallel input pins or core outputs into the Data
Register.
SHIFT-DR
Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are
similartoDataregisters.Theseinstructionsoperateontheinstructionregisters.
Thepreviouslycaptureddataisshiftedinserially,LSBfirstattherisingedge
ofTCLKintheTDI/TDOpathandshiftedoutserially,LSBfirstatthefallingedge
ofTCLKtowardstheoutput.
UPDATE-DR
The shifting process has been completed. The data is latched into their
paralleloutputsinthisstatetobeaccessedthroughtheinternalbus.
24
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
THE INSTRUCTION REGISTER
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
31(MSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0 0X33
28 27
12 11
1 0(LSB)
1
IDT72V7230/40/50/60/70/80/90/100 JTAG Device Identification Register
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
TESTDATAREGISTER
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
•
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
TheInstructionRegisterisa4bitfield(i.e.IR3,IR2,IR1,IR0)todecode16
differentpossibleinstructions. Instructionsaredecodedasfollows.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
TABLE 1 JTAG INSTRUCTION REG-
ISTERDECODING
Hex
Instruction
Function
Value
0x00
0x02
0x01
0x03
0x0F
TEST BYPASS REGISTER
EXTEST
IDCODE
SAMPLE/PRELOAD
HI-Z
BYPASS
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
SelectBoundaryScanRegister
JTAG
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
SelectBypassRegister
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
EXTEST
The mandatoryEXTESTinstructionis providedforexternalcircuityand
boardlevelinterconnectioncheck.
THE DEVICE IDENTIFICATION REGISTER
IDCODE
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
ThisinstructionisprovidedtoselectDeviceIdentificationRegistertoread
outmanufacture’sidentity,partnumberandversionnumber.
SAMPLE/PRELOAD
ThemandatorySAMPLE/PRELOADinstructionallowsdatavaluestobe
loadedontothelatchedparalleloutputsoftheboundary-scanshiftregisterprior
toselectionofthe boundary-scantestinstruction. The SAMPLEinstruction
allowsasnapshotofdataflowingfromthesystempinstotheon-chiplogicorvice
versa.
For the IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100,thePartNumberfieldcontainsthefollowingvalues:
Device
Part# Field
0x57
IDT72V7230
IDT72V7240
IDT72V7250
IDT72V7260
IDT72V7270
IDT72V7280
IDT72V7290
IDT72V72100
0x51
0x52
0x53
0x54
0x55
0x56
0x50
HIGH Z
Thisinstructionplacesalltheoutputpinsonthedeviceintoahighimpedance
state.
BYPASS
TheBypassinstructioncontainsasingleshift-registerstageandissetto
provideaminimum-lengthserialpathbetweentheTDIandtheTDOpinsofthe
device whennotest operation ofthe device is required.
25
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
tRS
MRS
REN
t
RSR
RSR
t
RSS
RSS
t
t
WEN
tRSR
tRSS
FWFT/SI
tRSS
tRSR
LD
tRSS
FSEL0,
FSEL1
tRSS
tRSS
tRSS
tRSS
BM,
OW, IW
BE
RM
PFM
tRSS
IP
RT
t
RSS
RSS
t
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
EF/OR
t
RSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4680 drw13
Figure 8. Master Reset Timing
26
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4680 drw 14
Figure 9. Partial Reset Timing
27
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKH
t
CLKL
NO WRITE
NO WRITE
WCLK
2
1
(1)
1
(1)
2
t
SKEW1
t
DH
t
SKEW1
tDS
t
DH
tDS
DX+1
DX
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
t
ENH
tENH
REN
RCS
tRCSS
tA
tA
Q0
- Qn
NEXT DATA READ
DATA READ
4680 drw15
tRCSLZ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 10. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
tENS
1
2
RCLK
REN
tENH
tENS
tENS
tENH
tENH
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
tA
D0
LAST WORD
D1
LAST WORD
Q0 - Qn
tOLZ
tOHZ
t
OLZ
tOE
OE
WCLK
WEN
tSKEW1(1)
tENS
tENS
tENH
tDH
tENH
tDH
tDS
tDS
D0
D1
D0 - Dn
4680 drw16
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. RCS is LOW.
Figure 11. Read Cycle, Output Enable, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
28
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
2
1
RCLK
tENS
REN
RCS
tRCSH
tRCSS
tRCSS
tRCSS
tREF
tREF
EF
tRCSHZ
tRCSHZ
tA
tA
tRCSLZ
tRCSLZ
LAST DATA-1
LAST DATA
Q0 - Qn
t
SKEW1(1)
WCLK
tENS
tENH
WEN
tDS
tDH
Dn
Dx
4680 drw 17
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. OE is LOW.
Figure 12. Read Cycle and Read Chip Select Timing (IDT Standard Mode)
29
1
WCLK
tENS
WEN
tDS
tDS
tDS
tDS
tDH
tENH
D-1
D-1
D-1
WD
W3
W[n+4]
W[D-m-2]
W1
W
2
W4
W[n +2]
W
[n+3]
[
]
[
]
[
W
]
W[D-m-1]
W[D-m]
W[D-m+1]
W[D-m+2]
W[D-1]
W
W
D0 - Dn
(2)
tSKEW2
t
SKEW1(1)
2
1
3
1
2
RCLK
RCS
REN
t
RCSS
tRCSLZ
tA
Q0 - Qn
W1
PREVIOUS DATA IN OUTPUT REGISTER
t
REF
OR
t
PAES
PAE
tHF
HF
t
PAFS
PAF
IR
t
WFF
4680 drw 18
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than tSKEW1, then OR assertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 513 for IDT72V7230, 1,025 for IDT72V7240, 2,049 for IDT72V7250, 4,097 for IDT72V7260, 8,193 for IDT72V7270, 16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
Figure 13. Write Timing (First Word Fall Through Mode)
WCLK
1
2
(2)
(1)
tSKEW1
tSKEW2
tENS
tDS
tENH
tDH
WEN
WD
D0 - Dn
1
RCLK
tENS
tENS
REN
OE
tOHZ
tOE
W1
tA
tA
tA
tA
tA
tA
W[m+3]
WD
Wm+2
W[D-1
]
W[D-1
]
W[D-n-1]
W[D-n]
W1
W2
W3
W[m+4]
W[D-n+1]
W[D-n+2]
W[D-1]
Q0 - Qn
tREF
OR
tPAES
PAE
tHF
HF
tPAFS
PAF
IR
tWFF
tWFF
4680 drw 19
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 513 for IDT72V7230, 1,025 for IDT72V7240, 2,049 for IDT72V7250, 4,097 for IDT72V7260, 8,193 for IDT72V7270, 16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
6. RCS = LOW.
Figure 14. Read Timing (First Word Fall Through Mode)
WCLK
1
2
(2)
(1)
tSKEW2
tENS
tENH
tSKEW1
WEN
tDS
tDH
WD
D0 - Dn
1
RCLK
tENS
tENS
tRCSS
REN
RCS
tRCSH
tRCSHZ
tA
tRCSLZ
tA
tA
tA
tA
D-1
D-1
[
]
[
]
WD
W1
W2
W3
W[m+3]
W[m+4]
W[D-n+1]
W[D-n+2]
W[D-1]
Wm+2
W
W
W[D-n-1]
W[D-n]
Q0 - Qn
t
REF
OR
PAE
HF
t
PAES
tHF
t
PAFS
PAF
IR
t
WFF
t
WFF
4680 drw 20
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 513 for IDT72V7230, 1,025 for IDT72V7240, 2,049 for IDT72V7250, 4,097 for IDT72V7260, 8,193 for IDT72V7270, 16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
6. OE = LOW.
Figure 15. Read Cycle and Read Chip Select Timing (First Word Fall Through Mode)
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
RCLK
1
2
tENS
tENH
tENS
tENH
tRTS
REN
tA
tA
tA
2(3)
W
1(3)
0 n
Q - Q
W
x
W
x+1
W
tSKEW2
1
2
WCLK
tRTS
WEN
RT
tENH
tENS
tREF
tREF
EF
PAE
HF
tPAES
tHF
tPAFS
PAF
4680 drw21
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW; RCS = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 512 for IDT72V7230, 1,024 for IDT72V7240, 2,048 for IDT72V7250, 4,096 for IDT72V7260, 8,192 for IDT72V7270, 16,384 for the IDT72V7280, 32,768 for the IDT72V7290
and 65,536 for the IDT72V72100.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 16. Retransmit Timing (IDT Standard Mode)
33
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
3
1
2
4
RCLK
tENH
tENH
tENS
tENS
tRTS
REN
tA
tA
tA
tA
(4)
Q0 - Qn
Wx+1
Wx
W
1(4)
W
2 (4)
W3
W4
tSKEW2
1
2
WCLK
tRTS
WEN
tENH
tENS
RT
OR
tREF
tREF
tPAES
PAE
tHF
HF
tPAFS
PAF
4680 drw22
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280, 32,769 for
the IDT72V7290 and 65,537 for the IDT72V72100.
3. OE = LOW; RCS = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 17. Retransmit Timing (FWFT Mode)
34
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
1
2
3
RCLK
t
ENH
t
ENS
REN
t
A
t
A
tA
t
A
t
A
(3)
2
(3)
1
Q0 - Qn
W
3
W
Wx
W0
W
Wx+1
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
EF
t
PAES
PAE
tHF
HF
t
PAFS
PAF
4680 drw23
NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW; RSC = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 512 for IDT72V7230, 1,024 for IDT72V7240, 2,048 for IDT72V7250, 4,096 for IDT72V7260, 8,192 for IDT72V7270, 16,384 for the IDT72V7280, 32,768 for the IDT72V7290
and 65,536 for the IDT72V72100.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 18. Zero Latency Retransmit Timing (IDT Standard Mode)
35
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
4
1
2
5
3
RCLK
t
ENH
t
ENS
REN
t
A
t
A
t
A
tA
t
A
(4)
(4)
(4)
Q0 - Qn
Wx
Wx+1
W3
W1
W
2
W
4
W5
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
t
ENH
RT
OR
t
PAES
PAE
HF
tHF
t
PAFS
PAF
4680 drw24
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280, 32,769 for
the IDT72V7290 and 65,537 for the IDT72V72100.
3. OE = LOW; RCS = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 19. Zero Latency Retransmit Timing (FWFT Mode)
SCLK
t
ENH
LDH
t
t
ENS
LDS
t
ENH
SEN
LD
t
t
LDH
tDH
t
DS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4680 drw25
FULL OFFSET
EMPTY OFFSET
NOTE:
1. X = 8 for the IDT72V7230, X= 9 for the IDT72V7240, X = 10 for the IDT72V7250, X = 11 for the IDT72V7260, X = 12 for the IDT72V7270, X = 13 for the IDT72V7280, X = 14 for
the IDT72V7290 and X = 15 for the IDT72V72100.
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
36
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDH
t
LDS
t
LDH
ENH
t
t
ENH
t
ENS
WEN
t
DS
tDH
t
DH
PAF
OFFSET
PAE
OFFSET
D0 - Dn
4680 drw26
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
CLKL
t
CLKH
RCLK
t
LDS
t
LDH
t
t
LDH
ENH
LD
t
ENS
t
ENH
REN
t
A
t
A
DATA IN OUTPUT REGISTER
PAE OFFSET
PAF OFFSET
Q0
- Q16
4680 drw27
NOTES:
1. OE = LOW; RCS = LOW.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLKL
tCLKL
1
2
WCLK
WEN
PAF
2
1
tENS
tENH
t
PAFS
t
PAFS
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
t
SKEW2(3)
RCLK
tENS
tENH
4680 drw 28
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250, 4,096 for the IDT72V7260 and 8,192 for the IDT72V7270, 16,384 for
the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
In FWFT mode: D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280,
32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
37
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
SKEW2(4)
t
PAES
t
PAES
t
1
2
1
2
RCLK
tENS
tENH
4680 drw29
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS is LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words
in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
4680 drw30
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250, 4,096 for the IDT72V7260, 8,192 for the IDT72V7270, 16,384 for the
IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
In FWFT Mode: D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270, 16,385 for the IDT72V7280,
32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
38
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
(2)
(2)
tPAEA
n words in FIFO
,
n words in FIFO
,
(2)
n+1wordsinFIFO
,
(3)
(3)
PAE
RCLK
REN
n + 1 words in FIFO
n + 1 words in FIFO
(3)
n+2wordsinFIFO
tPAEA
tENS
4680 drw 31
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D-1
2
[
+ 2]
words in FIFO(2)
D-1
D-1
2
[
+ 1
]
words in FIFO(2)
[
+ 1
]
words in FIFO(2)
2
tHF
RCLK
tENS
REN
4680 drw32
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 512 for the IDT72V7230, 1,024 for the IDT72V7240, 2,048 for the IDT72V7250,4,096 for the IDT72V7260, 8,192 for the
IDT72V7270, 16,384 for the IDT72V7280, 32,768 for the IDT72V7290 and 65,536 for the IDT72V72100.
2. In FWFT mode: D = maximum FIFO depth. D = 513 for the IDT72V7230, 1,025 for the IDT72V7240, 2,049 for the IDT72V7250, 4,097 for the IDT72V7260, 8,193 for the IDT72V7270,
16,385 for the IDT72V7280, 32,769 for the IDT72V7290 and 65,537 for the IDT72V72100.
Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)
39
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
avoided by creating composite flags, that is, ANDingEF of every FIFO, and
separatelyANDingFFofeveryFIFO. InFWFTmode,compositeflagscanbe
createdbyORingORofeveryFIFO,andseparatelyORingIRofeveryFIFO.
Figure 28 demonstrates a width expansion using two IDT72V7230/
72V7240/72V7250/72V7260/72V7270/72V7280/72V7290/72V72100 de-
vices. D0 - D71 from each device form a 144-bit wide input bus and Q0-Q71
fromeachdeviceforma144-bitwideoutputbus.Anywordwidthcanbeattained
by adding additional IDT72V7230/72V7240/72V7250/72V7260/72V7270/
72V7280/72V7290/72V72100devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
READ SHIP SELECT (RCS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
IDT
IDT
READ ENABLE (REN)
OUTPUT ENABLE (OE)
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
FIFO
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
FIFO
PROGRAMMABLE (PAE)
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
#1
DATA OUT
#2
m
4680 drw 33
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 28. Block Diagram of 512 x 144, 1,024 x 144, 2,048 x 144, 4,096 x 144, 8,192 x 144, 16,384 x 144, 32,768 x 144 and 65,536 x 144 Width
Expansion
40
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72 AND 64K x 72
COMMERCIALTEMPERATURERANGE
FWFT/SI
TRANSFER CLOCK
READ CLOCK
FWFT/SI
FWFT/SI
RCLK
WRITE CLOCK
WCLK
WEN
IR
RCLK
WCLK
READ CIP SELECT
IDT
IDT
RCS
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
WRITE ENABLE
INPUT READY
OR
WEN
READ ENABLE
REN
OR
OUTPUT READY
REN
RCS
OE
IR
OUTPUT ENABLE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
4680 drw34
Figure 29. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72, 32,768 x 72, 65,572 x 72 and 131,072 x 72 Depth
Expansion
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towrite a wordtofillit.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72V7230 can easily be adapted to applications requiring depths
greater than 512, 1,024 for the IDT72V7240, , 2,048 for the IDT72V7250,
4,096 for the IDT72V7260, 8,192 for the IDT72V7270, 16,384 for the
IDT72V7280,32,768fortheIDT72V7290and65,536fortheIDT72V72100
withan18-bitbuswidth.InFWFTmode,theFIFOscanbeconnectedinseries
(thedataoutputsofoneFIFOconnectedtothedatainputsofthenext)withno
externallogicnecessary. Theresultingconfigurationprovides atotaldepth
equivalenttothesumofthedepthsassociatedwitheachsingleFIFO. Figure
29 shows a depth expansion using two IDT72V7230/72V7240/72V7250/
72V7260/72V7270/72V7280/72V7290/72V72100devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain – no read operation is
necessarybutthe RCLKofeachFIFOmustbe free-running. Eachtime the
datawordappearsattheoutputsofoneFIFO,thatdevice'sORlinegoesLOW,
enabling a write to the next FIFO in line.
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
41
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
BB
Commercial (0°C to +70°C)
Fine Pitch Ball Grid Array (PBGA, BB256−1)
10
15
Clock Cycle Time (tCLK)
Commercial
Speed in Nanoseconds
L
Low Power
72V7230
72V7240
72V7250
72V7260
72V7270
72V7280
72V7290
72V72100
512 x 72
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
16,384 x 72
32,768 x 72
65,536 x 72
3.3V SuperSync II FIFO
NOTE:
4680 drw35
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
6/01/2000
11/1/00
pg. 1, 2, 3, 7, 33, 34, 34, 35, 38, 41 and 42
pg. 1, 2 and 42
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for Tech Support:
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email:FIFOhelp@idt.com
www.idt.com*
PBGAPkg: www.idt.com/docs/PSC4081.pdf
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
42
相关型号:
72V73273BBBLANK
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS
IDT
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