72V73263BB [IDT]
Digital Time Switch, PBGA208, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208;
| 型号： | 72V73263BB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Digital Time Switch, PBGA208, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208 电信 电信集成电路 |
| 文件： | 总36页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE
MATCHING 16,384 X 16,384 CHANNELS
IDT72V73263
•
Selectable Synchronous and Asynchronous Microprocessor
bus timing modes
IEEE-1149.1 (JTAG) Test Port
Availablein208-pin(17mmx17mm)PlasticBallGridArray(PBGA)
Operating Temperature Range -40°C to +85°C
FEATURES:
•
•
•
Up to 64 serial input and output streams
Maximum 16,384 x 16,384 channel non-blocking switching
Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,
16.384Mb/s or 32.768Mb/s
•
•
•
•
•
Rate matching capability: rate selectable on both RX and TX
in eight groups of 8 streams
Optional Output Enable Indication Pins for external driver
High-Z control
Per-channel Variable Delay Mode for low-latency applications
Per-channel Constant Delay Mode for frame integrity applications
Enhanced Block programming capabilities
TX/RX Internal Bypass
Automatic identification of ST-BUS and GCI serial streams
Per-stream frame delay offset programming
Per-channel High-Impedance output control
Per-channelprocessormodetoallowmicroprocessor writestoTX
streams
DESCRIPTION:
TheIDT72V73263hasanon-blockingswitchcapacityof 16,384x16,384
channelsat32.768Mb/s.With64inputsand64outputs,programmableper
streamcontrol, andavarietyofoperatingmodestheIDT72V73263is
designed for the TDM time slot interchange function in either voice or data
applications.
•
•
•
•
•
•
•
•
Some of the main features of the IDT72V73263 are LOW power 3.3 Volt
operation,automaticST-BUS® /GCIsensing,memoryblockprogramming,
simplemicroprocessorinterface,JTAGTestAccessPort(TAP)andper
stream programmable input offset delay, variable or constant throughput
modes,outputenableandprocessormode,BERtesting, bypassmode,and
advancedblockprogramming.
•
•
Bit Error Rate Testing (BERT) for testing
Direct microprocessor access to all internal memories
FUNCTIONALBLOCKDIAGRAM
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS isatrademarkofMitelCorp.
September 2007
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
DSC-6160/4
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
PINCONFIGURATIONS
A1 BALL PAD CORNER
A
RX1
RX2
RX4
RX5
RX6
RX7
TX0
TX1
TX2
TX3
TX4
TX7
TX12/ TX15/ RX11 RX15
OEI4 OEI7
RX20
RX19
TX16
RX23
TX18
TX17
TX22
TX19
TX20
TX21
RESET
Vcc
C32i
F32i
ODE
RX0
B
C
D
E
F
TX8/
OEI0
TX11/ TX14/
OEI3 OEI6
RX10
RX14
TX5
TX6
S/A(1)
TDO
TMS
TCK
TDI
TX9/
OEI1 OEI2
TX10/ TX13/ RX9
OEI5
RX13 RX18
RX3
RX22
RX21
TRST
DS
VCC
RX17
RX16
VCC
VCC
VCC
RX8
RX12
TX24/ TX23
OEI16
A0
A4
TX26/
OEI18
A1
A5
TX27/
OEI19
TX25/
OEI17
CS
A2
R/W
A3
TX31/ TX30/
OEI23 OEI22
TX29/
OEI21
TX28/
OEI20
G
H
J
A6
A7
A8
V
CC
GND
GND
GND
GND
RX25
V
CC
RX26
RX29
RX30
RX24
RX27
RX32
A9
A10
A13
A11
A12
VCC
GND
GND
GND
GND
VCC
GND
GND
GND
GND
RX28
RX31
VCC
A14
VCC
K
L
D15
D12
DTA/
BEH
A15
V
CC
GND
GND
GND
V
CC
RX33
RX34
RX35
GND
BEL
RX38
TX34
TX38
RX39
TX35
TX39
D13
D9
D14
D10
D7
RX36
TX32
TX36
RX37
TX33
M
N
P
R
T
D8
D5
D11
D6
RX56 TX60/ TX56/
OEI52 OEI48
VCC
VCC
VCC
VCC
RX51
RX50
RX47
RX46
RX45
RX44
TX37
D4
RX60
RX57
RX58
TX57/
OEI49
TX53
TX50
TX49
TX42/
OEI34
D3
TX61/
OEI53
RX54
RX53
RX52
TX40/
TX41/
OEI32 OE33
RX43
RX63
D0
RX61
RX62
TX62/ TX58/ TX54
OEI54 OEI50
TX48
RX55
RX49
RX48
RX42 RX40
TX46/ TX43/
OEI38 OEI35
D2
D1
TX51
TX52
RX41 TX47/ TX45/ TX44/
OEI39 OEI37 OEI36
RX59 TX63/ TX59/
OEI55 OEI51
TX55
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6160 drw03
NOTE:
1. S/A should be tied directly to VCC or GND for proper
operation.
PBGA: 1mm pitch, 17mm x 17mm (BB208-1 order code: BB)
TOP VIEW
2
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
PINDESCRIPTION
SYMBOL
NAME
I/O
PBGA
DESCRIPTION
PIN NO.
A0-A15
Address0-15
I
*See PBGA Theseaddresslinesaccessallinternalmemories.
TableBelow
BEL
Byte Enable LOW
Clock
I
I
L4
In synchronous mode, this input will enable the lower byte (D0-7) on to the data bus.
C32i
A1
Serialclockforshiftingdatain/outontheserialdatastreams. Thisinputacceptsa
32.768MHz clock.
CS
ChipSelect
DataBus0-15
DataStrobe
I
E1
ActiveLOWinputusedbyamicroprocessortoactivatethemicroprocessorportofthe
device.
D0-15
DS
I/O
I
*See PBGA Thesepinsarethedatabusofthemicroprocessorport.
TableBelow
This active LOW input works in conjunction with CSto enable the read and write
D4
K2
operations. ThisactiveLOWinputsetsthedatabuslines(D0-D15).
DTA/BEH
DataTransfer
Acknowledgment
ActiveLOWOutput
I/O
In asynchronousmodethispinindicatesthatadatabustransferiscomplete.Whenthe
bus cycle ends,this pin drives HIGH and then High-Z allowing for faster bus cycles
with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level
when the pin is High-Z. When the device is in /Byte Enable HIGH synchronous
bus mode, this pin acts as an input and will enable the upper byte (D8-15) on to the
databus.
F32i
FramePulse
I
I
B1
Thisinputacceptsandautomaticallyidentifiesframesynchronizationsignalsformatted
according to ST-BUS and GCI specifications.
GND
ODE
*See PBGA Ground.
TableBelow
OutputDriveEnable
A3
ThisistheoutputenablecontrolfortheTXserialoutputs.WhenODEinputisLOWand
the OSB bit of the CR register is LOW, all TX outputs are in a High-Impedance state. If
this input is HIGH, the TX output drivers are enabled. However, each channel may
stillbeputintoaHigh-Impedancestatebyusingtheperchannelcontrolbitsinthe
Connection Memory HIGH.
RX0-63
RX Input 0 to 63
DeviceReset:
Read/Write
I
I
*See PBGA SerialdataInputStream.Thesestreamsmayhavedataratesof2.048Mb/s,
TableBelow
4.096Mb/s,8.192Mb/s,16.384Mb/s,or32.768Mb/sdependingupontheselectioninReceive
DataRateSelectionRegister(RDRSR).
RESET
A2
Thisinput(activeLOW)putsthedeviceinitsresetstatethatclearsthedeviceinternal
counters,registersandbringsTX0-63andmicroportdataoutputstoaHigh-Impedance
state. The RESET pin must be held LOW for a minimum of 20ns to reset the device.
R/W
S/A
I
I
E2
C1
Thisinputcontrolsthedirectionofthedatabuslines(D0-D15)duringamicroprocessor
access.
Synchronous/
Asynchronous
Bus Mode
Thisinputwillselectbetweenasynchronousmicroprocessorbustimingandsynchronous
microprocessorbustiming.Insynchronousmode,DTA/BEHactsastheBEHinputandis
usedinconjunctionwithBELtooutputdataonthedatabus.Inasynchronousbusmode,
BELis tied LOW and DTA/BEHacts as the DTA, data bus acknowledgment output.
TCK
TDI
TestClock
I
I
D2
C3
Provides the clock to the JTAG test logic.
TestSerialDataIn
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH
byaninternalpull-upwhennotdriven.
TDO
TestSerialDataOut
TestModeSelect
TestReset
O
I
D1
C2
D3
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in
High-ImpedancestatewhenJTAGscanisnotenabled.
TMS
TRST
JTAGsignalthatcontrolsthestatetransitionsoftheTAPcontroller.Thispinispulled
HIGH by an internal pull-up when not driven.
I
AsynchronouslyinitializestheJTAGTAPcontrollerbyputtingitintheTest-Logic-
Resetstate.Thispinispulledbyaninternalpull-upwhennotdriven.Thispinshould
be pulsed LOW on power-up, or held LOW, to ensure that the device is in the normal
functionalmode.
3
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
PINDESCRIPTION(CONTINUED)
SYMBOL
NAME
I/O
PBGA
DESCRIPTION
PIN NO.
TX0-7
TXOutput
O
*See PBGA
TableBelow
SerialdataOutputStream.Thesestreamsmayhavedataratesof2.048Mb/s,
4.096Mb/s,8.192Mb/s,16.384Mb/s,or32.768Mb/sdependingupontheselectionin
TransmitDataRateSelectionRegister(TDRSR).IfG0/G2/G4/G6areprogrammedto
32.768Mb/smodethecorrespondingoddgroupisunavailable(G1/G3/G5G7).
TX16-23
TX32-39
TX48-55
TX8-15/OEI0-7
TX24-31/OEI16-23 EnableIndication
TX40-47/OEI32-39
TXOutput/Output
O
*See PBGA
TableBelow
WhenoutputstreamsareselectedviaTDRSR,thesepinsaretheTXoutputstreams.
Whenoutputenableindicationfunctionisselected,thesepinsreflecttheactiveorHigh-
ImpedancestatusforthecorrespondingTXoutputstream.
TX56-63/OEI48-55
VCC
*See PBGA
TableBelow
+3.3 Volt Power Supply.
PBGA PIN NUMBER TABLE
SYMBOL
A0-A15
D0-D15
GND
NAME
I/O
PIN NUMBER
AddressA0-15
DataBus0-15
Ground
I
E3, E4, F1, F2, F3, F4, G1, G2, G3, H1, H2, H3, J3, J2, J1, K3.
T2, T1, R1, P1, P2, N1, N2, N3, M1, M2, M3, M4, L1, L2, L3, K1.
G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10,K7, K8, K9, K10,
I/O
RX0-63
RX Input 0 to 63
I
B3, A4, B4, C4, A5, B5, C5, D5, D11, C11, B11, A11, D12, C12, B12, A12, E13, D13, C13, B13, A13, D14, C14 , B14,
G16, G15, G14, H16, H15, H14, J14, J15, J16, K14, K15, K16, L13, L14, L15, L16, R14, T13, R13, P13, T12, R12, P12,
N12, T11, R11, P11, N11, T10, R10, P10, T9, N4, P4, R4, T4, P3, R3, T3, R2.
TX0-TX7
TX16-23
TX32-39
TX48-55
TXOutput
O
A6, B6, C6, D6, A7, B7, C7, A8
A14, B15, A15, A16, B16, C16, C15, D16
M13, M14, M15, M16, N13, N14, N15, N16
R9, P9, P8, R8. T8, P7, R7, T7
TX8-15/OEI0-7
TXOutput/Output
O
B8, C8, C9, B9, A9, C10, B10, A10.
D15, E16, E15, E14, F16, F15, F14, F13.
P14, P15, P16, R16, T16, T15, R15, T14.
N6, P6, R6, T6, N5, P5, R5, T5.
TX24-31/OEI16-23
TX40-47/OEI32-39
TX56-63/OEI48-55
Vcc
B2, D7, D8, D9, D10, G4, G13, H4, H13, J4, J13, K4, K13, N7, N8, N9, N10.
4
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
MOD2-0 bits are set to 0-0-1 accordingly, that particular channel will be in
ConstantDelayMode.Finally,iftheMOD2-0bitsaresetto0-0-0,thatparticular
channel will be in Variable Delay Mode.
DESCRIPTION(CONTINUED):
The IDT72V73263 is capable of switching up to 16,384 x 16,384 channels
withoutblocking.Designedtoswitch64Kbit/sPCMorNx64Kbit/sdata,the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delay for voice applications on a per-channel basis.
SERIAL DATA INTERFACE TIMING
ThemasterclockfrequencyoftheIDT72V73263is32.768MHz,C32i. For
32.768Mb/sdatarates,thisresultsinasingle-bitperclock.For16.384Mb/s,
8.192Mb/s, 4.096Mb/s, and2.048Mb/sthiswillresultintwo, four, eight, and
sixteenclocksperbit,respectively. TheIDT72V73263providestwodifferent
interface timing modes, ST-BUS or GCI. The IDT72V73263 automatically
detectsthepolarityofaninputframepulseandidentifiesitaseitherST-BUS
or GCI.
For32.768Mb/s,inST-BUS Mode,dataisclockedoutonafallingedgeand
is clocked in on the subsequent rising-edge. For 16.384Mb/s, 8.192Mb/s,
4.096Mb/s,and2.048Mb/showeverthereisnotthetypicalassociatedclock
sincetheIDT72V73263acceptsonlya32.768MHzclock. Asaresulttherewill
be 2, 4, 8, and 16 clock between the 32.768Mb/s transmit edge and the
subsequentlytransmitedges. Althoughinthisisthecase,theIDT72V73263
willappropriatelytransmitandsampleontheproperedgeasiftherespective
clock were present. See ST-BUS Timing for detail.
For 32.768Mb/s, in GCI Mode, data is clocked out on a rising edge and is
clocked in on the subsequent falling-edge. For 16.384Mb/s, 8.192Mb/s,
4.096Mb/s,and2.048Mb/showever,againthereisnotthetypicalassociated
clocksincetheIDT72V73263acceptsonlya32.768MHzclock. Asaresultthere
will2,4,8,and16clocksbetweenthe32.768Mb/stransmitedgeandtheother
transmitedges. Althoughthisisthecase,theIDT72V73263willappropriately
transmitandsampleontheproperedgeasiftherespectiveclockwerepresent.
SeeGCIBusTimingfordetail.
The 64 serial input streams (RX) of the IDT72V73263 can be run at
2.048Mb/s,4.096Mb/s,8.192Mb/s,16.384Mb/sor32.768Mb/sallowing32,
64, 128, 256or512channelsper125µsframe. Thedataratesontheoutput
streamscanindependentlybeprogrammedtorunatanyofthesedatarates.
Withtwomainoperatingmodes,ProcessorModeandConnectionMode,the
IDT72V73263 can easily switch data from incoming serial streams (Data
Memory)orfromthecontrollingmicroprocessorviaConnectionMemory.
Ascontrolandstatusinformationiscriticalindatatransmission,theProcessor
Modeisespeciallyusefulwhentherearemultipledevicessharingtheinputand
outputstreams.
With data coming from multiple sources and through different paths, data
enteringthedeviceisoftendelayed.Tohandlethisproblem,theIDT72V73263
hasaFrameOffset featuretoallowindividualstreamstobeoffsetfromtheframe
pulseinhalfclock-cycleintervalsupto+7.5clockcycles.
The IDT72V73263 also provides a JTAG test access port, memory block
programming, Group Block Programming, RX/TX internal bypass, a simple
microprocessor interface and automatic ST-BUS /GCI sensing to shorten
setup time, aid in debugging and ease use of the device without sacrificing
capabilities.
FUNCTIONALDESCRIPTION
DATAANDCONNECTIONMEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversionbeforebeingstoredintointernalDataMemory.The8 KHzframe
pulse(F32i)isusedtomarkthe125µsframeboundariesandtosequentially
addresstheinputchannelsinDataMemory.
DELAY THROUGH THE IDT72V73263
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabilities
onaper-channelbasis.Forvoiceapplications,variablethroughputdelayisbest
asitensureminimumdelaybetweeninputandoutputdata.Inwidebanddata
applications, constant throughput delay is best as the frame integrity of the
informationismaintainedthroughtheswitch.
DataoutputontheTXstreamsmaycomefromeithertheserialinputstreams
(DataMemory)orfromtheConnectionMemoryviathemicroprocessororin
thecasethatRXinputdataistobeoutput,theaddressesinConnectionMemory
areusedtospecifyastreamandchanneloftheinput.TheConnectionMemory
issetupinsuchawaythateachlocationcorrespondstoanoutputchannelfor
eachparticularstream.Inthatway,morethanonechannelcanoutputthesame
data. In Processor Mode, the microprocessor writes data to the Connection
Memorylocationscorrespondingtothestreamandchannelthatistobeoutput.
Thelowerhalf(8leastsignificantbits)oftheConnectionMemoryLOW isoutput
everyframeuntilthemicroprocessorchangesthedataormodeofthechannels.
ByusingthisProcessorModecapability,themicroprocessorcanaccessinput
andoutputtime-slotsonaper-channelbasis.
ThethreeleastsignificantbitsoftheConnectionMemoryHIGHareusedto
controlper-channelmodeoftheoutputstreams.TheMOD2-0bitsareusedto
selectProcessorMode,ConstantorVariableDelayMode,BitErrorRate,and
theHigh-Impedancestateofoutputdrivers.IftheMOD2-0bitsaresetto1-1-1
accordingly, only that particular output channel (8 bits) will be in the High-
Impedancestate. IftheMOD2-0bitsaresetto1-0-0accordingly,thatparticular
channelwillbeinProcessorMode. IftheMOD2-0bitsaresetto1-0-1aBitError
RateTest patternwillbetransmittedforthattimeslot. SeeBERTsection. Ifthe
Thedelaythroughthedevicevariesaccordingtothetypeofthroughputdelay
selectedintheMODbitsoftheConnectionMemory.
VARIABLE DELAY MODE (MOD2-0 = 0-0-0)
Inthismode,mostlyforvoiceapplicationswhereminimumthroughputdelay
is desired, delay is dependent on the combination of source and destination
channels.Theminimumdelayachievableisa3channelperiodsoftheslower
datarate.
CONSTANT DELAY MODE (MOD2-0 = 0-0-1)
Inthismode,frameintegrityismaintainedinallswitchingconfigurationsby
makinguseofamultipledatamemorybuffer.Inputchanneldataiswritteninto
thedatamemorybuffersduringframenwillbereadoutduringframen+2. In
theIDT72V73263,theminimumthroughputdelayachievableinConstantDelay
mode will be one frame plus one channel. See Table 14.
5
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
MICROPROCESSOR INTERFACE
internalmemories.TheonlywriteoperationallowedduringaSoftwareReset
The IDT72V73263’s microprocessor interface looks like a standard RAM istotheSoftwareResetbitintheControlRegistertocompletetheSoftwareReset.
interfacetoimproveintegrationintoasystem. Witha16-bitaddressbusand
a16-bitdatabusallmemoriescanbeaccessed. UsingtheTSImicroprocessor CONNECTIONMEMORYCONTROL
interface,readsandwritesaremappedintoDataandConnectionmemories.
IftheODEpinandtheOutputStandbybitareLOW,alloutputchannelswill
By allowing the internal memories to be randomly accessed, the controlling be in three-state. See Table 2 for detail.
microprocessorhasmoretimetomanageotherperipheraldevices
IfMOD2-0oftheConnectionMemoryHIGHis1-0-0accordingly,theoutput
andcanmoreeasilyandquicklygatherinformationandsetuptheswitchpaths. channel will be in Processor Mode. In this case the lower eight bits of the
Table1showsthemappingoftheaddressesintointernalmemoryblocks. In Connection Memory LOW are output each frame until the MOD2-0 bits are
ordertominimizetheamountofmemorymappedspacehowever,theMemory changed.IfMOD2-0oftheConnectionMemoryHIGHare0-0-1accordingly,
Select(MS1-0)bitsintheControlRegistermustbewrittentofirsttoselectbetween thechannelwillbeinConstantDelayModeandbits14-0areusedtoaddress
theConnectionMemoryHIGH,theConnectionMemoryLOW,orDataMemory. a location in Data Memory. If MOD2-0 of the Connection Memory HIGH are
Effectively,theMemorySelectbitsactasaninternalmuxtoselectbetweenthe 0-0-0, the channel will be in Variable Delay Mode and bits 14-0 are used to
DataMemory, ConnectionMemoryHIGH, andConnectionMemoryLOW.
addressalocationinDataMemory.IfMOD2-0oftheConnectionMemoryHIGH
are1-1-1, thechannelwillbeinHigh-Impedancemodeandthatchannelwill
beinthree-state.
MEMORYMAPPING
Theaddressbusonthemicroprocessorinterfaceselectstheinternalregisters
and memoriesoftheIDT72V73263.Themostsignificantbitoftheaddressselect RX/TX INTERNAL BYPASS
betweentheregistersandinternalmemories.SeeTable1formappings.
WhentheBypassbitofcontrolregistersis1,allRXstreamswillbe“shorted”
AsexplainedintheInitializationsection,aftersystempower-up,theTDRSR toTX ineffectbypassingallinternalcircuitryoftheTSI. Thiseffectivelysetsthe
and RDRSR, should be programmed immediately to establish the desired TSItoa1-to-1switchmodewithminimalI/Odelay. Azerocanbewrittentoallow
switchingconfiguration.
normaloperation.TheintentionofthismodeistominimizethedelayfromtheRX
The data in the Control Register consists of the Software Reset, RX/TX inputtotheTXoutputmakingtheTSI“invisible”.
Bypass,OutputEnablePolarity,AllOutputEnable,FullBlockProgramming,
BlockProgrammingData,BeginBlockProgrammingEnable,ResetConnection
MemoryLOWinBlockProgramming,OutputStandby,andMemorySelect.
INITIALIZATION OF THE IDT72V73263
Afterpowerup,thestateoftheConnectionMemoryisunknown. Assuch,the
outputsshouldbeputinHigh-ImpedancebyholdingtheODEpinLOW. While
theODEisLOW,themicroprocessorcaninitializethedevicebyusingtheBlock
Programmingfeatureandprogramtheactivepathsviathemicroprocessorbus.
Oncethedeviceisconfigured,theODEpin(orOutputStandbybitdepending
oninitialization)canbeswitchedtoenabletheTSIswitch.
SOFTWARE RESET
The Software Reset serves the same function as the hardware reset. As
withthehardreset,theSoftwareResetmustalsobesetHIGHfor20nsbefore
bringingtheSoftwareResetLOWagainfornormaloperation. OncetheSoftware
ResetisLOW,internalregistersandothermemoriesmaybereadorwritten.
During Software Reset, the microprocessor port is still able to read from all
6
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE1—ADDRESSMAPPING
A15 A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R/W Location
Hex Value
1
STA5 STA4 STA3 STA2 STA1 STA0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R/W Internal
0x8000-
0xFFFF
memory
(CM, DM
(readonly)(1)
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
R/W Control
0x00XX
Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W TDRSR0
R/W TDRSR1
R/W RDRSR0
R/W RDRSR1
R/W BPSA
0x02XX
0x04XX
0x06XX
0x08XX
0x0AXX
0x0CXX
0x-0EXX
0x10XX
0x20XX
0x22XX
0x24XX
0x26XX
0x28XX
0x2AXX
0x2CXX
0x2EXX
0x30XX
0x32XX
0x34XX
0x36XX
0x38XX
0x3AXX
0x3CXX
0x3EXX
0
0
0
0
0
R/W BPEA
0
R/W
R/W
BIS
0
BER
0
R/W FOR0
R/W FOR1
R/W FOR2
R/W FOR3
R/W FOR4
R/W FOR5
R/W FOR6
R/W FOR7
R/W FOR8
R/W FOR9
R/W FOR10
R/W FOR11
R/W FOR12
R/W FOR13
R/W FOR14
R/W FOR15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOTE:
1) Select Connection Memory High, Connection Memory Low, or Data Memory by setting the MS1-0 bits in the Control Register.
TABLE 2 OUTPUT HIGH-IMPEDANCE CONTROL
MOD2-0 BITS IN
CONNECTION
MEMORY HIGH
OE X BIT OF TDRSR
CONTROL REGISTER
ODE PIN
OSB BIT IN
OUTPUT DRIVER STATUS
1-1-1
1
1
1
1
1
0
X
0
0
1
1
X
X
0
1
0
1
X
PerChannelHigh-Impedance
Any,otherthan1-1-1
Any,otherthan1-1-1
Any,otherthan1-1-1
Any,otherthan1-1-1
Any,otherthan1-1-1
AllTXinHigh-Impedance
Enable
Enable
Enable
Group x of OEx is in High-Impedance
NOTE:
X = Don't Care.
7
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE 3 CONTROL REGISTER (CR) BITS
Reset Value:
0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRS
BYP
OEPOL AOE
PRST CBER SBER
FBP
BPD2 BPD1
BPD0
BPE
RCML
OSB
MS1
MS0
BIT
NAME
SRS
DESCRIPTION
A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.
15
(SoftwareReset)
14
BYP
(RX/TXBypass)
WhentheBypassbitis1,allRXstreamswillbe"shorted"toTX—ineffectbypassingallinternalcircuitryoftheTSI. Thiseffectively
setstheTSItoa1-to-1switchmodewithalmostonlyafewnanosecondsofdelay. Azerocanbewrittentoallownormaloperation.
TheintentionofthismodeistominimizethedelayfromtheRXinputtotheTXoutput makingtheTSI"invisible". Anyoffsetvalues
intheFORregisterwillberequired.
13
12
11
10
9
OEPOL
(OutputEnablePolarity)
When1,aoneonOEIpindenotesanactivestateontheoutputdatastream;zeroonOEIpindenotesHigh-Impedancestate. When
0, aonedenotesHigh-Impedanceandazerodenotesanactivestate. OEImodeisenteredonaper-group basisintheDRSR.
AOE
(AllOutputEnable)
When1,alloutputstreampins(TXn)becomeOEItoallowforatwo-chipsolutionforalargerswitchingmatrixwithOEIpins. When
inAOEtheDRSmustbesettothecorrespondingdatarateoftheotherdevice.
PRST
(PRBS Reset)
WhenHIGH, thePRBStransmitteroutputwillbeinitialized.
CBER
(ClearBitErrorRate)
A low to high transititon of this bit clears the BER register (BERR).
SBER
(StartBitErrorRate)
A low to high transition in this bit starts the bit error rate test. The bit error test results is kept in the BER register (BERR).
When1, thisbitoverridestheBPSAandBPEAregistersandprogramsthefullConnectionMemoryspace. When0, theBPSA
8
FBP
(FullBlockProgramming) andBPEAdeterminetheConnectionMemoryspacetobeprogrammed.
7-5
BPD2-0
ThesebitscarrythevaluetobeloadedintotheConnectionMemoryblockwhenevertheConnectionMemoryblockprogramming
(BlockProgrammingData) featuresisactivated. AftertheBPEbitissetto1from0, thecontentsofthebitsBPD1-0areloadedintobit1and0(MOD2-0)of
the Connection Memory HIGH.
4
3
BPE
AzerotoonetransitionofthisbitenablestheConnectionMemoryblockprogrammingfeaturedelimitedbytheBPSAandBPEA
registersaswellasforafullblockprogram. OncetheBPEbitissetHIGH,thedevicewillprogramtheConnectionMemoryblock
asfastasthaniftheusermanuallyprogrammedeachConnectionMemorylocationthroughthemicroprocessor. Aftertheprogramming
function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE bit can be
setto0toabortblockprogramming.
(BeginBlock
ProgrammingEnable)
RCML
WhenRCML=1,allbits14-0inConnectionMemoryLOWwillberesettozeroduringblockprogramming;whenRCML=0,bits
14-0inConnectionMemoryLOWwillretaintheiroriginalvaluesduringblockprogramming.
(ResetConnection
Memory LOW in Block
Programming)
2
OSB
(OutputStandby)
When ODE = 0 and OSB = 0, the output drivers of transmit serial streams are in High-Impedance mode. When either ODE = 1
or OSB = 1, the output serial stream drivers function normally.
1-0
MS1-0
These two bitsdecide which memoryto be accessed via microprocessor port.
(MemorySelect)
00 -- Connection Memory LOW
01 -- Connection Memory HIGH
10 -- Data Memory
11 -- Reserved
8
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
MEMORYBLOCKPROGRAMMING
microprocessormoretimetoperformotherfunctions. Also,theTSIcanbemore
TheIDT72V73263providesuserswiththecapabilityofinitializingtheentire efficientinprogrammingthelocationssinceoneCMHlocationisprogrammed
Connection Memory block in two frames. To set bits 2,1 and 0 of every every 32i clock cycles. The group block programming function programs
ConnectionMemoryHIGHlocation,settheFullBlockProgramto1,writethe "channel n"forallstreamsdeliniatedbythegroupbeforegoingto"channeln+1".
desiredpatternintotheBlockProgrammingDataBits(BPD2). Alloftheblock A C-cycle representation is shown below. The Group Block Programming
programmingcontrolcanbefoundintheControlRegisterandenable theBlock featureiscomposedoftheBlockProgrammingStartAddress(BPSA),theBlock
ProgramEnablebit.
ProgrammingEndAddress(BPEA),andtheBPEandBPDbitsintheControl
EnabledbysettingtheBlockProgramEnablebitoftheControlRegisterHIGH. Register. TheBPSAcontainsastartaddressfortheblockprogrammingand
WhentheBlockProgrammingEnablebitoftheControlRegisterissettoHIGH, BPEAcontainsanendaddress.Theblockprogrammingwillstartatthestart
the Block Programming data will be loaded into the bits 2,1 and 0 of every address and program until the end address even if the end address is “less”
ConnectionMemoryHIGHlocationregardlessoftheselecteddatarateforthe thanthestartaddress. Inotherwordsthereisnomechanismtopreventastart
group.TheConnectionMemoryLOWbitswillbeloadedwithzeroswhenthe address that is larger than the end address. If this occurs, the inverse CM
Reset Connection Memory LOW(RCML) bit is enabled and is otherwise left locationsinthegivengroupareprogrammedresultingina“wraparound”effect.
untouched.Whenthememoryblockprogrammingiscomplete,thedeviceresets This “wrap around” effect is independent for both the stream and channel
the Block Programming Enable and the BPD 2-0 bits to zero.
addresses. ThisisillustratedintheGroupBlockProgrammingdiagramSee
The IDT72V73263 also incorporates a feature termed Group Block Figure 1 Group Block Programming Feature. Users must not initiat a block
Programming. GroupBlockProgramming,allowssubsectionsoftheConnection programtooclose(ahead)ofthepresenttransmitlocation. Ifthisisdonethe
Memorytobeblockprogrammedasifthemicroprocessorwereaccessingthe TSI may simultaneously access the CM location that is being modified and
ConnectionMemoryHIGHlocationsinaback-to-backfashion. Theresultsin unpredictabledataonTXoutputsmayoccur. Itshouldbenotedhowever,in
oneconnectionmemoryhighlocationbeingprogrammedforeachC32iclock ordertoenabletheGroupBlockProgrammingtheFullBlockProgram(FBP)
cycle. By having the TSI perform this function it allows the controlling
mustbe0.
9
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE 4 BLOCK PROGRAMMING STARTING ADDRESS (BPSA) REGISTER
Reset Value:
0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
G2
G1
G0
STA2
STA1 STA0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
BIT
15
NAME
DESCRIPTION
Mustbezerofornormaloperation.
Thesebitsareusedtoselectwhichgroupwillbeblockprogrammed
Unused
G2-0
14-12
(GroupAddress
bits2-0)
11-9
8-0
STA2-0
(StreamAddress
bits2-0)
Thesebitsareusedtoselectstartingstreamnumberforblockprogramming.
Thesebitsareusedtoselectstartingchannelnumberforblockprogramming.
CHA8-0
(ChannelAddress
bits8-0)
TABLE 5 BLOCK PROGRAMMING ENDING ADDRESS (BPEA) REGISTER
Reset Value:
FFFFH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
STA2
STA1
STA0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
BIT
15-12
11-9
NAME
DESCRIPTION
Mustbeonefornormaloperation.
Unused
STA2-0
Thesebitsareusedtoselectendingstreamnumberforburstprogramming.
(StreamAddress
bits2-0)
8-0
CHA8-0
Thesebitsareusedtoselectstartingchannelnumberforburstprogramming.
(ChannelAddress
bits8-0)
10
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
CONNECTION MEMORY
CONNECTION MEMORY
Channels
X
Channels
255
0,0
0,0
255
X
X
X
X
X
Stream 2
Stream 2
X
X
X
X
X
X
X
X
X
X
Streams
Streams
X
X
X
X
X
X
Stream 4
Stream 4
X
X
7
7
X
X
Channel 20
Channel 123
BPSA = St2, Ch20
BPEA = St4, Ch 123
Channel 20
Channel 123
BPSA = St4, Ch123
BPEA = St2, Ch20
Channels
X
Channels
X
0,0
0,0
255
255
X
X
X
X
Stream 2
Stream 2
X
X
X
X
X
X
X
X
X
X
Streams
Streams
X
X
X
X
X
X
Stream 4
Stream 4
X
X
7
7
X
X
BPSA = ST4, CH20
BPEA = ST2, CH23
BPSA = ST4, CH23
BPEA = ST2, CH20
Channel 20
Channel 123
Channel 20
Channel 123
6140 drw04
6160 drw04
NOTE:
The group number is defined by the stream address in the BPSA.
Figure 1. Group Block Programming
11
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
int ST, CH
for (CH = StartChannel; CH <= EndChannel; CH++) {
for (ST = StartStream; ST <= EndStream; ST++) {
CMH[ST][CH] = BPD;
}
}
NOTE:
This code is for illustraion purposes only. The IDT72V73263
is a HW instantiation of this kind of software.
Figure 2. "Basic Instantiation"
/* GroupNum is 0-7 */
/* GroupDataRate = 2, 4, 8, 16. or 32 (2Mb/s, 4Mb/s, 8Mb/s, 16Mb/s, 32Mb/s) */
functional BlockProgram (int GroupNum; int GroupDataRate) {
int ST, CH;
int MaxStream = ((GroupNum * 8) + 7);
int MaxChannel = (((GroupDataRate/2) * 32) - 1);
/* StartChannel <= EndChannel */
if (StartChannel <= EndChannel){
for (CH = StartChannel; CH <= EndChannel; CH++){
/* StartStream <= EndStream and StartChannel <= EndChannel */
if (StartStream <= EndStream){
for (ST = StartStream; ST <= EndStream; ST++){
CMH[ST][CH] = BPD;
}
}
/* StartStream > EndStream and StartChannel <= EndChannel */
else{
for (ST = EndStream; ST <= MaxStream; ST++){
CMH [ST] [CH] = BPD;
}
for (ST = (GroupNum*7); ST <= StartStream; ST++){
CMH [ST] [CH] = BPD;
}
}
}
}
/* End > Start Channel */
else{
/* The last part to be programmed */
for (CH = EndChannel; CH <= MaxChannel; CH++){
/* StartStream > EndStream and StartChannel > EndChannel */
if (StartStream <= EndStream){
for (ST = StartStream; ST <= EndStream; ST++){
CMH [ST] [CH] = BPD;
}
}
/* StartStream > EndStream and StartChannel > EndChannel */
else{
for (ST = EndStream; ST <= MaxStream; ST++){
CHM [ST] [CH] = BPD;
}
for (ST = GroupNum*7); ST <= StartStream; ST++){
CMH [ST] [CH] = BPD;
}
}
]
/* The first part to be programmed */
for (CH = 0; CH <= StartChannel; CH++){
/* StartStream > EndStream and StartChannel > EndChannel */
if (StartStream <= EndStream){
for (ST = StartStream; ST <= EndStream; ST++){
CMH [ST] [CH] = BPD;
}
}
/* StartStream > EndStream and StartChannel . EndChannel */
else{
for (ST = EndStream; ST <= MaxStream; ST++){
CMH [ST] [CH] = BPD;
}
for (ST = (GroupNum*7); ST <= StartStream; ST++){
CMH [ST] [CH] = BPD;
}
}
}
}
NOTE:
This code is for illustration purposes only. The IDT72V73263
is a HW instantiation of this kind of software.
Figure 3. "Real" Instantiation of Memory Block Programming
12
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
polled periodically and reset to prevent an overflow condition. To reset the
Pseudo-random bit sequence and the error count registers set the PRST,
CBER,andSBER,oftheControlRegistertohigh. SeetheControlRegisterfor
details.
Following a write to the BERR register a read of the BERR will result in the
present value of the BERR data. Likewise, when the Clear Bit Error Rate bit
(CBER) in the control register is activated, this will clear the internal BERR
(iBERR).
BIT ERROR RATE
Pseudo-RandomBitSequences(PRBS)canbeindependentlytransmitted
andreceived. BysettingtheconnectionmemoryhighbitstotheBERtransmit
mode,thatparticularchannelwilltransmitaBERpatternoftheform215-1. For
thereceiveronlyonechannelcanbespecifiedandmonitoredatagiventime.
BysettingtheBERInputSelection(BIS)toagivenchannel,everyerrorinthe
BER sequence will be incremented by one.
Asageneralrule,areadofBERRshouldbeproceededbyawritetoBERR.
Again,itshouldbenotedthatthewritetotheBERRregisterwillactuallyinitiate
atransferfromthe iBERRtotheBERRwhilethemicroprocessordataisignored.
If the more than 216-1 errors are encountered the BERR register will
automaticallyoverflowandberesettozero. Itisimportanttonotethatnointerrupt
orwarningwillbeissuedinthiscase. Itisrecommendedthatthisregisterbe
TABLE 6 BER INPUT SELECTION REGISTER (BIS)
Reset Value:
Unknown (must be programmed)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
BG2
BG1
BG0
BSA2 BSA1 BSA0 BCA8 BCA7 BCA6 BCA5 BCA4 BCA3 BCA2 BCA1 BCA0
BIT
15
NAME
Unused
BG2-BG0
DESCRIPTION
Mustbezerofornormaloperation
14-12
ThesebitsrefertotheinputdatagroupwhichreceivestheBERdata.
(BER Input Group
AddressBits)
11-9
8-0
BSA2-BSA0
(BER Input
StreamAddressBits)
ThesebitsrefertotheinputdatastreamwhichreceivestheBERdata.
ThesebitsrefertotheinputchannelwhichreceivestheBERdata.
BCA8-BCA0
(LocalBERInput
ChannelAddressBits)
TABLE 7
Reset Value:
15
BIT ERROR RATE REGISTER (BERR)
Unknown (must be programmed)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER15 BER14 BER13 BER12 BER11 BER10 BER9 BER8 BER7 BER6 BER5 BER4 BER3 BER2 BER1 BER0
BIT
NAME
DESCRIPTION
15-0
BER15-BER0
(LocalBitErrorRate
CountBits)
Thesebitsrefertothelocalbiterrorcounts.
NOTE:
Before a read of the BERR, a write to the BERR is neccesary. As a read only register the write will have no effect. See the Bit Error Rate section for more details.
delayed, this feature is useful in compensating for the skew between input
INPUTFRAMEOFFSETSELECTION
streams.
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
Eachinputstreamcanhaveitsowndelayoffsetvaluebyprogrammingthe
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment.Although
frameinputoffsetregisters(FOR,Table8).Themaximumallowableskewis+7.5
allinputdatacomesinatthesamespeed, delayscanbecausedbyvariable
clockperiodsforwardwitharesolutionof½clockperiod,seeTable9.Theoutput
pathserialbackplanesandvariablepathlengthswhichmaybeimplemented
streamscannotbeadjusted.
inlargecentralizedanddistributedswitchingsystems.Becausedataisoften
13
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE 8 FRAME INPUT OFFSET REGISTER (FOR) BITS
Reset Value: 0000H .
Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FOR0Register
FOR1Register
FOR2Register
FOR3Register
FOR4Register
FOR5Register
FOR6Register
FOR7Register
FOR8Register
FOR9Register
OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
OF192 OF191 OF190 DLE19 OF182 OF181 OF180 DLE18 OF172 OF171 OF170 DLE17 OD162 OD161 OF160 DLE16
OF232 OF231 OF230 DLE23 OF222 OF221 OF220 DLE22 OF212 OF211 OF210 DLE21 OF202 OF201 OF200 DLE20
OF272 OF271 OF270 DLE27 OF262 OF261 OF260 DLE26 OF252 OF251 OF250 DLE25 OF242 OF241 OF240 DLE24
OF312 OF311 OF310 DLE31 OF302 OF301 OF300 DLE30 OF292 OF291 OF290 DLE29 OF282 OF281 OF280 DLE28
OF352 OF351 OF350 DLE35 OF342 OF341 OF340 DLE34 OF332 OF331 OF330 DLE33 OF322 OF321 OF320 DLE32
OF392 OF391 OF390 DLE39 OF382 OF381 OF380 DLE38 OF372 OF371 OF370 DLE37 OF362 OF361 OF360 DLE36
FOR10Register OF432 OF431 OF430 DLE43 OF422 OF421 OF420 DLE42 OF412 OF411 OF410 DLE41 OF402 OF401 OF400 DLE40
FOR11Register OF472 OF471 OF470 DLE47 OF462 OF461 OF460 DLE46 OF452 OF451 OF450 DLE45 OF442 OF441 OF440 DLE44
FOR12Register OF512 OF511 OF510 DLE51 OF502 OF501 OF500 DLE50 OF492 OF491 OF490 DLE49 OF482 OF481 OF480 DLE48
FOR13Register OF552 OF551 OF550 DLE55 OF542 OF541 OF540 DLE54 OF532 OF531 OF530 DLE53 OF522 OF521 OF520 DLE52
FOR14Register OF592 OF591 OF590 DLE59 OF582 OF581 OF580 DLE58 OF572 OF571 OF570 DLE57 OF562 OF561 OF560 DLE56
FOR15Register OF632 OF631 OF630 DLE63 OF622 OF621 OF620 DLE62 OF612 OF611 OF610 DLE61 OF602 OF601 OF600 DLE60
NAME
DESCRIPTION
OFn2, OFn1, OFn0
(Offset Bits 2, 1 & 0)
Thesethreebitsdefinehowlongtheserialinterfacereceivertakestorecognizeandstorebit0fromtheRXinputpin:i.e.,tostartanewframe.
Theinputframeoffsetcanbeselectedto+7.5clockperiodsfromthepointwheretheexternalframepulseinputsignalis
appliedtotheFOiinputofthedevice.
DLEn
ST-BUS and
GCI mode:
DLEn = 0, offset is on the clock boundary.
(DataLatchEdge)
DLEn = 1, offset is a half cycle off of the clock boundary.
TABLE 9 OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELAY BITS
(FD11,FD2-0)
INPUT STREAM OFFSET
CLOCK PERIOD SHIFT BASED ON 32.768MHZ CLOCK
CORRESPONDING
OFFSET BITS
32.768Mb/s
None
+ 0.5
16.384Mb/s
None
+ 1.0
8.192Mb/s
None
+ 1.0
4.096Mb/s
None
2.048Mb/s
None
OFn2
OFn1
OFn0
DLEn
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+ 2.0
+ 4.0
+ 1.0
+ 2.0
+ 2.0
+ 4.0
+ 8.0
+ 1.5
+ 3.0
+ 3.0
+ 6.0
+ 12.0
+ 2.0
+ 4.0
+ 4.0
+ 8.0
+ 16.0
+ 2.5
+ 5.0
+ 5.0
+ 10.0
+ 12.0
+ 14.0
+ 20.0
+ 3.0
+ 6.0
+ 6.0
+ 24.0
+ 3.5
+ 7.0
+ 7.0
+ 28.0
• • • • • • • • •
+ 7.5
+ 15.0
+ 15.0
+30.0
+ 60.0
1
1
1
1
ExamplesforInputOffsetDelayTiming
14
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
15
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
16
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
OUTPUT ENABLE INDICATION
OutputEnableIndicationmodehowever,thoseoutputstreamscannotbeused
TheIDT72V73263hasthecapabilitytoindicatethestateoftheoutputs(active totransmitCMorDMdataonlyOEdata. Inthediagrambelownoticehowthe
orthree-state)byenablingtheOutputEnableIndicationintheDRSR. Inthe transmittingstream,TX0isuneffectedbytheenablinganddisablingoftheOE
stream(TX8).
F32i
C32i
TX0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DS
Set OE1 = 0
in TDRSR0
Set OE1 = 1
in TDRSR0
TX8/OEI0
OEPOL = 1
TX8/OEI0
OEPOL = 0
6160 drw6a
NOTE:
The TX0-7 pins are unaffected by the OEI Change.
Figure 6. The Effect of Enabling and Disabling of the OE Bit in TDRSR
17
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
F32i
1
2
3
4
5
6
7
8
C32i
TX0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TX8-OEI0
OEPOL =1
TX8-OEI0
OEPOL = 0
6160 drw6b
NOTE:
Group 0 is in 32.768Mb/s and Group 1 is in OEI Mode.
Figure 7. OEI Function
F32i
C32i
Bit 7
Bit 6
Bit 5
Bit 4
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX0(-7)
DS
Set OE0 = 0
in TDRSR0
Set OE0 = 1
in TDRSR0
TX8-OEI0
OEPOL =1
TX8-OEI0
OEPOL = 0
6160 drw6c
NOTE:
The OEI pins are unaffected by the OE0 change.
Figure 8. Group OE Operation
18
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE 10 TRANSMIT DATA RATE SELECTION REGISTER (TDRSR)
Reset Value:
0000H
TX DRSR 1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OE7
G72
G71
G70
OE6
G62
G61
G60
OE5
G52
G52
G51
OE4
G42
G41
G40
TX DRSR 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OE3
G32
G31
G30
OE2
G22
G21
G20
OE1
G12
G11
G10
OE0
G02
G01
G00
OEx
These bits can be used to High-Z the entire associated group. If OEx = 0 the group will be in High-Z. If OEx =1, the group is in Low-Z (active state).
Thesethreegroupbitsareusedtoselectthetransmitdataratesfortheeightgroupsofeightstreams. Seetable11fordatarates.
Gx2-Gx0
Gx2(1)
Gx1(1)
Gx0(1)
DataRate
2.048Mb/s
4.096Mb/s
8.192Mb/s
16.384Mb/s
32.768Mb/s
Reserved(2)
Reserved(2)
OEI(3)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
If G0/G2/G4/G6 are programmed to be run at 32.768Mb/s, then G1/G3/G5/G7 will be unavailable, respectively, except for OEI purposes. In other words if G0 is
programmed for 32.768Mb/s, G1 will only be available for OEI.
NOTES:
1. "x" corresponds to groups 0-7 (8 Data streams per group).
2. If the Gx2-0 are programmed to the reserved values the device will operate in the
default 2.048Mb/s mode.
3. Only odd groups can be programmed for OEI. The OEI rate corresponds it's
associated even group.
TABLE 11
TX GROUPING AND DATA RATES
GROUP
STREAMS
SPEED
WITH OEI=1
NUMBER
G0
G1
G2
G3
G4
G5
G6
G7
0-7
2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s OEI<0-7>
8-15
16-23
24-31
32-39
40-47
48-55
56-63
2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s OEI<16-23>
2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s OEI<32-39>
2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s OEI<48-55>
19
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE 12 RECEIVE DATA RATE SELECTION REGISTER(RDRSR)
Reset Value:
0000H
RX DRSR 1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
G72
G71
G70
0
G62
G61
G60
0
G52
G51
G50
0
G42
G41
G40
RX DRSR 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
G32
G31
G30
0
G22
G21
G20
0
G12
G11
G10
0
G02
G01
G00
Gx0-Gx2
Thesethreegroupbitsareusedtoselectthereceivedataratesfortheeightgroupsofeightstreams. Seetable13fordatarates.
Gx2(1)
Gx1(1)
Gx0(1)
DataRate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2.048Mb/s
4.096Mb/s
8.192Mb/s
16.384Mb/s
32.768Mb/s
Reserved(2)
Reserved(2)
Reserved(2)
If G0/G2/G4/G6 are programmed to be run at 32.768Mb/s, then G1/G3/G5/G7 will be unavailable, respectively, except for OEI purposes. In other words if G0 is
programmed for 32.768Mb/s, G1 will only be available for OEI.
NOTES:
1. "x" corresponds to groups 0-7 (8 Data streams per group).
2. If the Gx2-0 are programmed to the reserved values the device will operate in the
default 2.048Mb/s mode.
3. Only odd groups can be programmed for OEI. The OEI rate corresponds to it's
associated even group.
TABLE 13 RX GROUPING AND DATA RATES
GROUPNUMBER
STREAMS
SPEED
G0
G1
G2
G3
G4
G5
G6
G7
0-7
2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s
2.048Mb/s-32.768Mb/s
8-15
16-23
24-31
32-39
40-47
48-55
56-63
20
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE 14 CONNECTION MEMORY HIGH
Reset Value:
Unknown (must be programmed)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MOD2 MOD1 MOD0
BIT
15-3
2-0
NAME
DESCRIPTION
Mustbezerofornormaloperation.
Unused
MOD2-0
MOD2
MOD1
MOD0 MODE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VariableDelayMode
ConstantDelayMode
Reserved
Reserved
ProcessorMode
BitErrorRateTest
Reserved
High-Impedance
TABLE 15 CONNECTION MEMORY LOW
Reset Value:
Unknown (must be programmed)
13 12 11 10
SAB5 SAB4 SAB3
15
14
9
8
7
6
5
4
3
2
1
0
0
SAB2 SAB1 SAB0 CAB8 CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
BIT
15
NAME
DESCRIPTION
Mustbezerofornormaloperation
Unused
14-9
SAB5-0
Thebinaryvalueisthenumberofthedatastreamforthesourceoftheconnection.
(SourceStream
Address Bits)
8-0
CAB8-0
Thebinaryvalueisthenumberofthechannelforthesourceoftheconnection.
(SourceChannel
AddressBits)
NOTES:
1. When running the device at lower bit rates (i.e. 2, 4, 8, or 16.384Mb/s), make sure
the bitscorresponding to the unused channels are set to 0.
2. When G0/G2/G4/G6 are programmed for 32.768Mb/s operation its corresponding
group G1/G3/G5/F7 will be unavailable.
3. In processor mode, data in the lower byte (bits0-7) of the Connection Memory LOW
will be output to the TX streams. The order in which the data are output will be starting
from the LSB (Bit 0) to the MSB (Bit 7) of the lower byte. The figure below illustrates
the sequence:
15
14
13
12
11
10
9
8
7
H
6
G
5
F
4
E
3
D
2
C
1
0
A
B
Figure 9. Processor Mode Bit Sequencing
21
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE 16 BOUNDARY SCAN REGISTER BITS
Boundary Scan Bit 0 to 267
Boundary Scan Bit 0 to 267
Device Pin
Input
Scan Cell
Output
Scan Cell
Three-state
Control
Device Pin
Input
Scan Cell
Output
Scan Cell
Three-state
Control
ODE
RESET
C32i
F32i
S/A
DS
0
RX60
RX59
79
80
81
82
83
1
2
RX58
3
RX57
4
RX56
5
TX63/OEI31
TX62/OEI30
TX61/OEI29
TX60/OEI28
TX59/OEI27
TX58/OEI26
TX57/OEI25
TX56/OEI24
TX55/OEi23
TX54/OEi22
TX53/OEI21
TX52/OEI20
TX51/OEI19
TX50/OEI18
TX49/OE17
TX48/OEI16
RX55
84
86
85
87
CS
6
R/W
A0
7
88
89
8
90
91
A1
9
92
93
A2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
70
73
76
77
78
94
95
A3
96
97
A4
98
99
A5
100
102
104
106
108
110
112
114
101
103
105
107
109
111
113
115
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BEL
DTA/BEH
D15
D14
D13
D12
D11
D10
D9
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
RX54
RX53
RX52
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
74
27
30
33
36
39
42
45
48
51
54
57
60
63
66
69
72
75
RX51
RX50
RX49
RX48
RX47
RX46
RX45
RX44
D8
RX43
D7
RX42
D6
RX41
D5
RX40
D4
TX47/OEI15
TX46/OEI14
TX45/OEI13
TX44/OEI12
TX43/OEI11
TX42/OEI10
TX41/OEI9
TX40/OEI8
132
134
136
138
140
142
144
146
133
135
137
139
141
143
145
147
D3
D2
D1
D0
RX63
RX62
RX61
22
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE 16 BOUNDARY SCAN REGISTER BITS (CONTINUED)
Boundary Scan Bit 0 to 267
Boundary Scan Bit 0 to 267
Device Pin
Input
Scan Cell
Output
Scan Cell
Three-state
Control
Device Pin
Input
Scan Cell
Output
Scan Cell
Three-state
Control
RX19
RX18
RX17
RX16
RX15
RX14
RX13
RX12
RX11
RX10
RX9
RX8
TX15
TX14
TX13
TX12
TX11
TX10
TX9
216
217
218
219
220
221
222
223
224
225
226
227
TX39/OEI7
TX38/OEI6
TX37/OEI5
TX36/OEI4
TX35/OEI3
TX34/OEI2
TX33/OEI1
TX32/OEI0
RX39
148
150
152
154
156
158
160
162
149
151
153
155
157
159
161
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
RX38
RX37
RX36
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
RX35
RX34
RX33
RX32
RX31
RX30
RX29
TX8
RX28
TX7
RX27
TX6
RX26
TX5
RX25
TX4
RX24
TX3
TX31
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
TX2
TX30
TX1
TX29
TX0
TX28
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
260
261
262
263
264
265
266
267
TX27
TX26
TX25
TX24
TX23
TX22
TX21
TX20
TX19
TX18
TX17
TX16
RX23
212
213
214
215
RX22
RX21
RX20
23
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
•Test Reset (TRST)
ResettheJTAGscanstructure.ThispinisinternallypulledtoVCCwhenit
is not driven from an external source.
JTAGSUPPORT
TheIDT72V73263JTAGinterfaceconformstotheBoundary-Scanstandard
IEEE-1149.1.Thisstandardspecifiesadesign-for-testabilitytechniquecalled
Boundary-Scan test (BST). The operation of the boundary-scan circuitry is
controlledbyanexternaltestaccessport(TAP)Controller.
INSTRUCTION REGISTER
InaccordancewiththeIEEE-1149.1standard,theIDT72V73263usespublic
instructions.TheIDT72V73263JTAGinterfacecontainsafour-bitinstruction
register.InstructionsareseriallyloadedintotheinstructionregisterfromtheTDI
whentheTAPControllerisinitsshift-IRstate.Subsequently,theinstructionsare
decodedtoachievetwobasicfunctions:toselectthetestdataregisterthatmay
operatewhiletheinstructioniscurrent,andtodefinetheserialtestdataregister
path, which is used to shift data between TDI and TDO during data register
scanning.SeeTable12forInstructiondecoding.
TEST ACCESS PORT (TAP)
The Test Access Port (TAP) provides access to the test functions of the
IDT72V73263.Itconsistsofthreeinputpinsandoneoutputpin.
•Test Clock Input (TCK)
TCKprovidestheclockforthetestlogic.TheTCKdoesnotinterferewithany
on-chipclockandthusremainsindependent.TheTCKpermitsshiftingoftest
data into or out of the Boundary-Scan register cells concurrently with the
operationofthedeviceandwithoutinterferingwiththeon-chiplogic.
•Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controllertocontrolthetestoperations.TheTMSsignalsaresampledatthe
risingedgeoftheTCKpulse. ThispinisinternallypulledtoVCCwhenitisnot
driven from an external source.
TESTDATAREGISTER
AsspecifiedinIEEE-1149.1,theIDT72V73263JTAGInterfacecontainstwo
testdataregisters:
•The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
arrangedtoformascanpatharoundtheboundaryoftheIDT72V73263core
logic.
•Test Data Input (TDI)
•The Bypass Register
Serialinputdataappliedtothisportisfedeitherintotheinstructionregisteror
intoatestdataregister,dependingonthesequencepreviouslyappliedtothe
TMSinput.Bothregistersaredescribedinasubsequentsection.Thereceived
inputdataissampledattherisingedgeofTCKpulses.Thispinisinternallypulled
to VCC when it is not driven from an external source.
TheBypassregisterisasinglestageshiftregisterthatprovidesaone-bitpath
from TDI to TDO. The IDT72V73263 boundary scan register bits are shown
inTable14.Bit0isthefirstbitclockedout.Allthree-stateenablebitsareactive
HIGH.
•TestDataOutput(TDO)
DependingonthesequencepreviouslyappliedtotheTMSinput,thecontents
ofeithertheinstructionregisterordataregisterareseriallyshiftedoutthrough
the TDO pin on the falling edge of each TCK pulse. When no data is shifted
through the boundary scan cells, the TDO driver is set to a High-Impedance
state.
ID CODE REGISTER
AsspecifiedinIEEE-1149.1,thisinstructionloadstheIDRwiththeRevision
Number, DeviceID, JEDECID, andIDRegisterIndicatorBit. SeeTable10.
TABLE17—IDENTIFICATIONREGISTERDEFINITIONS
INSTRUCTION FIELD
RevisionNumber(31:28)
IDT Device ID (27:12)
VALUE
DESCRIPTION
0x0
Reservedforversionnumber
DefinesIDTpartnumber
0x0430
0x33
1
IDT JEDEC ID (11:1)
AllowsuniqueidentificationofdevicevendorasIDT
IndicatesthepresenceofanIDregister
IDRegisterIndicatorBit(Bit0)
TABLE 18— SCAN REGISTER SIZES
REGISTER NAME
BIT SIZE
Instruction(IR)
4
1
Bypass (BYR)
Identification(IDR)
Boundary Scan (BSR)
NOTE:
32
Note(1)
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on
the IDT website (www.idt.com), or by contacting your local IDT sales representative.
24
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
TABLE19—SYSTEMINTERFACEPARAMETERS
INSTRUCTION
EXTEST
CODE
0000
1111
0010
0011
0001
DESCRIPTION
Forcescontentsoftheboundaryscancellsontothedeviceoutputs(1).Placestheboundaryscanregister(BSR)betweenTDIandTDO.
BYPASS
Places the bypass register (BYR) between TDI and TDO.
IDCODE
LoadstheIDregister(IDR)withthevendorIDcodeandplacestheregisterbetweenTDIandTDO.
Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state.
Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs(2) and outputs(1) to be
capturedintheboundaryscancellsandshiftedseriallythroughTDO.PRELOADallowsdatatobeinputseriallyintotheboundary
scan cells via the TDI.
HIGH-Z
SAMPLE/PRELOAD
RESERVED
Allothercodes Severalcombinationsarereserved. Donotuseothercodesthanthoseidentifiedabove.
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS and TRST.
TABLE 20 — JTAG AC ELECTRICAL CHARACTERISTICS (1,2,3,4)
SYMBOL
tJCYC
tJCH
PARAMETER
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock LOW
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAGReset
MIN.
100
40
MAX.
UNITS
ns
ns
tJCL
40
ns
tJR
3(1)
3(1)
ns
tJF
ns
tJRST
tJRSR
tJCD
50
50
ns
JTAG Reset Recovery
JTAGDataOutput
JTAGDataOutputHold
JTAGSetup
ns
25
ns
tJDC
0
ns
tJS
15
15
ns
tJH
JTAG Hold
ns
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
tJCYC
tJR
tJF
tJCH
tJCL
TCK
(1)
TDI/TMS
(Device Inputs)
tJH
tJS
tJDC
TDO
(Device Outputs)
tJCD
tJRSR
6160 drw07
TRST
x
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
Figure 10. JTAG Timing Specifications
25
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATING
CONDITIONS(1)
Symbol Parameter
Min.
Max.
Unit
Symbol
Parameter
Min.
3.0
Typ.
Max.
3.6
Unit
V
VCC
Vi
SupplyVoltage
-0.5
GND -0.3
-50
+4.0
VCC +0.3
50
V
V
VCC
Positive Supply
Input HIGH Voltage
InputLOWVoltage
3.3
VoltageonDigitalInputs
CurrentatDigitalOutputs
StorageTemperature
VIH(1)
VIL
2.0
VCC
0.8
V
IO
mA
°C
W
-0.3
-40
V
TS
-55
+125
2
TOP
OperatingTemperature
Industrial
25
+85
°C
PD
PackagePowerDissapation
NOTES:
1. Inputs/Outputs are not 5V tolerant
2. Voltages are with respect to ground (GND) unless otherwise stated.
NOTE:
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
DCELECTRICALCHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
380
60
Units
mA
µA
µA
µA
V
(2)
ICC
SupplyCurrent
(3,4)
IIL
InputLeakage(inputpins)
InputLeakage(I/Opins)
High-ImpedanceLeakage
Output HIGH Voltage
OutputLOWVoltage
—
—
(3,4)
IBL
60
(3,4)
IOZ
60
(5)
VOH
2.4
(6)
VOL
0.4
V
NOTES:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Outputs unloaded.
3. 0 ≤ V ≤ VCC.
4. Maximum leakage on pins (output or I/O pins in High-Impedance state) is over an applied voltage (V).
5. IOH = 10 mA.
6. IOL = 10 mA.
ACELECTRICALCHARACTERISTICS-TIMINGPARAMETER
MEASUREMENTVOLTAGELEVELS
VDD
Symbol
Rating
Level Unit
VTT
TTLThreshold
1.5
2.0
0.8
V
V
50Ω
VHM
TTLRise/FallThresholdVoltageHIGH
TTLRise/FallThresholdVoltageLOW
InputPulseLevels
Z0 = 50Ω
I/O
VLM
V
V
6160 drw08
tr,tf
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1
ns
V
V
Figure 11. AC Termination
(1)
CL
50
pF
VDD
NOTE:
1. JTAG CL is 30pF
330Ω
D.U.T.
30pF*
510Ω
6160 drw09
Figure 12. AC Test Load
26
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - RESET AND ODE TIMING
Symbol
Parameter
Min.
Typ.
Max.
12
Units
ns
t
RZ
Active to High-Z on Master Reset
ResetPulseWidth
—
—
tRS
20
—
—
ns
tODELZ
Output Driver Enable (ODE) to Low-Z
6
—
—
ns
RESET
tRZ
tRS
TX
ODE
6160 Drw10
Figure 13. Reset and ODE Timing
AC ELECTRICAL CHARACTERISTICS - C32i AND ODE TO HIGH-Z TIMING AND
C32i AND ODE TO LOW-Z TIMING
Symbol
tCLZ(1)
tCHZ(1)
tODEA
tODEHZ
tODELZ
tSIH(1)
Parameter
Min.
3
Typ.
—
—
—
—
—
—
7
Max.
—
9
Units
ns
Clock to Low-Z
Clock to High-Z
—
6
ns
ODE to Valid Data
—
9
ns
OutputDriverEnable(ODE)toHigh-Z
Outut Driver Enable (ODE) to Low-Z
RXHoldTime
3
ns
4
—
—
9
ns
4
ns
tSOD
Clock to Valid Data
3
ns
NOTE:
1. CL = 30pF.
C32i
(ST-BUS mode)
C32i
(GCI mode)
ODE
TX
t
SOD
t
ODEA
tODELZ
tODEHZ
tCHZ
TX
TX
VALID DATA
VALID DATA
t
CLZ
6160 drw12
tSIH
VALID DATA
6160 drw11
Figure 15. Output Driver Enable (ODE)
Figure 14. Serial Output and External Control
27
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - ST-BUS TIMING
Symbol
Parameter
Min.
Typ.
15.25
15.25
Max.
17
Units
ns
tCH
C32i Pulse Width HIGH
Clock rate = 32.768Mb/s
13
tCL
tCP
C32i Pulse Width LOW
Clock rate = 32.768Mb/s
13
17
ns
C32iPeriod
Clock rate = 32.768Mb/s
29
5
30.5
—
35
—
—
ns
ns
ns
tFPH
tFPS
tFPW
Frame Pulse Hold Time from C32i falling (ST-BUS or GCI)
Frame Pulse Setup Time from C32i falling *ST-BUS or GCI)
5
—
Frame Pulse Width (ST-BUS , GCI)
Clock rate = 32.768Mb/s
13
—
4
—
1
31
—
—
—
9
ns
ns
ns
ns
ns
tr,tf(1)
tSIH
ClockRise/FallTime
RXHoldTime
—
—
7
tSIS
RXSetupTime
2
tSOD
Clock to Valid Data
3
NOTE:
1. Parameters verified under test conditions.
tFPW
F32i
t
r
t
f
tFPS
tFPH
tCH
tCL
C32i
TX 32.768 Mb/s
RX 32.768 Mb/s
t
SOD
tCP
Bit 7
Bit 1
Bit 3
Bit 0
Bit 5
Bit 2
Bit 7
Bit 4
Bit 1
Bit 6
Bit 3
Bit 0
Bit 5
Bit 2
Bit 7
SIH
Bit 4
Bit 1
Bit 6
Bit 0
Bit 2
t
t
SIS
Bit 7
Bit 1
Bit 3
Bit 0
Bit 5
Bit 2
Bit 7
Bit 4
Bit 1
Bit 6
Bit 3
Bit 0
Bit 5
Bit 2
Bit 1
Bit 7
Bit 6
Bit 4
Bit 0
Bit 2
tCH
tCL
CLK-16.384 MHz(1)
tCP
tSOD
Bit 7
Bit 7
TX 16.384 Mb/s
RX 16.384 Mb/s
Bit 1
Bit 1
Bit 0
Bit 7
SIH
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
tSIS
t
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
tSOD
Bit 0
Bit 0
Bit 3
TX 8.192 Mb/s
RX 8.192 Mb/s
Bit 4
Bit 7
Bit 6
Bit 5
tSIS
tSIH
Bit 7
Bit 6
Bit 5
Bit 4
tCH
tCL
CLK- 8.192 MHz(1)
tCP
tSOD
TX 4.096 Mb/s
RX 4.096 Mb/s
Bit 5
Bit 0
Bit 7
Bit 6
tSIS
tSIH
Bit 0
Bit 7
Bit 6
CLK- 4.096 MHz(1)
tSOD
TX 2.048 Mb/s
RX 2.048 Mb/s
Bit 0
Bit 7
Bit 6
tSIS
tSIH
Bit 7
6160 drw13
NOTE:
1. These clocks are for reference purposes only.
The TSI only accepts a 32.768MHz clock.
Figure 16. ST-BUS Timing
28
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - GCI BUS TIMING
Symbol
Parameter
Min.
Typ.
15.25
15.25
Max.
17
Units
ns
tCH
C32i Pulse Width HIGH
Clock rate = 32.768Mb/s
13
tCL
tCP
C32iPulseWidth
Clock rate = 32.768Mb/s
13
17
ns
C32iPeriod
Clock rate = 32.768Mb/s
29
5
30.5
—
35
—
—
ns
ns
ns
tFPH
tFPS
tFPW
Frame Pulse Hold Time from C32i falling (ST-BUS or GCI)
Frame Pulse Setup Time before C32i falling (ST-BUS or GCI)
5
—
Frame Pulse Width (ST-BUS or GCI)
Clock rate = 32.768Mb/s
13
—
4
—
1
31
—
—
—
9
ns
ns
ns
ns
ns
(1)
tr,tf
ClockRise/FallTime
RXHoldTime
tSIH
tSIS
tSOD
—
—
7
RXSetupTime
2
Clock to Valid Data
3
NOTE:
1. Parameters verified under test conditions.
tFPW
F32i
tFPS
tFPH
t
r
t
f
tCL
tCH
CLK- 32.768 MHz
tCP
tSOD
Bit 5
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
TX 32.768 Mb/s
RX 32.768 Mb/s
tSIH
tSIS
Bit 0
Bit 3
Bit 6
Bit 1
Bit 4
Bit 7
Bit 6
Bit 7
Bit 1
Bit 2
Bit 4
Bit 5
Bit 7
Bit 0
Bit 2
Bit 3
Bit 5
Bit 6
tCH
tCL
CLK- 16.384 MHz(1)
tCP
tSOD
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
TX 16.384 Mb/s
RX 16.384 Mb/s
tSIH
tSIS
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
tSOD
TX 8.192 Mb/s
RX 8.192 Mb/s
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
tSIS
tSIH
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
tCH
tCL
CLK- 8.192 MHz(1)
tSOD
tCP
Bit 7
Bit 0
Bit 1
TX 4.096 Mb/s
RX 4.096 Mb/s
tSIH
tSIS
Bit 7
Bit 0
Bit 1
CLK- 4.096 MHz(1)
tSOD
TX 2.048 Mb/s
RX 2.048 Mb/s
Bit 7
Bit 0
tSIH
tSIS
Bit 0
6160 drw14
NOTE:
1. These clocks are for reference purposes only.
The TSI only accepts a 32.768MHz clock.
Figure 17. GCI Bus Timing
29
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - OEI BUS TIMING IN ST-BUS MODE
Symbol
Parameter
Min.
Typ.
Max.
Units
tCH
C32i Pulse Width HIGH
Clock rate = 32.768Mb/s
13
—
15.25
—
17
9
ns
ns
tCHZ(2)
tCL
Clock to High-Z
C32iPulseWidth
Clock rate = 32.768Mb/s
13
3
15.25
—
17
—
ns
ns
tCLZ(2)
tCP
Clock to Low-Z
C32iPeriod
Clock rate = 32.768Mb/s
29
5
30.5
—
35
—
—
ns
ns
ns
tFPH
tFPS
tFPW
Frame Pulse Hold Time from C32i falling (ST-BUS or GCI)
Frame Pulse Setup Time before C32i falling (ST-BUS or GCI)
5
—
Frame Pulse Width (ST-BUS or GCI)
Clock rate = 32.768Mb/s
13
3
—
—
—
1
31
9
ns
ns
ns
ns
ns
tOEIE
tOEID
Clock to OEI Enable
Clock to OEI Disable
ClockRise/FallTime
Clock to Valid Data
3
9
(1)
tr,tf
—
3
—
9
tSOD
7
NOTE:
1. Parameters verified under test conditions.
2. CL = 300pF
tFPW
F32i
C32i
t
f
tFPS
tCL
tr
tFPH
tCH
tCP
tSOD
tCHZ
TX16.384 Mb/s
Bit 0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 7
Bit 6
Bit 5
tCLZ
tOEID
tOEIE
OEI(1)
OEI(2)
tOEIE
tOEID
6160 drw15
NOTES:
1) OEPOL = 1
2) OEPOL = 0
Figure 18. OEI Bus Timing in ST-BUS Mode
30
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - RX TO TX INTERNAL BYPASS BIT
SYMBOL
PARAMETER
MIN. TYP.
MAX.
UNITS
tBC
2
8
12
ns
RX
t
BC
t
BC
t
BC
TX
6160 drw16
t
BC = end to end chip delay
Figure 19. RX to TX Internal Bypass Bit
31
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MOTOROLANON-MULTIPLEXEDBUS
ASYCHRONOUSTIMINGMEMORYACCESS
SYMBOL
tADH
PARAMETER
MIN. TYP.
MAX.
—
UNITS
ns
Address Hold afterDS Rising
AddressSetupfromDSFalling
2
2
—
—
tADS
—
ns
(1)
tAKD
AcknowledgmentDelay:
Reading/WritingMemory
—
—
0
—
—
—
—
—
15
—
—
—
—
—
—
30
10
—
—
—
25
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1,2,3)
tAKH
AcknowledgmentHoldTime
CS Hold Time after DS Rising
CS Setup from DS Falling
Data Setup from DTALOW on Read
Data Hold On Read
tCSH
tCSS
0
(1)
tDDR
2
(1)
tDHR
10
5
tDHW
tDSS
DataHoldonRead
DataStrobeSetupTime
DataStrobeonWrite
2
tDSPW
tRWH
tRWS
tSWD
6
R/W Hold after DS Rising
R/WSetup from DSFalling
ValidDataDelayonWrite
3
3
2
NOTES:
1. CL = 30pF
2. RL = 1K
3. High-ImpedanceismeasuredbypullingtotheappropriaterailwithRL,withtimingcorrectedtocanceltimetakentodischargeCL.
4. Toachieveonclockcyclefastmemoryaccess,thissetuptime,tDSSshouldbemet. Otherwise,worst-casememoryaccessoperationisdetermined
by tAKD.
CLK GCI
CLK ST-BUS
tDSPW
tDSS
tDSS
DS
tCSS
tCSH
tCSS
tCSH
CS
tRWS
tRWH
tRWS
tRWH
R/W
tADH
tADH
tADS
tADS
A0-A15
D0-D15
VALID READ ADDRESS
VALID WRITE ADDRESS
VALID WRITE DATA
tSWD
tDHR
tDHW
VALID READ DATA
tDDR
tAKH
tAKD
tAKH
tAKD
DTA
6160 drw17
Figure 20. Motorola Non-Multiplexed Bus Asychronous Memory Access
32
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MOTOROLANON-MULTIPLEXEDBUS
ASYNCRONOUSTIMINGREGISTERACCESS
SYMBOL
PARAMETER
MIN. TYP.
MAX.
UNITS
tADH
Address Hold after DS Rising
AddressSetupfromDSFalling
2
2
—
—
—
ns
tADS
—
ns
(1)
tAKD
AcknowledgmentDelay:
Reading/WritingRegisters
—
—
0
—
—
—
—
—
15
—
—
—
—
—
40
20
—
—
—
25
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1,2,3)
tAKH
AcknowledgmentHoldTime
CS Hold Time after DS Rising
CS Setup from DS Falling
Data Setup from DTALOW on Read
Data Hold On Read
tCSH
tCSS
0
(1)
tDDR
2
(1)
tDHR
10
5
tDHW
tDSPW
tDSW
tRWH
tSWD
DataHoldonRead
DataStrobeonWrite
6
DataSetuponWrite
10
3
R/W Hold after DS Rising
R/W Setup fromDSFalling
3
NOTES:
1. CL = 30pF
2. RL = 1K
3. High-ImpedanceismeasuredbypullingtotheappropriaterailwithRL,withtimingcorrectedtocanceltimetakentodischargeCL.
4. Toachieveonclockcyclefastmemoryaccess,thissetuptime,tDSSshouldbemet. Otherwise,worst-casememoryaccessoperationisdetermined
by tAKD.
DS
tDSPW
tCSS
tCSH
tCSS
tCSH
CS
tRWS
tRWH
tRWS
tRWH
R/W
tADH
tADH
tADS
tADS
A0-A15
D0-D15
VALID READ ADDRESS
VALID WRITE ADDRESS
tDHR
tDSW
tDHW
VALID WRITE
DATA
VALID READ DATA
tDDR
tAKH
tAKD
tAKH
tAKD
DTA
6160 drw17a
Figure 21. Motorola Non-Multiplexed Bus Asychronous Timing Register Access
33
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-SYNCHRONOUSBUSTIMING
SYMBOL
tADH
PARAMETER
Address Hold
AddressSetup
Byte Enable Hold
BtyeEnableSetup
Clock to Data
DataHoldonRead
DataHoldonWrite
DataSetuponWrite
R/W Hold
MIN. TYP.
MAX.
—
UNITS
ns
3
3
—
—
—
—
—
15
—
—
—
—
—
—
tADS
—
ns
tBEH
3
—
ns
tBES
3
—
ns
tCD
—
10
3
20
ns
(1,2,3)
tDHR
25
ns
tDHW
tDSW
tRWH
tRWS
tsCSH
tsCSS
—
ns
3
—
ns
3
—
ns
R/WSetup
3
—
ns
CS Hold
3
—
ns
CS Setup
3
—
ns
NOTES:
1. CL = 30pF
2. RL = 1K
3. High-ImpedanceismeasuredbypullingtotheappropriaterailwithRL,withtimingcorrectedtocanceltimetakentodischargeCL.
4. Toachieveonclockcyclefastmemoryaccess,thissetuptime,tDSS shouldbemet. Otherwise,worst-casememoryaccessoperationisdetermined
by tAKD.
CLK ST-BUS
CLK GCI
tSCSH
tSCSS
tSCSH
tSCSS
CS
tBES
tBEH
tBEH
tBES
BEN
tRWS
tRWH
R/W
A0-15
t
RWS
tRWH
t
ADS
tADS
tADH
tADH
WRITE
READ
tDSW tDHW
DATA-IN
Dn
tCD
DATA-OUT
Qn
6160 drw18
tDHR
Figure 22. Synchronous Bus Timing
34
IDT72V732633.3VTIMESLOTINTERCHANGE
DIGITALSWITCHWITHRATEMATCHING 16,384x16,384CHANNELS
INDUSTRIAL TEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-BYTEENABLE
SYMBOL
tADH
PARAMETER
Address Hold
AddressSetup
Byte Enable Hold
ByteEnableSetup
Clock to Data
DataHoldonRead
R/W Hold
MIN. TYP.
MAX.
—
UNITS
ns
3
3
—
—
—
—
—
15
—
—
—
—
tADS
—
ns
tBEH
3
—
ns
tBES
3
—
ns
tCD
—
10
3
20
ns
(1)
tDHR
25
ns
tRWH
tRWS
tsCSH
tsCSS
—
ns
R/WSetup
3
—
ns
CS Hold
3
—
ns
CS Setup
3
—
ns
NOTES:
1. CL = 30pF
2. RL = 1K
3. High-ImpedanceismeasuredbypullingtotheappropriaterailwithRL,withtimingcorrectedtocanceltimetakentodischargeCL.
CLK ST-BUS
CLK GCI
tSCSS
tSCSH
tSCSS
tSCSH
CS
tBEH
tBES
BEL
tBEH
tBES
BEH
tRWH
tRWS
R/W
tRWS
tRWH
A0-15(3)
READ
READ
tADS
tADH
tADS
tADH
D0-7
D0-7
tCD
tDHR
tCD
tDHR
D8-15
D8-15
6160 drw19
Figure 23. Byte Enable
35
ORDERINGINFORMATION
IDT
XXXXXX
XX
X
Device Type
Package
Process/
Temperature
Range
BLANK
Commercial (-40°C to +85°C)
Plastic Ball Grid Array (PBGA, BB208-1)
BB
72V73263
16.384 x 16.384 3.3V Time Slot Interchange Digital Switch with Rate Matching
6160 drw22
DATASHEETDOCUMENTHISTORY
06/30/2003 pgs. 9,14 and 33.
09/08/2003 pgs. 1, 4, 5, 20, 28, 33 and 34.
10/28/2003 pg. 1
CORPORATE HEADQUARTERS
2975StenderWay
for SALES:
800-345-7015 or 408-727-6116
for Tech Support:
408-330-1753
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com
email:TELECOMhelp@idt.com
36
相关型号：
72V73273BBBLANK
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS
IDT
©2020 ICPDF网 联系我们和版权申明