72V73250DAG [IDT]
Digital Time Switch;
| 型号： | 72V73250DAG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Digital Time Switch |
| 文件： | 总24页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
IDT72V73250
8,192 x 8,192
FEATURES:
DESCRIPTION:
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•
•
•
•
•
•
•
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8K x 8K non-blocking switching at 32.768Mb/s
16 serial input and output streams
The IDT72V73250 has a non-blocking switch capacity of 8,192 x 8,192
channels at 32.768Mb/s. With 16 inputs and 16 outputs, programmable per
streamcontrol,andavarietyofoperatingmodestheIDT72V73250isdesigned
fortheTDMtimeslotinterchangefunctionineithervoiceordataapplications.
Some of the main features of the IDT72V73250 are LOW power 3.3 Volt
operation, automatic ST-BUS® /GCI sensing, memory block programming,
simplemicroprocessorinterface, JTAGTestAccessPort(TAP)andperstream
programmableinputoffsetdelay,variableorconstantthroughputmodes,output
enable and processor mode.
Accepts single-bit single-data streams at 32.768Mb/s
Per-channel Variable Delay Mode for low-latency applications
Per-channel Constant Delay Mode for frame integrity applications
Automatic identification of ST-BUS® and GCI bus interfaces
Automatic frame offset delay measurement
Per-stream single data frame delay offset programming
Per-channel high-impedance output control
Direct microprocessor access to all internal memories
Memory block programming for quick setup
IEEE-1149.1 (JTAG) Test Port
3.3V Power Supply
Available in 144-pin (20mm x 20mm) Thin Quad Flatpack (TQFP)
and 144-pin (13mm x 13mm) Plastic Ball Grid Array (PBGA)
Operating Temperature Range -40°C to +85°C
The IDT72V73250 is capable of switching up to 8,192 x 8,192 channels
withoutblocking.Designedtoswitch64Kbit/sPCMorNx64Kbit/sdata,the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delay for voice applications on a per-channel basis.
The16serialinputstreams(RX)oftheIDT72V73250arerunat32.768Mb/s
allowing512channelsper125μsframe.Thedataratesontheoutputstreams
(TX) are identicalto those on the input streams(RX).
•
FUNCTIONAL BLOCK DIAGRAM
RESET
VCC
GND
ODE
TX0
TX1
RX0
RX1
Data Memory
MUX
Receive
Serial Data
Streams
TX7
Transmit
Serial Data
Streams
TX8/OEI0
TX9/OEI1
Connection
Memory
Internal
Registers
TX15/OEI7
RX15
Microprocessor Interface
Timing Unit
JTAG Port
DS
CS
DTA
TRST
TMS TDI TCK TDO
C32i F32i FE
R/W
A0-A14
D0-D15
5933 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS® isatrademarkofMitelCorp.
JUNE 2004
1
© 2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5933/10
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
PINCONFIGURATIONS
A1 BALL PAD CORNER
A
RX4
RX5
RX6
C32i RESET
ODE
RX0
TDI
RX1
RX2
RX3
RX7
TX0
TX1
TX4
TX3
TX2
TX7
TX6
TX5
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
B
C
D
E
NC(1)
NC(1)
F32i
FE
NC(1)
NC(1)
NC(1)
NC(1)
TMS
NC(1)
TDO
CS
NC(1)
RX8
TCK
DS
VCC
VCC
VCC
VCC
NC(1)
VCC
NC(1)
NC(1)
RX9
TRST
R/W
A0
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RX10
F
VCC
VCC
VCC
A1
A6
A2
A5
A3
A4
VCC
VCC
RX13
RX14
RX12
RX15
RX11
G
TX8/
OEI0
H
J
TX9/
OEI1
TX10/
OEI2
TX11/
OEI3
A9
A8
A7
VCC
TX12/
OEI4
TX13/ TX14/
OEI5
NC(1)
A13
A12
A11
A10
D8
VCC
VCC
VCC
VCC
OEI6
K
L
NC(1)
A14
D5
D2
D1
D0
TX15/
OEI7
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
D15
D14
1
D11
D12
3
D9
D10
4
D6
D7
5
D3
D4
6
DTA
M
D13
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
2
7
8
9
10
11
12
5933 drw02
NOTE:
1. NC = No Connect.
PBGA: 1mm pitch, 13mm x13mm (BB144-1, order code: BB)
TOP VIEW
2
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
PINCONFIGURATIONS(CONTINUED)
1
1
1
)
)
)
NC(
NC(
NC(
NC(
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
GND
72
71
70
69
68
67
66
65
64
V
CC
(1)
NC
NC
NC
1)
(1)
(1)
GND
1)
1)
1)
1)
1)
1)
1)
1)
1)
NC(
NC(
NC(
NC(
NC(
NC(
NC(
NC(
NC(
(1)
NC
GND
V
NC
NC
CC
(1)
(1)
63
(1)
NC
(1)
NC
62
61
60
GND
VCC
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
TX7
TX6
TX5
TX4
GND
GND
CC
V
D0
D1
D2
VCC
D3
TX3
TX2
TX1
TX0
GND
GND
VCC
D4
D5
D6
D7
VCC
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
ODE
GND
CC
V
D8
D9
138
139
140
141
142
D10
D11
GND
V
CC
D12
D13
143
144
RESET
5933 drw03
PIN 1
NOTE:
1. NC = No Connect.
TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA)
TOP VIEW
3
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
PINDESCRIPTION
SYMBOL
A0-14
C32i
NAME
Address 0 to 14
Clock
I/O
DESCRIPTION
Theseaddresslinesaccessallinternalmemories.
I
I
I
Serialclockforshiftingdatain/outontheserialdatastream.Thisinputacceptsa32.768MHzclock.
ThisactiveLOWinputisusedbyamicroprocessortoactivatethemicroprocessorportofIDT72V73250.
CS
D0-15
DS
ChipSelect
Data Bus 0-15
DataStrobe
I/O Thesepinsarethedatabitsofthemicroprocessorport.
I
ThisactiveLOWinputworksinconjunctionwith CStoenablethereadandwriteoperationsandsetsthe
data bus lines (D0-D15).
DTA
DataTransfer
Acknowledgment
O
Indicatesthatadatabustransferiscomplete. Whenthebuscycleends, thispindrivesHIGHandthengoes
high-impedance, allowingforfasterbuscycleswithaweakerpull-upresistor. Apull-upresistorisrequired
to hold a HIGH level when the pin is in high-impedance.
FE
Frame Evaluation
FramePulse
I
I
This input can be used to measure delay in the data path by comparing the frame pulse, F32i, with this input.
F32i
Thisinputacceptsandautomaticallyidentifiesframesynchronizationsignalsformattedaccordingto
ST-BUS®andGCIspecifications.
GND
ODE
Ground
GroundRail
OutputDriveEnable
I
I
ThisistheoutputenablecontrolfortheTXserialoutputs.WhentheODEinputisLOWandtheOutputStand
BybitoftheControlRegisterisLOW,allTXoutputsareinahigh-impedancestate.IfthisinputisHIGH,theTX
outputdriversareenabled.However,eachchannelmaystillbeputintoahigh-impedancestatebyusingthe
per-channelcontrolbitsintheConnectionMemory.
RESET
DeviceReset
Read/Write
ThisinputputstheIDT72V73250intoaresetstatethatclearsthedeviceinternalcounters,registersand
brings TX0-15 and D0-D15 into a high-impedance state. The RESET pin must be held LOW for a minimum
of 20ns to properly reset the device.
R/W
I
I
Thisinputcontrolsthedirectionofthedatabuslines(D0-D15)duringamicroprocessoraccess.
Serial data input stream. These streams have a data rate of 32.768 Mb/s.
RX0-15 DataStream
Input 0 to 15
TCK
TDI
TestClock
I
I
ProvidestheclocktotheJTAGtestlogic.
Test Serial Data In
JTAGserialtestinstructionsanddataareshiftedinonthispin. ThispinispulledHIGHbyaninternalpull-up
when not driven.
TDO
TMS
TRST
TestSerialDataOut
TestModeSelect
TestReset
O
I
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.
JTAGsignalthatcontrolsthestatetransitionsoftheTAPcontroller.ThispinispulledHIGHbyaninternal
pull-up when not driven.
I
AsynchronouslyinitializestheJTAGTAPcontrollerbyputtingitintheTest-Logic-Resetstate.Thispinis
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
toensurethattheIDT72V73250isinthenormalfunctionalmode.
TX0-7
TX Output 0 to 7
(Three-StateOutputs)
O
O
Serial data output stream. These streams have a data rate of 32.768 Mb/s.
TX8-15/ TX Output 8 to 15/
OEI0-7
Whenall16outputstreamsareselectedviaControlRegister,thesepinsaretheoutputstreamsTX8toTX15
andoperateat32.768Mb/s.Whenoutputenablefunctionisselected,thesepinsreflecttheactiveorhigh-
impedancestatusforthecorrespondingoutputstreamOutputEnableIndication0-7.
OutputEnable
Indication0-7
(Three-StateOutputs)
VCC
VCC
+3.3 Volt Power Supply.
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IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
SERIAL DATA INTERFACE TIMING
Fora32.768Mb/sserialdatarate,themasterclockfrequencywillberunning
at32.768MHzresultinginasingle-bitperclock. TheIDT72V73250provides
twodifferentinterfacetimingmodes,ST-BUS® orGCI.
The IDT72V73250 automatically detects the presence of an input frame
pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® Mode, data is
clockedoutonthefallingedgeandisclockedinonthesubsequentrising-edge.
SeeFigure12fortiming. InGCIMode,dataisclockedoutontherisingedge
and is clocked in on the subsequent falling edge. See Figure 13 for timing.
DESCRIPTION(CONTINUED)
Withtwomainoperatingmodes,ProcessorModeandConnectionMode,the
IDT72V73250 can easily switch data from incoming serial streams (Data
Memory)orfromthecontrollingmicroprocessorviaConnectionMemory.As
controlandstatusinformationiscriticalindatatransmission,theProcessorMode
isespeciallyusefulwhentherearemultipledevicessharingtheinputandoutput
streams.
Withdatacomingfrommultiplesourcesandthroughdifferentpaths, data
enteringthedeviceisoftendelayed.Tohandlethisproblem,theIDT72V73250
hasaFrameEvaluationfeaturetoallowindividualstreamstobeoffsetfromthe
framepulseinhalfclock-cycleintervalsupto+7.5clockcycles.
The IDT72V73250 also provides a JTAG test access port, memory block
programming,asimplemicroprocessorinterfaceandautomaticST-BUS® /GCI
sensing to shorten setup time, aid in debugging and ease use of the device
withoutsacrificingcapabilities.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment.Although
allinputdatacomesinatthesamespeed, delayscanbecausedbyvariable
pathserialbackplanesandvariablepathlengthswhichmaybeimplemented
inlargecentralizedanddistributedswitchingsystems.Becausedataisoften
delayed, this feature is useful in compensating for the skew between input
streams.
FUNCTIONALDESCRIPTION
Eachinputstreamcanhaveitsowndelayoffsetvaluebyprogrammingthe
frameinputoffsetregisters(FOR,Table8).Themaximumallowableskewis+7.5
master clock (C32i) periods forward with a resolution of ½ clock period, see
Table9. Theoutputframecannotbeadjusted.
DATAANDCONNECTIONMEMORY
AlldatathatcomesinthroughtheRXinputsgothroughaserial-to-parallel
conversionbeforebeingstoredintointernalDataMemory.The8KHzframe
pulse(F32i)isusedtomarkthe125μsframeboundariesandtosequentially
addresstheinputchannelsinDataMemory.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
DataoutputontheTXstreamsmaycomefromeithertheserialinputstreams
(DataMemory)orfromthemicroprocessor(ConnectionMemory).Inthecase
thatRXinputdataistobeoutput,theaddressesinConnectionMemoryareused
tospecifyastreamandchanneloftheinput.TheConnectionMemoryissetup
in such a way that each location corresponds to an output channel for each
particularstream.Inthatway,morethanonechannelcanoutputthesamedata.
InProcessorMode,themicroprocessorwritesdatatotheConnectionMemory
locationscorrespondingtothestreamandchannelthatistobeoutput.Thelower
half(8leastsignificantbits)oftheConnectionMemoryisoutputeveryframeuntil
the microprocessor changes the data or mode of the channel. By using this
ProcessorModecapability,themicroprocessorcanaccessinputandoutput
time-slotsonaper-channelbasis.
ThetwomostsignificantbitsoftheConnectionMemoryareusedtocontrol
per-channelmodeoftheoutputstreams.Specifically,theMOD1-0bitsareused
to select Processor Mode, Constant or Variable delay Mode, and the high-
impedancestateofoutputdrivers.IftheMOD1-0bitsaresetto1-1accordingly,
onlythatparticularoutputchannel(8bits)willbeinthehigh-impedancestate.
Ifhowever,theODEinputpinisLOWandtheOutputStandbyBitintheControl
RegisterisLOW, alloftheoutputswillbeinahigh-impedancestateevenifa
particular channel in Connection Memory has enabled the output for that
channel.Inotherwords,theODEpinandOutputStandBycontrolbitaremaster
output enables for the device (See Table 3).
The IDT72V73250 provides the Frame Evaluation input to determine
differentdatainputdelayswithrespecttotheframepulseF32i.Ameasurement
cycleisstartedbysettingtheStartFrameEvaluationbitoftheControlRegister
LOWforatleastoneframe.WhentheStartFrameEvaluationbitintheControl
RegisterischangedfromLOWtoHIGH,theevaluationstarts.Twoframeslater,
theCompleteFrameEvaluationbitoftheFrameAlignmentRegisterchanges
fromLOWtoHIGHtosignalthatavalidoffsetmeasurementisreadytoberead
frombits0 to12oftheFrameAlignmentRegister.TheStartFrameEvaluation
bitmustbesettozerobeforeanewmeasurementcycleisstarted.
InST-BUS® mode,thefallingedgeoftheframemeasurementsignal(Frame
Evaluation)isevaluatedagainstthefallingedgeoftheST-BUS® framepulse.
InGCImode,therisingedgeofFrameEvaluationisevaluatedagainsttherising
edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of
theFrameAlignmentRegister.
MEMORYBLOCKPROGRAMMING
TheIDT72V73250providesuserswiththecapabilityofinitializingtheentire
Connection Memory block in two frames. To set bits 14 and 15 of every
Connection Memory location, first program the desired pattern in the Block
ProgrammingDataBits(BPD1-0),locatedinbits7and8oftheControlRegister.
The block programming mode is enabled by setting the Memory Block
ProgrambitoftheControlRegisterHIGH.WhentheBlockProgrammingEnable
5
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
bitoftheControlRegisterissettoHIGH,theBlockProgrammingData willbe
loadedintothebits14and15ofeveryConnectionMemorylocation.Theother
ConnectionMemorybits(bit0tobit13)areloadedwithzeros.Whenthememory
block programming is complete, the device resets the Block Programming
Enable,BlockProgrammingData1-0 andMemoryBlockProgrambitstozero.
configuration.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit,theBlockProgrammingDatabits,theBeginBlockProgrammingEnable,the
Output Stand By , Start Frame Evaluation, Output Enable Indication, and
SoftwareReset.AsexplainedintheMemoryBlockProgrammingsection,the
Block Programming Enable begins the programming if the Memory Block
Programbitisenabled.ThisallowstheentireConnectionMemoryblocktobe
programmedwiththeBlockProgrammingDatabits.IftheODEpinisLOW,the
OutputStandBybitenables(ifHIGH)ordisables(ifLOW)allTXoutputdrivers.
IftheODEpinisHIGH,thecontentsoftheOutputStandBybitisignoredand
all TX output drivers are enabled.
DELAYTHROUGHTHEIDT72V73250
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesonaper-channelbasis.Forvoiceapplications,variablethroughputdelay
isbestasitensureminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
informationismaintainedthroughtheswitch.
SOFTWARE RESET
TheSoftwareResetservesthesamefunctionasthehardwarereset.Aswith
the hard reset, the Software Reset must also be set HIGH for 20ns before
bringingtheSoftwareResetLOWagainfornormaloperation. OncetheSoftware
ResetisLOW,internalregistersandothermemoriesmaybereadorwritten.
During Software Reset, the microprocessor port is still able to read from all
internalmemories. TheonlywriteoperationallowedduringaSoftwareReset
istotheSoftwareResetbitintheControlRegistertocompletetheSoftwareReset.
Thedelaythroughthedevicevariesaccordingtothetypeofthroughputdelay
selectedintheMODbitsoftheConnectionMemory.
VARIABLE DELAY MODE (MOD1-0 = 0-0)
Inthismode,thedelayisdependentonlyonthecombinationofsourceand
destination channels and is independent of input and output streams. The
minimumdelayachievableintheIDT72V73250isthreetime-slots.Iftheinput
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
beoutputinthefollowingframe(channeln,framep+1).Thesameistrueifthe
inputchannelnisswitchedtooutputchanneln+1orn+2.Iftheinputchannel
nisswitchedtooutputchanneln+3,n+4,...,thenewoutputdatawillappearin
the same frame. Table 2 shows the possible delays for the IDT72V73250 in
Variable Delay mode.
CONNECTIONMEMORYCONTROL
IftheODEpinandtheOutputStandBybitareLOW,alloutputchannelswill
be in three-state. See Table 3 for detail.
IfMOD1-0oftheConnectionMemoryis1-0accordingly,theoutputchannel
will be in Processor Mode. In this case the lower eight bits of the Connection
MemoryareoutputeachframeuntiltheMOD1-0bitsarechanged.IfMOD1-
0oftheConnectionMemoryare0-1accordingly,thechannelwillbeinConstant
Delay Mode and bits 12-0 are used to address a location in Data Memory. If
MOD1-0 of the Connection Memory are 0-0, the channel will be in Variable
Delay Mode and bits 12-0 are used to address a location in Data Memory. If
MOD 1-0 of the Connection Memory are 1-1, the channel will be in High-
Impedancemodeandthatchannelwillbeinthree-state.
CONSTANT DELAY MODE (MOD1-0 = 0-1)
Inthismode,frameintegrityismaintainedinallswitchingconfigurationsby
makinguseofamultipledatamemorybuffer.Inputchanneldataiswritteninto
thedatamemorybuffersduringframenwillbereadoutduringframen+2. In
theIDT72V73250,theminimumthroughputdelayachievableinConstantDelay
mode will be one frame plus one channel. See Table 1.
OUTPUT ENABLE INDICATION
TheIDT72V73250hasthecapabilitytoindicatethestateoftheoutputs(active
orthree-state)byenablingtheOutputEnableIndicationintheControlRegister.
IntheOutputEnableIndicationmodehowever,onlyhalfoftheoutputstreams
areavailable. Ifthissamecapabilityisdesiredwithall16streams,thiscanbe
accomplished by using two IDT72V73250 or one IDT72V73260 devices. In
onedevice,theAllOutputEnablebitissettoaonewhileintheothertheAllOutput
Enableissettozero. Inthisway,onedeviceactsastheswitchandtheother
asathree-statecontroldevice,seeFigure5. ItisimportanttonoteiftheTSI
deviceisprogrammedforAllOutputEnableandtheOutputEnableIndication
isalsoset,thedevicewillbeintheAllOutputEnablemodenotOutputEnable
Indication. Touseall16streams,setOutputEnableIndicationintheControl
Registertozero.
MICROPROCESSORINTERFACE
TheIDT72V73250’smicroprocessorinterfacelookslikeastandardRAM
interfacetoimproveintegrationintoasystem.Witha15-bitaddressbusanda
16-bitdatabus,readsandwritesaremappeddirectlyintoDataandConnection
memories. By allowing the internal memories to be randomly accessed, the
controllingmicroprocessorhasmoretimetomanageotherperipheraldevices
andcanmoreeasilyandquicklygatherinformationandsetuptheswitchpaths.
Table4showsthemappingoftheaddressesintointernalmemoryblocks.
MEMORYMAPPING
Theaddressbusonthemicroprocessorinterfaceselectstheinternalregisters
andmemoriesoftheIDT72V73250.
INITIALIZATIONOFTHEIDT72V73250
Thetwomostsignificantbitsoftheaddressselectbetweentheregisters,Data
Memory,andConnectionMemory.IfA14andA13areHIGH,A12-A0areused
toaddresstheDataMemory.IfA14isHIGHandA13isLOW,A12-A0areused
toaddressConnectionMemory. IfA14isLOWandA13isHIGHA12-A0are
usedtoselecttheControlRegister,FrameAlignmentRegister,andFrameOffset
Registers. SeeTable4formappings.
Afterpowerup,thestateoftheConnectionMemoryisunknown. Assuch,
theoutputsshouldbeputinhigh-impedancebyholdingtheODEpinLOW. While
theODEisLOW,themicroprocessorcaninitializethedevicebyusingtheBlock
Programmingfeatureandprogramtheactivepathsviathemicroprocessorbus.
Oncethedeviceisconfigured,theODEpin(orOutputStandBybitdepending
oninitialization)canbeswitchedtoenabletheTSIswitch.
AsexplainedintheInitializationsections,aftersystempower-up,theControl
Registershouldbeprogrammedimmediatelytoestablishthedesiredswitching
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IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
TABLE—1CONSTANTTHROUGHPUT
DELAY VALUE
TABLE2—VARIABLETHROUGHPUT
DELAY VALUE
Delay for Constant Throughput Delay Mode
Delay for Variable Throughput Delay Mode
Input Rate
(m – output channel number)
(n – input channel number)
Input Rate
(m – output channel number; n – input channel number)
m ≤ n+2
m > n+2
32.768 Mb/s
512+(512-n)+mtime-slots
32.768 Mb/s
512-(n-m)time-slots
(m-n)time-slots
TABLE3—OUTPUTHIGH-IMPEDANCECONTROL
Bits MOD1-0 Values in
ConnectionMemory
ODE pin
OSB bit in Control
Register
Output Status
1 and 1
Don’tCare
Don’tCare
PerChannel
High-Impedance
High-Impedance
Enable
Any, other than 1 and 1
Any, other than 1 and 1
Any, other than 1 and 1
Any, other than 1 and 1
0
0
1
1
0
1
0
1
Enable
Enable
TABLE 4—INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
A14
A13 A12 A11 A10 A9
A8
STA3 STA2 STA1 STA0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
STA3 STA2 STA1 STA0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R/W
A7
A6
A5
A4
A3
A2 A1
A0 R/W
Location
1
1
0
0
0
0
0
0
1
0
1
1
1
1
1
1
R
Data Memory
ConnectionMemory
ControlRegister
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R/W
R
FrameAlignRegister
FrameOffsetRegister0
FrameOffsetRegister1
FrameOffsetRegister2
FrameOffsetRegister3
R/W
R/W
R/W
R/W
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IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
TABLE 5—CONTROL REGISTER (CR) BITS
ResetValue:
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRS
OEI OEPOL AOE
0
0
MBP
BPD1 BPD0
BPE
OSB
SFE
0
0
0
0
BIT
NAME
DESCRIPTION
15
SRS
A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.
(SoftwareReset)
14
13
OEI
When1,theTX8-15/OEI0-7pinswillbeOEI0-7andreflecttheactiveorhigh-impedancestateoftheircorrespondingoutput
(OutputEnableIndication) datastreams. When0,thisfeatureisdisabledandthesepinsareusedasoutputdatastreamsTX8-15.
OEPOL
(OutputEnablePolarity)
When1,aoneonanOutputEnableIndicationpindenotesanactivestateontheoutputdatastream;zeroonanOutputEnableIndication
pindenoteshigh-impedancestate.When0,aoneonanOutputEnableIndicationpindenoteshigh-impedanceandazerodenotes
andactivestate.
12
AOE
(AllOutputEnable)
When1,TX0-15willbehaveasOEI0-15accordingly. Theseoutputswillreflecttheactiveorhigh-impedancestateofthe
correspondingoutputdatastreams(TX0-15)inanotherIDT72V73250ifprogrammedidentically. When0,theTSIoperatesinthe
normalswitchmode.
11-10
9
Unused
MBP
Mustbezerofornormaloperation.
When1,theConnectionMemoryblockprogrammingfeatureisreadyfortheprogrammingofConnectionMemoryHIGHbits,bit
(Memory Block Program) 14tobit15.When0,thisfeatureisdisabled.
8-7
BPD1-0
ThesebitscarrythevaluetobeloadedintotheConnectionMemoryblockwheneverthememoryblockprogrammingfeature
(BlockProgramming
Data)
isactivated. AftertheMemoryBlockProgrambitintheControlRegisterissetto1andtheBlockProgrammingEnableissetto
1, thecontentsofthebitsBlockProgrammingData1-0areloadedintobit15and14oftheConnectionMemory.Bit13tobit0of
the Connection Memory are set to 0.
6
BPE
Azerotoonetransitionofthisbitenablesthememoryblockprogrammingfunction.TheBlockProgrammingEnableand
BlockProgrammingData1-0bitsintheControlRegister havetobedefinedinthesamewriteoperation.OncetheBlockProgramming
EnablebitissetHIGH,thedevicerequirestwoframestocompletetheblockprogramming.Aftertheprogrammingfunctionhas
finished, the Block Programming Enable, Memory Block Program and Block Programming Data 1-0 bits will be reset to
zerobythedevicetoindicatetheoperationiscomplete.
(BeginBlock
ProgrammingEnable)
5
4
OSB
(OutputStandBy)
WhenODE=0andOutputStandBy=0, theoutputdriversofthetransmitserialstreamsareinhigh-impedancemode. When
either ODE = 1 or Output Stand By =1, the output serial streams drivers function normally.
SFE
AzerotoonetransitioninthisbitstartstheFrameEvaluationprocedure.WhentheCompleteFrameEvaluationbitintheFrame
AlignmentRegisterchangesfromzerotoone,theevaluationprocedurestops.TostartanotherFrameEvaluationcycle,setthis
bittozeroforatleastoneframe.
(StartFrameEvaluation)
3-0
Unused
Mustbezerofornormaloperation.
TABLE 6—CONNECTION MEMORY BITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MOD1 MOD0
0
SAB3 SAB2 SAB1 SAB0 CAB8 CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
Description
Bit
Name
15,14 MOD1-0
MOD1
MOD0
MODE
(SwitchingModeSelection)
0
0
1
1
0
1
0
1
VariableDelaymode
ConstantDelaymode
Processormode
OutputHigh-impedance
13
Unused
Mustbezerofornormaloperation.
12-9 SAB3-0
(SourceStreamAddressBits)
CAB8-0
(SourceChannelAddressBits)
Thebinaryvalueisthenumberofthedatastreamforthesourceoftheconnection.
8-0
Thebinaryvalueisthenumberofthechannelforthesourceoftheconnection.
8
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
TABLE 7— FRAME ALIGNMENT REGISTER (FAR) BITS
ResetValue:
0000H.
12
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
0
0
CFE
FD12 FD11 FD10
Description
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Bit
Name
15-14 Unused
Mustbezerofornormaloperation.
13
CFE (Complete
FrameEvaluation)
WhenCompleteFrameEvaluation=1,theFrameEvaluationiscompletedandbitsFD12toFD0bitscontainsavalidframealignmentoffset.
Thisbitisresettozero, whenStartFrameEvaluationbitintheControlRegisterischangedfrom1to0.
12
LOW
FD12
ThefallingedgeofFrameEvaluation(orrisingedgeforGCImode)issampledduringtheC32i-HIGHphase(FD12=1)orduringtheC32i-
(Frame Delay Bit 12) phase(FD12=0).Thisbitallowsthemeasurementresolutionto½C32icycle.Thisbitisresettozerowhen
oftheControlRegisterchangesfrom1to0.
theStartFrameEvaluationbit
11-0 FD11-0
Thebinaryvalueexpressedinthesebitsreferstothemeasuredinputoffsetvalue.ThesebitsareresettozerowhentheStartFrameEvaluation
bit of the Control Register changes from 1 to 0. (FD11 – MSB, FD0 – LSB)
(Frame Delay Bits)
ST-BUS® Frame
C32i
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16
Offset Value
FE Input
(FD[11:0] = 06
H)
(FD12 = 0, sample at CLK LOW phase)
GCI Frame
C32i
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
Offset Value
FE Input
(FD[11:0] = 09
H)
(FD12 = 1, sample at CLK HIGH phase)
5933 drw04
Figure 1. Example for Frame Alignment Measurement
9
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
TABLE 8— FRAME INPUT OFFSET REGISTER (FOR) BITS
Reset Value:0000H forallFORregisters.
Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FOR0Register
FOR1Register
FOR2Register
FOR3Register
OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
Name(1)
Description
OFn2, OFn1, OFn0,
(Offset Bits 2, 1 & 0)
Thesethreebitsdefinehowlongtheserialinterfacereceivertakestorecognizeandstorebit0fromthRXinputpin:i.e.,tostartanew
frame. Theinputframeoffsetcanbeselectedto+7.5clockperiodsfromthepointwheretheexternalframepulseinputsignalisappliedto
the F32i input of the device. See Figure 2.
DLEn
ST-BUS® and
GCI mode:
DLEn = 0, offset is on the clock boundary.
DLEn = 1, offset is a half clock cycle off of the clock boundary.
NOTE:
1. n denotes an input stream number from 0 to 15.
10
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
TABLE 9— OFFSET BITS (OFn2, OFn1, OFn0, DLEn) & FRAME DELAY BITS
(FD12,FD2-0)
MeasurementResultfrom
Corresponding
InputStream
Offset
Frame Delay Bits
OffsetBits
FD12
1
FD2
0
FD1
0
FD0
0
OFn2
OFn1
OFn0
DLEn
Noclockperiodshift(Default)
+ 0.5 clock period shift
+ 1.0 clock period shift
+ 1.5 clock period shift
+ 2.0 clock period shift
+ 2.5 clock period shift
+ 3.0 clock period shift
+ 3.5 clock period shift
+ 4.0 clock period shift
+ 4.5 clock period shift
+5.0 clock period shift
+5.5 clock period shift
+6.0 clock period shift
+6.5 clock period shift
+7.0 clock period shift
+7.5 clock period shift
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
®)
F32i(ST-BUS
®)
C32i(ST-BUS
RX Stream
(32.768 Mb/s)
Bit 4
Bit 5
Bit 5
Bit 7
Bit 6
Bit 7
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
(32.768 Mb/s)
Bit 6
RX Stream
(32.768 Mb/s)
offset = 0, DLE = 1
Bit 4
Bit 7
Bit 6
Bit 5
F32i (GCI)
C32i (GCI)
RX Stream
(32.768 Mb/s)
Bit 0
Bit 1
Bit 0
Bit 2
Bit 1
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
(32.768 Mb/s)
Bit 2
RX Stream
(32.768 Mb/s)
offset = 0, DLE = 1
Bit 2
Bit 0
Bit 1
5933 drw05
Figure 2. Examples for Input Offset Delay Timing in 32.768 Mb/s mode
11
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
•Test Reset (TRST)
ResettheJTAGscanstructure. ThispinisinternallypulledtoVCC whenit
is not driven from an external source.
JTAGSUPPORT
TheIDT72V73250JTAGinterfaceconformstotheBoundary-Scanstandard
IEEE-1149.1.Thisstandardspecifiesadesign-for-testabilitytechniquecalled
Boundary-Scan test (BST). The operation of the boundary-scan circuitry is
controlledbyanexternaltestaccessport(TAP)Controller.
INSTRUCTION REGISTER
InaccordancewiththeIEEE-1149.1standard,theIDT72V73250usespublic
instructions.TheIDT72V73250JTAGinterfacecontainsafour-bitinstruction
register.InstructionsareseriallyloadedintotheinstructionregisterfromtheTDI
whentheTAPControllerisinitsshift-IRstate.Subsequently,theinstructionsare
decodedtoachievetwobasicfunctions:toselectthetestdataregisterthatmay
operatewhiletheinstructioniscurrent,andtodefinetheserialtestdataregister
path, which is used to shift data between TDI and TDO during data register
scanning. SeeTable12belowforInstructiondecoding.
TEST ACCESS PORT (TAP)
The Test Access Port (TAP) provides access to the test functions of the
IDT72V73250.Itconsistsofthreeinputpinsandoneoutputpin.
•Test Clock Input (TCK)
TCKprovidestheclockforthetestlogic.TheTCKdoesnotinterferewithany
on-chipclockandthusremainsindependent.TheTCKpermitsshiftingoftest
data into or out of the Boundary-Scan register cells concurrently with the
operationofthedeviceandwithoutinterferingwiththeon-chiplogic.
•Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controllertocontrolthetestoperations.TheTMSsignalsaresampledatthe
risingedgeoftheTCKpulse.ThispinisinternallypulledtoVCCwhenitisnot
driven from an external source.
TESTDATAREGISTER
AsspecifiedinIEEE-1149.1,theIDT72V73250JTAGInterfacecontainstwo
testdataregisters:
•The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
arrangedtoformascanpatharoundtheboundaryoftheIDT72V73250core
logic.
•Test Data Input (TDI)
•The Bypass Register
Serialinputdataappliedtothisportisfedeitherintotheinstructionregister
orintoatestdataregister, dependingonthesequencepreviouslyappliedto
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.
•TestDataOutput(TDO)
TheBypassregisterisasinglestageshiftregisterthatprovidesaone-bitpath
from TDI to TDO. The IDT72V73250 boundary scan register bits are shown
inTable14.Bit0isthefirstbitclockedout.Allthree-stateenablebitsareactive
HIGH.
DependingonthesequencepreviouslyappliedtotheTMSinput,thecontents
ofeithertheinstructionregisterordataregisterareseriallyshiftedoutthrough
the TDO pin on the falling edge of each TCK pulse. When no data is shifted
throughtheboundaryscancells,theTDOdriverissettoahigh-impedancestate.
ID CODE REGISTER
AsspecifiedinIEEE-1149.1,thisinstructionloadstheIDRwiththeRevision
Number, DeviceID, JEDECID, andIDRegisterIndicatorBit. SeeTable10.
TABLE10—IDENTIFICATIONREGISTERDEFINITIONS
INSTRUCTION FIELD
RevisionNumber(31:28)
IDT Device ID (27:12)
VALUE
DESCRIPTION
0x0
Reservedforversionnumber
0x437
0x33
1
DefinesIDTpartnumber
IDT JEDEC ID (11:1)
AllowsuniqueidentificationofdevicevendorasIDT
IndicatesthepresenceofanIDregister
IDRegisterIndicatorBit(Bit0)
TABLE 11— SCAN REGISTER SIZES
REGISTER NAME
BIT SIZE
Instruction(IR)
4
1
Bypass (BYR)
Identification(IDR)
Boundary Scan (BSR)
32
Note(1)
NOTES:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on
the IDT website (www.idt.com), or by contacting your local IDT sales representative.
12
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
TABLE12—SYSTEMINTERFACEPARAMETERS
INSTRUCTION
EXTEST
CODE
0000
1111
0010
0100
0011
0001
DESCRIPTION
Forcescontentsoftheboundaryscancellsontothedeviceoutputs(1).Placestheboundaryscanregister(BSR)betweenTDIandTDO.
BYPASS
Places the bypass register (BYR) between TDI and TDO.
IDCODE
LoadstheIDregister(IDR)withthevendorIDcodeandplacestheregisterbetweenTDIandTDO.
Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state.
Placesthebypassregister(BYR)betweenTDIandTDO. Forcescontentsoftheboundaryscancellsontothedeviceoutputs.
Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs(2) and outputs(1) to be
capturedintheboundaryscancellsandshiftedseriallythroughTDO.PRELOADallowsdatatobeinputseriallyintotheboundary
scan cells via the TDI.
HIGH-Z
CLAMP
SAMPLE/PRELOAD
RESERVED
Allothercodes Severalcombinationsarereserved. Donotuseothercodesthanthoseidentifiedabove.
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS and TRST.
TABLE 13 — JTAG AC ELECTRICAL CHARACTERISTICS (1,2,3,4)
SYMBOL
tJCYC
tJCH
PARAMETER
JTAG Clock Input Period
JTAG Clock High
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAGReset
MIN.
100
40
MAX.
⎯
UNITS
ns
⎯
ns
tJCL
40
⎯
ns
tJR
⎯
⎯
50
3(1)
3(1)
⎯
ns
tJF
ns
tJRST
tJRSR
tJCD
ns
JTAG Reset Recovery
JTAGDataOutput
JTAGDataOutputHold
JTAGSetup
50
⎯
ns
⎯
0
25
ns
tJDC
⎯
ns
tJS
15
⎯
ns
tJH
JTAG Hold
15
⎯
ns
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
tJCYC
tJR
tJF
tJCL
tJCH
TCK
Device Inputs(1)
TDI/TMS
tJH
tJS
tJDC
Device Outputs(2)
TDO
tJCD
tJRSR
TRST
5933 drw06
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
Figure 3. JTAG Timing Specifications
13
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
TABLE 14— BOUNDARY SCAN REGISTER BITS
Boundary Scan Bit 0 to bit 119
Boundary Scan Bit 0 to bit 119
Device Pin
Input
Scan Cell
Output
Scan Cell
Three-State
Control
Device Pin
Input
Scan Cell
Output
Scan Cell
Three-State
Control
ODE
0
1
2
3
4
5
6
7
TX15/OEI7
TX14/OEI6
72
74
73
75
RESET
C32i
F32i
FE
DS
CS
R/W
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DTA
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
TX13/OEI5
TX12/OEI4
TX11/OEI3
TX10/OEI2
TX9/OEI11
TX8/OEI0
RX15
RX14
RX13
RX12
RX11
RX10
RX9
76
78
80
82
84
86
77
79
81
83
85
87
88
89
90
91
92
93
94
95
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
RX7
RX6
RX5
RX4
RX3
RX2
RX1
96
98
97
99
100
102
104
106
108
110
101
103
105
107
109
111
23
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
70
112
113
114
115
116
117
118
119
24
27
30
33
36
39
42
45
48
51
54
57
60
63
66
69
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
RX0
D0
14
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATING
CONDITIONS(1)
Symbol
Parameter
Min.
Max.
Unit
Symbol
VCC
Parameter
Min.
3.0
Typ.
3.3
⎯
Max.
3.6
Unit
V
VCC
Vi
SupplyVoltage
-0.5
GND -0.3
-50
+4.0
VCC +0.3
50
V
V
Positive Supply
Input HIGH Voltage
InputLOWVoltage
VoltageonDigitalInputs
CurrentatDigitalOutputs
StorageTemperature
VIH
2.0
VCC
0.8
V
IO
mA
°C
W
VIL
-0.3
-40
⎯
V
TS
-55
+125
2
TOP
OperatingTemperature
Industrial
25
+85
°C
PD
PackagePowerDissapation
⎯
NOTE:
NOTE:
1. Voltages are with respect to Ground unless otherwise stated.
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
DCELECTRICALCHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
160
60
Units
mA
μA
μA
V
(2)
ICC
SupplyCurrent
@32.768Mb/s
_
-
_
-
(3,4)
IIL
InputLeakage(inputpins)
High-impedanceLeakage
Output HIGH Voltage
OutputLOWVoltage
(3,4)
IOZ
-
-
60
(5)
VOH
2.4
-
-
-
(6)
VOL
-
0.4
V
NOTES:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Outputs unloaded.
3. 0 ≤ V ≤ VCC.
4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V).
5. IOH = 10 mA.
6. IOL = 10 mA.
15
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-TIMINGPARAMETER
MEASUREMENTVOLTAGELEVELS
Symbol Rating
Level Unit
VTT
VHM
VLM
TTLThreshold
1.5
2.0
0.8
V
V
TTLRise/FallThresholdVoltageHIGH
TTLRise/FallThresholdVoltageLOW
InputPulseLevels
V
V
tR, tF
InputRise/FallTimes
1
ns
V
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
V
CL(1)
Cin(2)
50
8
pF
pF
InputCapacitance
NOTES:
1. JTAG CL is 30pF.
2. For 144 TQFP.
VDD
3.3v
50Ω
330Ω
Z0 = 50Ω
I/O
D.U.T.
30pF*
510Ω
5933 drw07
5933 Drw08
Figure 4. Output Load
Figure 5. Output Load
6
5
4
3
2
1
20 30 50 80 100
Capacitance (pF)
200
5933 drw09
Figure 6. Lumped Capacitive Load, Typical Derating
16
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLOCK
Symbol
Parameter
Min.
Typ.
Max.
Units
tFPW
FramePulseWidth
Bit rate = 32.768 Mb/s
13
5
⎯
⎯
⎯
31
⎯
⎯
ns
ns
ns
tFPS
tFPH
tCP
FramePulseSetuptimebeforeC32ifalling
FramePulseHoldTimefromC32ifalling
10
C32iPeriod
Bit rate = 32.768 Mb/s
29
13
13
30.5
15
35
20
20
ns
ns
ns
tCH
tCL
C32i Pulse Width HIGH
Bit rate = 32.768 Mb/s
C32i Pulse Width LOW
Bit rate = 32.768 Mb/s
15
17
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
(1)
ODE
t
RESET
tZR
tRZ
tRZ
tRS
TX
tODELZ
ODE
5933 drw10
NOTE:
1. To guarantee TX outputs remain in High-Impedance.
Figure 7. Reset and ODE Timing
C32i
(ST-BUS® mode)
C32i
(GCI mode)
tSOD
tCHZ
ODE
tODEA
TX
TX
t
ODEL
Z
tODEHZ
VALID DATA
tCLZ
tSIH
TX
VALID DATA
VALID DATA
5933 drw12
5933 drw11
Figure 8. Serial Output and External Control
Figure 9. Output Driver Enable (ODE)
18
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MICROPROCESSORINTERFACETIMING
Symbol
Parameter
Min.
0
Typ.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
15
Max.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
25
Units
ns
tCSS
CS Setup from DS falling
tRWS
tADS
R/WSetupfromDSfalling
AddressSetupfromDSfalling
CS Hold after DS rising
3
ns
2
ns
tCSH
0
ns
tRWH
tADH
R/W Hold after DS Rising
Address Hold after DS Rising
Data Setup from DTA LOW on Read
DataHoldonRead
3
ns
2
ns
tDDR
tDHR
tDSW
tSWD
tDHW
tAKD
1
ns
10
10
⎯
5
ns
DataSetuponWrite(RegisterWrite)
ValidDataDelayonWrite(ConnectionMemoryWrite)
DataHoldonWrite
⎯
⎯
⎯
⎯
0
ns
ns
⎯
ns
AcknowledgmentDelay:
Reading/WritingRegisters
Reading/WritingMemory
AcknowledgmentHoldTime
DataStrobeSetupTime
32
80
ns
ns
@ 32.768 Mb/s
tAKH
⎯
6
⎯
⎯
—
20
⎯
—
ns
ns
ns
tDSS
tDSPW
DataStrobePulseWidthHigh
28
19
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
C32i GCI
C32iST-BUS®
tDSPW
tDSS
DS
tCSH
tCSS
CS
tRWH
tRWS
R/W
tADH
tADS
VALID ADDRESS
A0-A11
tDHR
D0-D15
READ
VALID READ DATA
tSWD
tDSW
tDHW
D0-D15
WRITE
VALID WRITE DATA
tDDR
tAKH
tAKD
DTA
5933 drw13
NOTE:
1. For quick microprocessor access tDSS must be met. In this case tAKD = tAKD (max) - C32i (period)+ tDSS.
Figure 10. Motorola Non-Multiplexed Bus Timing
20
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
21
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS ⎯ SERIAL STREAM (ST-BUS® and GCI)
Symbol
Parameter
Min.
Typ.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Max.
⎯
⎯
12
Units
tSIS
RXSetupTime
2
ns
tSIH
RXHoldTime
4
ns
tSOD
tCHZ
tCLZ
Clock to Valid Data
4
ns
Clock to High-Z
⎯
3
9
ns
Clock to Low-Z
⎯
⎯
9
ns
tODE
tODEHZ
tODELZ
tOEI
OutputDriverEnabletoResetHigh
OutputDriverEnable(ODE)toHigh-Z
Output Driver Enable (ODE) to Low-Z
OutputEnableIndicator
Active to High-Z on Master Reset
High-Z to Active on Master Reset
Resetpulsewidth
5
ns
⎯
5
ns
⎯
12
ns
8
ns
tRZ
⎯
⎯
20
6
12
ns
tZR
12
ns
tRS
⎯
16
ns
tODEA
Output Driver Enable to Active
ns
22
IDT72V732503.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURERANGE
®
®
23
ORDERINGINFORMATION
IDT
XXXXX
XX
XX
Device Type Package
Process/
Temp. Range
Blank
Commercial (-40ºC to +85ºC)
BBG
DAG
PBGA - Green (PBGA, BB144-1)
TQFP – Green (TQFP, DA144-1)
8192 x 8192 – 3.3V Time Slot Interchange
Digital Switch
72V73250
DATASHEETDOCUMENTHISTORY
08/15/2001
09/24/2001
12/19/2001
12/21/2001
03/25/2002
08/02/2002
05/27/2003
06/21/2004
12/04/2012
pgs. 2, 3, 18, 19, 21, 22, 23 and 24.
pgs. 2, 11, 21, 23 and 24.
pgs. 1-14 and 17-24.
pgs. 1, 4-6, 8, 13, 15-17 and 22.
pgs. 15 and 16.
pg. 8.
pg. 16.
pgs. 19 and 20.
pg. 24
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for Tech Support:
408-330-1552
email:TELECOMhelp@idt.com
www.idt.com
24
相关型号：
72V73273BBBLANK
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS
IDT
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