72V73260DAG8 [IDT]
Digital Time Switch, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144;
| 型号： | 72V73260DAG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Digital Time Switch, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144 电信 电信集成电路 |
| 文件： | 总26页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
PRELIMINARY
IDT72V73260
16,384 X 16,384
•
•
Available in 144-pin (13mm x 13mm) Plastic Ball Grid Array
(PBGA) and 144-pin (20mm x 20mm) Thin Quad Flatpack (TQFP)
Operating Temperature Range -40°C to +85°C
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
16K x 16K non-blocking switching at 32.768Mb/s
32 serial input and output streams
Accepts single-bit single-data streams at 32.768Mb/s
Per-channel Variable Delay Mode for low-latency applications
Per-channel Constant Delay Mode for frame integrity applications
Automatic identification of ST-BUS® and GCI bus interfaces
Automatic frame offset delay measurement
Per-stream single data frame delay offset programming
Per-channel high-impedance output control
Direct microprocessor access to all internal memories
Memory block programming for quick setup
IEEE-1149.1 (JTAG) Test Port
DESCRIPTION:
TheIDT72V73260hasanon-blockingswitchcapacityof 16,384x16,384
channels at 32.768Mb/s. With 32 inputs and 32 outputs, programmable per
streamcontrol,andavarietyofoperatingmodestheIDT72V73260isdesigned
fortheTDMtimeslotinterchangefunctionineithervoiceordataapplications.
Some of the main features of the IDT72V73260 are LOW power 3.3 Volt
operation, automatic ST-BUS® /GCI sensing, memory block programming,
simplemicroprocessorinterface,JTAGTestAccessPort(TAP)andperstream
programmableinputoffsetdelay,variableorconstantthroughputmodes,output
enable andprocessormode.
3.3V Power Supply
FUNCTIONAL BLOCK DIAGRAM
RESET
VCC
GND
ODE
TX0
RX0
RX1
Data Memory
TX1
MUX
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
TX15
TX16/OEI0
TX17/OEI1
Connection
Memory
Internal
Registers
TX31/OEI15
RX31
Microprocessor Interface
Timing Unit
JTAG Port
DS CS
DTA
TRST
TMS TDI TCK TDO
C32i F32i
FE
R/W
A0-A15
D0-D15
5932 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS® isatrademarkofMitelCorp.
MAY 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
DSC-5932/8
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
PINCONFIGURATIONS
A1 BALL PAD CORNER
A
RX4
RX5
RX6
C32i RESET
ODE
RX0
TDI
RX1
RX2
RX3
RX7
TX0
TX1
TX4
TX3
TX2
TX7
TX6
TX5
TX10
TX9
TX12
TX11
RX11
TX14
TX13
RX10
TX15
RX8
RX9
B
C
D
E
F32i
FE
(1)
NC
TMS
TX8
TDO
TRST
DS
TCK
VCC
VCC
VCC
VCC
RX15
VCC
RX14
RX18
RX13
RX17
RX12
RX16
CS
R/W
A0
VCC
GND
GND
GND
GND
F
A1
A6
A2
A5
A3
A4
V
CC
RX21
RX22
RX20
RX23
RX19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
G
TX16/
OEI0
V
CC
CC
H
J
TX19/
OEI3
TX18/
OEI2
TX17/
OEI1
A9
A8
A7
V
VCC
TX20/
OEI4
A13
A12
A11
A10
D8
TX21/
OEI5
TX22/
OEI6
VCC
VCC
VCC
VCC
RX27
RX26
K
L
TX31/
OEI15
TX23/
OEI7
TX24/
OEI8
(1)
D2
NC
A15
DTA
D13
2
A14
D5
D1
RX30
TX26/
OEI10
TX30/
OEI14
TX25/
OEI9
D15
D14
1
D11
D12
3
D9
D10
4
D6
D7
5
D3
D4
6
D0
RX31
7
RX29
RX28
8
RX25
RX24
9
M
TX29/
OEI13
TX28/
OEI12
TX27/
OEI11
10
11
12
5932 drw02
NOTE:
1. NC = No Connect.
PBGA: 1mm pitch, 13mm x13mm (BB144-1, order code: BB)
TOP VIEW
2
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
PINCONFIGURATIONS(CONTINUED)
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
GND
VCC
TX15
TX14
TX13
TX12
GND
VCC
TX11
TX10
TX9
TX8
GND
VCC
TX7
TX6
TX5
TX4
GND
VCC
TX3
TX2
TX1
TX0
GND
VCC
TX28/OEI12
TX29/OEI13
TX30/OEI14
TX31/OEI15
GND
VCC
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
GND
VCC
D0
D1
D2
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
D3
GND
VCC
D4
D5
D6
D7
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
ODE
RESET
GND
VCC
D8
D9
138
139
140
141
142
D10
D11
GND
VCC
D12
D13
143
144
5932 drw03
PIN 1
NOTE:
1. NC = No Connect.
TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA)
TOP VIEW
3
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
PINDESCRIPTION
SYMBOL
A0-15
C32i
NAME
Address 0 to 15
Clock
I/O
DESCRIPTION
Theseaddresslinesaccessallinternalmemories.
I
I
I
Serialclockforshiftingdatain/outontheserialdatastream.Thisinputacceptsa32.768MHzclock.
ThisactiveLOWinputisusedbyamicroprocessortoactivatethemicroprocessorportofIDT72V73260.
CS
D0-15
DS
ChipSelect
Data Bus 0-15
DataStrobe
I/O Thesepinsarethedatabitsofthemicroprocessorport.
I
This activeLOWinputworks inconjunctionwithCStoenablethereadandwriteoperations andsets the
data bus lines (D0-D15).
DTA
DataTransfer
Acknowledgment
O
Indicatesthatadatabustransferiscomplete.Whenthebuscycleends,thispindrivesHIGHandthengoes
high-impedance,allowingforfasterbus cycles withaweakerpull-upresistor.Apull-upresistoris required
to hold a HIGH level when the pin is in high-impedance.
FE
Frame Evaluation
FramePulse
I
I
This input can be used to measure delay in the data path by comparing the frame pulse, F32i, with this input.
F32i
Thisinputacceptsandautomaticallyidentifiesframesynchronizationsignalsformattedaccordingto
ST-BUS®andGCIspecifications.
GND
ODE
Ground
GroundRail
OutputDriveEnable
I
I
ThisistheoutputenablecontrolfortheTXserialoutputs.WhentheODEinputisLOWandtheOutputStand
BybitoftheControlRegisterisLOW,allTXoutputsareinahigh-impedancestate.IfthisinputisHIGH,theTX
outputdriversareenabled.However,eachchannelmaystillbeputintoahigh-impedancestatebyusingthe
per-channelcontrolbitsintheConnectionMemory.
RESET
DeviceReset
Read/Write
ThisinputputstheIDT72V73260intoaresetstatethatclearsthedeviceinternalcounters,registersand
brings TX0-31andD0-D15intoa high-impedance state. The RESET pinmustbe heldLOWfora minimum
of 20ns to properly reset the device.
R/W
I
I
Thisinputcontrolsthedirectionofthedatabuslines(D0-D15)duringamicroprocessoraccess.
Serialdatainputstream.Thesestreams haveadatarateof32.768Mb/s.
RX0-31 DataStream
Input 0 to 31
TCK
TDI
TestClock
I
I
ProvidestheclocktotheJTAGtestlogic.
TestSerialData In
JTAGserialtestinstructionsanddataareshiftedinonthispin.ThispinispulledHIGHbyaninternalpull-up
when not driven.
TDO
TMS
TRST
TestSerialDataOut
TestModeSelect
TestReset
O
I
JTAGserialdatais outputonthis pinonthefallingedgeofTCK. This pinis heldinhigh-impedancestate
whenJTAGscanis notenabled.
JTAGsignalthatcontrolsthestatetransitionsoftheTAPcontroller.ThispinispulledHIGHbyaninternal
pull-up when not driven.
I
AsynchronouslyinitializestheJTAGTAPcontrollerbyputtingitintheTest-Logic-Resetstate.Thispinis
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
toensurethattheIDT72V73260isinthenormalfunctionalmode.
TX0-15 TXOutput0to15
(Three-StateOutputs)
O
O
Serialdataoutputstream.Thesestreams haveadatarateof 32.768Mb/s.
TX16-31/ TX Output 16 to 31/
OEI0-15 OutputEnable
Indication0to15
Whenall32outputstreamsareselectedviaControlRegister,thesepinsaretheoutputstreamsTX16toTX31
andoperateat32.768Mb/s.Whenoutputenablefunctionisselected,thesepinsreflecttheactiveor
high-impedancestatusforthecorrespondingoutputstreamOutputEnableIndication0-15.
(Three-StateOutputs)
VCC
VCC
+3.3 Volt Power Supply.
4
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
SERIAL DATA INTERFACE TIMING
DESCRIPTION(CONTINUED)
Fora32.768Mb/sserialdatarate,themasterclockfrequencywillberunning
at32.768MHzresultinginasingle-bitperclock. TheIDT72V73260provides
twodifferentinterfacetimingmodes,ST-BUS® orGCI.
The IDT72V73260 automatically detects the presence of an input frame
pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® Mode, data is
clockedoutonthefallingedgeandisclockedinonthesubsequentrising-edge.
SeeFigure14fortiming. InGCIMode,dataisclockedoutontherisingedge
andis clockedinonthe subsequentfallingedge. See Figure 15fortiming.
TheIDT72V73260iscapableofswitchingupto16,384x16,384channels
withoutblocking.Designedtoswitch64Kbit/sPCMorNx64Kbit/sdata,the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delayforvoice applications ona per-channelbasis.
The32serialinputstreams(RX)oftheIDT72V73260arerunat32.768Mb/s
allowing512channelsper125µsframe.Thedataratesontheoutputstreams
(TX)areidenticaltothoseontheinputstreams (RX).
Withtwomainoperatingmodes,ProcessorModeandConnectionMode,the
IDT72V73260 can easily switch data from incoming serial streams (Data
Memory)orfromthecontrollingmicroprocessorviaConnectionMemory.As
controlandstatusinformationiscriticalindatatransmission,theProcessorMode
isespeciallyusefulwhentherearemultipledevicessharingtheinputandoutput
streams.
Withdatacomingfrommultiplesources andthroughdifferentpaths,data
enteringthedeviceisoftendelayed.Tohandlethisproblem,theIDT72V73260
hasaFrameEvaluationfeaturetoallowindividualstreamstobeoffsetfromthe
framepulseinhalfclock-cycleintervalsupto+7.5clockcycles.
The IDT72V73260alsoprovides a JTAGtestaccess port, memoryblock
programming,asimplemicroprocessorinterfaceandautomaticST-BUS® /GCI
sensing to shorten setup time, aid in debugging and ease use of the device
withoutsacrificingcapabilities.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment.Although
allinputdatacomes inatthesamespeed,delays canbecausedbyvariable
pathserialbackplanesandvariablepathlengthswhichmaybeimplemented
inlargecentralizedanddistributedswitchingsystems.Becausedataisoften
delayed, this feature is useful in compensating for the skew between input
streams.
Eachinputstreamcanhaveitsowndelayoffsetvaluebyprogrammingthe
frameinputoffsetregisters(FOR,Table8).Themaximumallowableskewis+7.5
master clock (C32i) periods forward with a resolution of ½ clock period, see
Table9.Theoutputframecannotbeadjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
FUNCTIONALDESCRIPTION
The IDT72V73260 provides the Frame Evaluation input to determine
differentdatainputdelayswithrespecttotheframepulseF32i.Ameasurement
cycleisstartedbysettingtheStartFrameEvaluation bitoftheControlRegister
LOWforatleastoneframe.WhentheStartFrameEvaluationbitintheControl
RegisterischangedfromLOWtoHIGH,theevaluationstarts.Twoframeslater,
theCompleteFrameEvaluation bitoftheFrameAlignmentRegister changes
fromLOWtoHIGHtosignalthatavalidoffsetmeasurementisreadytoberead
frombits0 to12oftheFrameAlignmentRegister.TheStartFrameEvaluation
bitmustbesettozerobeforeanewmeasurementcycleisstarted.
InST-BUS® mode,thefallingedgeoftheframemeasurementsignal(Frame
Evaluation)isevaluatedagainstthefallingedgeoftheST-BUS® framepulse.
InGCImode,therisingedgeofFrameEvaluationisevaluatedagainsttherising
edge ofthe GCIframe pulse. See Table 7andFigure 1forthe descriptionof
theFrameAlignmentRegister.
DATAANDCONNECTIONMEMORY
AlldatathatcomesinthroughtheRXinputsgothroughaserial-to-parallel
conversionbeforebeingstoredintointernalDataMemory.The8KHzframe
pulse(F32i)isusedtomarkthe125µsframeboundariesandtosequentially
addresstheinputchannelsinDataMemory.
DataoutputontheTXstreamsmaycomefromeithertheserialinputstreams
(DataMemory)orfromthemicroprocessor(ConnectionMemory).Inthecase
thatRXinputdataistobeoutput,theaddressesinConnectionMemoryareused
tospecifyastreamandchanneloftheinput.TheConnectionMemoryissetup
in such a way that each location corresponds to an output channel for each
particularstream.Inthatway,morethanonechannelcanoutputthesamedata.
InProcessorMode,themicroprocessorwritesdatatotheConnectionMemory
locationscorrespondingtothestreamandchannelthatistobeoutput.Thelower
half(8leastsignificantbits)oftheConnectionMemoryisoutputeveryframeuntil
the microprocessor changes the data or mode of the channel. By using this
ProcessorModecapability,themicroprocessorcanaccessinputandoutput
time-slotsonaper-channelbasis.
ThetwomostsignificantbitsoftheConnectionMemoryareusedtocontrol
per-channelmodeoftheoutputstreams.Specifically,theMOD1-0bitsareused
to select Processor Mode, Constant or Variable delay Mode, and the high-
impedancestateofoutputdrivers.IftheMOD1-0bitsaresetto1-1accordingly,
onlythatparticularoutputchannel(8bits)willbeinthehigh-impedancestate.
Ifhowever,theODEinputpinisLOWandtheOutputStandbyBitintheControl
RegisterisLOW,alloftheoutputswillbeinahigh-impedancestateevenifa
particular channel in Connection Memory has enabled the output for that
channel.Inotherwords,theODEpinandOutputStandBycontrolbitaremaster
output enables for the device (See Table 3).
MEMORYBLOCKPROGRAMMING
TheIDT72V73260providesuserswiththecapabilityofinitializingtheentire
Connection Memory block in two frames. To set bits 14 and 15 of every
Connection Memory location, first program the desired pattern in the Block
ProgrammingDataBits(BPD1-0),locatedinbits7and8 oftheControlRegister.
The block programming mode is enabled by setting the Memory Block
Program bitoftheControlRegisterHIGH.WhentheBlockProgrammingEnable
bitoftheControlRegisterissettoHIGH,theBlockProgrammingdata willbe
loadedintothebits14and15ofeveryConnectionMemorylocation.Theother
ConnectionMemorybits(bit0tobit13)areloadedwithzeros.Whenthememory
block programming is complete, the device resets the Block Programming
Enable, BPD 1-0 and Memory Block Program bits to zero.
5
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
theOutputStandBy,StartFrameEvaluation,OutputEnableIndication and
SoftwareReset.AsexplainedintheMemoryBlockProgrammingsection,the
Block Programming Enable begins the programming if the Memory Block
Programbitisenabled.ThisallowstheentireConnectionMemoryblocktobe
programmedwiththeBlockProgrammingDatabits.IftheODEpinisLOW,the
OutputStandBybitenables(ifHIGH)ordisables(ifLOW)allTXoutputdrivers.
IftheODEpinisHIGH,thecontentsoftheOutputStandBybitisignoredand
all TX output drivers are enabled.
DELAYTHROUGHTHEIDT72V73260
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesonaper-channelbasis.Forvoiceapplications,variablethroughputdelay
isbestasitensureminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
informationismaintainedthroughtheswitch.
SOFTWARE RESET
Thedelaythroughthedevicevariesaccordingtothetypeofthroughputdelay
selectedintheMODbitsoftheConnectionMemory.
The Software Reset serves the same functionas the hardware reset. As
withthehardreset,theSoftwareResetmustalsobesetHIGHfor20nsbefore
bringingtheSoftwareResetLOWagainfornormaloperation. OncetheSoftware
ResetisLOW,internalregistersandothermemoriesmaybereadorwritten.
During Software Reset, the microprocessor port is still able to read from all
internalmemories.TheonlywriteoperationallowedduringaSoftwareReset
istotheSoftwareResetbitintheControlRegistertocompletetheSoftwareReset.
VARIABLE DELAY MODE (MOD1-0 = 0-0)
Inthismode,thedelayisdependentonlyonthecombinationofsourceand
destination channels and is independent of input and output streams. The
minimumdelayachievableintheIDT72V73260isthreetime-slots.Iftheinput
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
beoutputinthefollowingframe(channeln,framep+1).Thesameistrueifthe
inputchannelnisswitchedtooutputchanneln+1orn+2.Iftheinputchannel
nisswitchedtooutputchanneln+3,n+4,...,thenewoutputdatawillappearin
the same frame. Table 2shows the possible delays forthe IDT72V73260in
VariableDelaymode.
CONNECTIONMEMORYCONTROL
IftheODEpinandtheOutputStandBybitareLOW,alloutputchannelswill
be inthree-state. See Table 3fordetail.
IfMOD1-0oftheConnectionMemoryis1-0accordingly,theoutputchannel
willbeinProcessorMode. Inthis casethelowereightbits oftheConnection
MemoryareoutputeachframeuntiltheMOD1-0bitsarechanged.IfMOD1-
0oftheConnectionMemoryare0-1accordingly,thechannelwillbeinConstant
DelayMode andbits 13-0are usedtoaddress a locationinData Memory. If
MOD1-0 of the Connection Memory are 0-0, the channel will be in Variable
Delay Mode and bits 13-0 are usedto address a location in Data Memory. If
MOD 1-0 of the Connection Memory are 1-1, the channel will be in high-
Impedancemodeandthatchannelwillbeinthree-state.
CONSTANT DELAY MODE (MOD1-0 = 0-1)
Inthismode,frameintegrityismaintainedinallswitchingconfigurationsby
makinguseofamultipledatamemorybuffer.Inputchanneldataiswritteninto
thedatamemorybuffers duringframenwillbereadoutduringframen+2.In
theIDT72V73260,theminimumthroughputdelayachievableinConstantDelay
mode will be one frame plus one channel. See Table 1.
MICROPROCESSORINTERFACE
OUTPUT ENABLE INDICATION
TheIDT72V73260hasthecapabilitytoindicatethestateoftheoutputs(active
orthree-state)byenablingtheOutputEnableIndicationintheControlRegister.
IntheOutputEnableIndicationmodehowever,onlyhalfoftheoutputstreams
areavailable. Ifthissamecapabilityisdesiredwithall32streams,thiscanbe
accomplishedbyusingtwoIDT72V73260devices. Inonedevice,theAllOutput
EnablebitissettoaonewhileintheothertheAllOutputEnableissettozero.
Inthisway,onedeviceactsastheswitchandtheotherasathree-statecontrol
device,seeFigure5.ItisimportanttonoteiftheTSIdeviceisprogrammedfor
AllOutputEnableandtheOutputEnableIndicationisalsoset,thedevicewill
beintheAllOutputEnablemodenotOutputEnableIndication. Touseall32
streams,setOutputEnableIndicationintheControlRegistertozero.
TheIDT72V73260’s microprocessorinterfacelooks likeastandardRAM
interfacetoimproveintegrationintoasystem.Witha16-bitaddressbusanda
16-bitdatabus,readsandwritesaremappeddirectlyintoDataandConnection
memories. Byallowingthe internalmemories tobe randomlyaccessed, the
controllingmicroprocessorhasmoretimetomanageotherperipheraldevices
andcanmoreeasilyandquicklygatherinformationandsetuptheswitchpaths.
Table4showsthemappingoftheaddressesintointernalmemoryblocks.
MEMORYMAPPING
Theaddressbusonthemicroprocessorinterfaceselectstheinternalregisters
andmemoriesoftheIDT72V73260.
Thetwomostsignificantbitsoftheaddressselectbetweentheregisters,Data
Memory,andConnectionMemory.IfA15andA14areHIGH,A13-A0areused
toaddresstheDataMemory.IfA15isHIGHandA14isLOW,A13-A0areused
toaddress ConnectionMemory.IfA15is LOWandA14is HIGHA13-A0are
usedtoselecttheControlRegister,FrameAlignmentRegister,andFrameOffset
Registers.SeeTable4formappings.
AsexplainedintheInitializationsections,aftersystempower-up,theControl
Registershouldbeprogrammedimmediatelytoestablishthedesiredswitching
configuration.
INITIALIZATIONOFTHEIDT72V73260
Afterpowerup,thestateoftheConnectionMemoryisunknown. Assuch,
theoutputsshouldbeputinhigh-impedancebyholdingtheODEpinLOW. While
theODEisLOW,themicroprocessorcaninitializethedevicebyusingtheBlock
Programmingfeatureandprogramtheactivepathsviathemicroprocessorbus.
Oncethedeviceisconfigured,theODEpin(orOutputStandBybitdepending
oninitialization)canbeswitchedtoenabletheTSIswitch.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit,theBlockProgrammingDatabits,theBeginBlockProgrammingEnable,
6
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
TABLE— 1 CONSTANT THROUGHPUT
DELAYVALUE
TABLE2—VARIABLETHROUGHPUT
DELAYVALUE
Delay for Constant Throughput Delay Mode
Delay for Variable Throughput Delay Mode
InputRate
(m – output channel number)
(n – input channel number)
InputRate
(m – output channel number; n – input channel number)
m ≤ n+2
m > n+2
32.768Mb/s
512+(512-n)+mtime-slots
32.768Mb/s
512-(n-m)time-slots
(m-n)time-slots
TABLE3—OUTPUTHIGH-IMPEDANCECONTROL
Bits MOD1-0 Values in
ConnectionMemory
ODE pin
OSB bit in Control
Register
OutputStatus
1 and 1
Don’tCare
Don’tCare
Per-channel
high-Impedance
Any, other than 1 and 1
Any, other than 1 and 1
Any, other than 1 and 1
Any, other than 1 and 1
0
0
1
1
0
1
0
1
high-Impedance
Enable
Enable
Enable
TABLE 4—INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
A15 A14 A13 A12 A11 A10 A9
A8
STA4 STA3 STA2 STA1 STA0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
STA4 STA3 STA2 STA1 STA0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R/W
A7
A6
A5
A4
A3
A2 A1 A0 R/W
Location
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
R
Data Memory
ConnectionMemory
ControlRegister
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R/W
R
FrameAlignRegister
R/W FrameOffsetRegister0
R/W FrameOffsetRegister1
R/W FrameOffsetRegister2
R/W FrameOffsetRegister3
R/W FrameOffsetRegister4
R/W FrameOffsetRegister5
R/W FrameOffsetRegister6
R/W FrameOffsetRegister7
7
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
TABLE 5—CONTROL REGISTER (CR) BITS
ResetValue:
0000H
12
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
SRS
OEI OEPOL AOE
0
0
MBP
BPD1 BPD0
BPE
OSB
SFE
0
0
0
0
BIT
NAME
DESCRIPTION
Aone willresetthe device andhave the same effectas the RESETpin. Mustbe zerofornormaloperation.
15
SRS
(SoftwareReset)
14
OEI
When1,theTX16-31/OutputEnableIndication0-15pinswillbeOutputEnableIndication0-15andreflect theactiveorhigh-impedance
(OutputEnableIndication) stateoftheircorrespondingoutputdatastreams.When0,thisfeatureisdisabledandthesepinsareusedasoutputdatastreams
TX16-31.
13
12
OEPOL
(OutputEnablePolarity)
When1,aoneonanOutputEnableIndicationpindenotesanactivestateontheoutputdatastream;zeroonanOutputEnableIndication
pindenoteshigh-impedancestate.When0,aoneonanOutputEnableIndicationpindenoteshigh-impedanceandazerodenotes
anactivestate.
AOE
(AllOutputEnable)
When1,TX0-31willbehaveasOutputEnableIndication0-31accordingly.Theseoutputswillreflecttheactiveorhigh-impedance
stateofthecorrespondingoutputdatastreams(TX0-31)inanotherIDT72V73260ifprogrammedidentically. When0,theTSIoperates
inthenormalswitchmode.
11-10
9
Unused
MBP
Mustbezerofornormaloperation.
When1,theConnectionMemoryblockprogrammingfeatureis readyfortheprogrammingofConnectionMemoryHIGHbits,
(Memory Block Program) bit14tobit15.When0,thisfeatureisdisabled.
8-7
BPD1-0
ThesebitscarrythevaluetobeloadedintotheConnectionMemoryblockwheneverthememoryblockprogrammingfeature
(BlockProgramming
Data)
isactivated.AftertheMemoryBlockProgrambitintheControlRegisterissetto1andtheBlockProgrammingEnableissetto1,
thecontentsofthebitsBPD1-0areloadedintobit15and14oftheConnectionMemory.Bit13tobit0oftheConnectionMemory
are setto0.
6
BPE
Azerotoonetransitionofthisbitenablesthememoryblockprogrammingfunction.TheBlockProgrammingEnableandBPD1-0bits
intheControlRegisterhavetobedefinedinthesamewriteoperation.OncetheBlockProgrammingEnablebitis setHIGH,the
devicerequirestwoframestocompletetheblockprogramming.Aftertheprogrammingfunctionhasfinished,theBlockProgramming
Enable, Memory Block Program and BPD 1-0 bits will be reset to zero by the device to indicate the operation is complete.
(BeginBlock
ProgrammingEnable)
5
4
OSB
(OutputStandBy)
WhenODE=0andOutputStandBy=0, the outputdrivers ofthe transmitserialstreams are inhigh-impedance mode. When
eitherODE=1orOutputStandBy=1, theoutputserialstreams drivers functionnormally.
SFE
AzerotoonetransitioninthisbitstartstheFrameEvaluationprocedure.WhentheCompleteFrameEvaluationbitintheFrameAlignment
(StartFrameEvaluation) Registerchangesfromzerotoone,theevaluationprocedurestops.TostartanotherFrameEvaluationcycle,setthisbitto
zeroforatleastoneframe.
3-0
Unused
Mustbezerofornormaloperation.
TABLE 6—CONNECTION MEMORY BITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MOD1 MOD0 SAB4 SAB3 SAB2 SAB1 SAB0 CAB8 CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
Bit
15,14 MOD1-0
(SwitchingModeSelection)
Name
Description
MOD1 MOD0
MODE
0
0
1
1
0
1
0
1
VariableDelaymode
ConstantDelaymode
Processormode
Outputhigh-impedance
13-9 SAB4-0
(SourceStreamAddressBits)
8-0 CAB8-0
(SourceChannelAddressBits)
Thebinaryvalueisthenumberofthedatastreamforthesourceoftheconnection.
Thebinaryvalueisthenumberofthechannelforthesourceoftheconnection.
8
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
TABLE 7— FRAME ALIGNMENT REGISTER (FAR) BITS
ResetValue:
0000H.
12
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
0
0
CFE
FD12 FD11 FD10
Description
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Bit
Name
15-14 Unused
Mustbezerofornormaloperation
13
12
CFE (Complete
FrameEvaluation)
WhenCompleteFrameEvaluation=1,theFrameEvaluationiscompletedandbitsFD12toFD0bitscontainsavalidframealignmentoffset.
This bitis resettozero,whenStartFrameEvaluationbitintheControlRegisteris changedfrom1to0.
FD12
The fallingedge ofFrame Evaluation(orrisingedge forGCImode)is sampledduringthe C32i-HIGHphase (FD12=1)orduringthe
(Frame Delay Bit 12) C32i-LOWphase(FD12=0).Thisbitallowsthemeasurementresolutionto½C32icycle.ThisbitisresettozerowhentheStartFrameEvaluation
bitoftheControlRegisterchangesfrom1to0.
11-0 FD11-0
Thebinaryvalueexpressedinthesebitsreferstothemeasuredinputoffsetvalue.ThesebitsareresettozerowhentheStartFrameEvaluation
(Frame DelayBits) bit of the Control Register changes from 1 to 0. (FD11 – MSB, FD0 – LSB)
ST-BUS Frame
C32i
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16
Offset Value
FE Input
(FD[11:0] = 06
H)
(FD12 = 0, sample at CLK LOW phase)
GCI Frame
C32i
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
Offset Value
FE Input
(FD[11:0] = 09
H)
(FD12 = 1, sample at CLK HIGH phase)
5932 drw04
Figure 1. Example for Frame Alignment Measurement
9
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
TABLE 8— FRAME INPUT OFFSET REGISTER (FOR) BITS
Reset Value:0000H forallFORregisters.
Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FOR0Register
FOR1Register
OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
FOR2Register OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8
FOR3Register OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
FOR4Register OF192 OF191 OF190 DLE19 OF182 OF181 OF180 DLE18 OF172 OF171 OF170 DLE17 OD162 OD161 OF160 DLE16
FOR5Register OF232 OF231 OF230 DLE23 OF222 OF221 OF220 DLE22 OF212 OF211 OF210 DLE21 OF202 OF201 OF200 DLE20
FOR6Register OF272 OF271 OF270 DLE27 OF262 OF261 OF260 DLE26 OF252 OF251 OF250 DLE25 OF242 OF241 OF240 DLE24
FOR7Register OF312 OF311 OF310 DLE31 OF302 OF301 OF300 DLE30 OF292 OF291 OF290 DLE29 OF282 OF281 OF280 DLE28
Name(1)
Description
OFn2, OFn1, OFn0
(Offset Bits 2, 1 & 0)
Thesethreebitsdefinehowlongtheserialinterfacereceivertakestorecognizeandstorebit0fromtheRXinputpin:i.e.,tostartanewframe.
Theinputframeoffsetcanbeselectedto+7.5clockperiodsfromthepointwheretheexternalframepulseinputsignalisappliedtotheF32i
inputofthe device. See Figure 2.
DLEn
ST-BUS® and
GCI mode:
DLEn = 0, offset is on the clock boundary.
DLEn = 1, offset is a half clock cycle off of the clock boundary.
NOTE:
1. n denotes an input stream number from 0 to 31.
10
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
TABLE 9—OFFSET BITS (OFn2, OFn1, OFn0, DLEN) & FRAME DELAY BITS
(FD12,FD2-0)
MeasurementResultfrom
Frame Delay Bits
Corresponding
OffsetBits
InputStream
Offset
FD12
1
FD2
0
FD1
0
FD0
0
OFn2
0
OFn1
OFn0
0
DLEn
0
Noclockperiodshift(Default)
+0.5clockperiodshift
+1.0clockperiodshift
+1.5clockperiodshift
+2.0clockperiodshift
+2.5clockperiodshift
+3.0clockperiodshift
+3.5clockperiodshift
+4.0clockperiodshift
+4.5clockperiodshift
+5.0clockperiodshift
+5.5clockperiodshift
+6.0clockperiodshift
+6.5clockperiodshift
+7.0clockperiodshift
+7.5clockperiodshift
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
1
0
1
1
1
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
1
1
0
1
0
0
0
1
1
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
1
1
1
0
1
1
1
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
F32i (ST-BUS )
C32i (ST-BUS )
RX Stream
(32.768 Mb/s)
Bit 4
Bit 5
Bit 5
Bit 7
Bit 6
Bit 7
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
(32.768 Mb/s)
Bit 6
RX Stream
(32.768 Mb/s)
offset = 0, DLE = 1
Bit 4
Bit 7
Bit 6
Bit 5
F32i (GCI)
C32i (GCI)
RX Stream
(32.768 Mb/s)
Bit 0
Bit 1
Bit 0
Bit 2
Bit 1
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
(32.768 Mb/s)
Bit 2
RX Stream
(32.768 Mb/s)
offset = 0, DLE = 1
Bit 2
Bit 0
Bit 1
5932 drw05
Figure 2. Examples for Input Offset Delay Timing in 32.768Mb/s mode
11
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
•Test Reset (TRST)
JTAGSUPPORT
ResettheJTAGscanstructure.ThispinisinternallypulledtoVCCwhenit
is not driven from an external source.
TheIDT72V73260JTAGinterfaceconformstotheBoundary-Scanstandard
IEEE-1149.1.Thisstandardspecifiesadesign-for-testabilitytechniquecalled
Boundary-Scan test (BST). The operation of the boundary-scan circuitry is
controlledbyanexternaltestaccess port(TAP)Controller.
INSTRUCTION REGISTER
InaccordancewiththeIEEE-1149.1standard,theIDT72V73260usespublic
instructions.TheIDT72V73260JTAGinterfacecontainsafour-bitinstruction
register.InstructionsareseriallyloadedintotheinstructionregisterfromtheTDI
whentheTAPControllerisinitsshift-IRstate.Subsequently,theinstructionsare
decodedtoachievetwobasicfunctions:toselectthetestdataregisterthatmay
operatewhiletheinstructioniscurrent,andtodefinetheserialtestdataregister
path, which is used to shift data between TDI and TDO during data register
scanning.SeeTable12forInstructiondecoding.
TEST ACCESS PORT (TAP)
The Test Access Port (TAP) provides access to the test functions of the
IDT72V73260.Itconsistsofthreeinputpinsandoneoutputpin.
•Test Clock Input (TCK)
TCKprovidestheclockforthetestlogic.TheTCKdoesnotinterferewithany
on-chipclockandthusremainsindependent.TheTCKpermitsshiftingoftest
data into or out of the Boundary-Scan register cells concurrently with the
operationofthedeviceandwithoutinterferingwiththeon-chiplogic.
•TestMode SelectInput(TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controllertocontrolthetestoperations.TheTMSsignalsaresampledatthe
risingedgeoftheTCKpulse. ThispinisinternallypulledtoVCCwhenitisnot
driven from an external source.
TESTDATAREGISTER
AsspecifiedinIEEE-1149.1,theIDT72V73260JTAGInterfacecontainstwo
testdataregisters:
•The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
arrangedtoformascanpatharoundtheboundaryoftheIDT72V73260core
logic.
•Test Data Input (TDI)
•The Bypass Register
Serialinputdataappliedtothisportisfedeitherintotheinstructionregister
orintoatestdataregister,dependingonthesequencepreviouslyappliedto
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.
•TestDataOutput(TDO)
TheBypassregisterisasinglestageshiftregisterthatprovidesaone-bitpath
fromTDItoTDO. The IDT72V73260boundaryscanregisterbits are shown
inTable14.Bit0isthefirstbitclockedout.Allthree-stateenablebitsareactive
HIGH.
DependingonthesequencepreviouslyappliedtotheTMSinput,thecontents
ofeithertheinstructionregisterordataregisterareseriallyshiftedoutthrough
the TDO pin on the falling edge of each TCK pulse. When no data is shifted
throughtheboundaryscancells,theTDOdriverissettoahigh-impedancestate.
ID CODE REGISTER
AsspecifiedinIEEE-1149.1,thisinstructionloadstheIDRwiththeRevision
Number,DeviceID,JEDECID,andIDRegisterIndicatorBit. SeeTable10.
TABLE10—IDENTIFICATIONREGISTERDEFINITIONS
INSTRUCTION FIELD
RevisionNumber(31:28)
IDT Device ID (27:12)
VALUE
0x0
DESCRIPTION
Reservedforversionnumber
0x436
0x33
1
DefinesIDTpartnumber
IDT JEDEC ID (11:1)
AllowsuniqueidentificationofdevicevendorasIDT
IndicatesthepresenceofanIDregister
IDRegisterIndicatorBit(Bit0)
TABLE 11— SCAN REGISTER SIZES
REGISTERNAME
Instruction(IR)
BIT SIZE
4
1
Bypass (BYR)
Identification(IDR)
Boundary Scan (BSR)
32
Note(1)
NOTES:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on
the IDT website (www.idt.com), or by contacting your local IDT sales representative.
12
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
TABLE12—SYSTEMINTERFACEPARAMETERS
INSTRUCTION
EXTEST
CODE
0000
1111
0010
0100
0011
0001
DESCRIPTION
Forcescontentsoftheboundaryscancellsontothedeviceoutputs(1).Placestheboundaryscanregister(BSR)betweenTDIandTDO.
BYPASS
Places the bypass register(BYR)betweenTDIandTDO.
IDCODE
Loads theIDregister(IDR)withthevendorIDcodeandplaces theregisterbetweenTDIandTDO.
Places the bypass register(BYR)betweenTDIandTDO. Forces alldevice outputdrivers toa High-Zstate.
Places thebypass register(BYR)betweenTDIandTDO. Forces contents oftheboundaryscancells ontothedeviceoutputs.
Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs(2) andoutputs(1) tobe
capturedintheboundaryscancellsandshiftedseriallythroughTDO.PRELOADallowsdatatobeinputseriallyintotheboundary
scan cells via the TDI.
HIGH-Z
CLAMP
SAMPLE/PRELOAD
RESERVED
Allothercodes Severalcombinationsarereserved. Donotuseothercodesthanthoseidentifiedabove.
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS and TRST.
TABLE 13 — JTAG AC ELECTRICAL CHARACTERISTICS (1,2,3,4)
SYMBOL
tJCYC
tJCH
tJCL
PARAMETER
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock LOW
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAGReset
MIN.
100
40
MAX.
UNITS
ns
ns
40
ns
tJR
50
3(1)
3(1)
ns
tJF
ns
tJRST
tJRSR
tJCD
tJDC
ns
JTAG Reset Recovery
JTAGDataOutput
JTAGDataOutputHold
JTAGSetup
50
ns
0
25
ns
ns
tJS
15
ns
tJH
JTAG Hold
15
ns
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
tJCYC
tJR
tJF
tJCL
tJCH
TCK
Device Inputs(1)
TDI/TMS
tJH
tJS
tJDC
Device Outputs(2)
TDO
tJCD
tJRSR
5932 drw06
TRST
x
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
Figure 3. JTAG Timing Specifications
13
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
TABLE 14 — BOUNDARY SCAN REGISTER BITS
Boundary Scan Bit 0 to bit 168
Boundary Scan Bit 0 to bit 168
Device Pin
Input
Scan Cell
Output
Scan Cell
Three-State
Control
Device Pin
Input
Scan Cell
Output
Scan Cell
Three-State
Control
ODE
RESET
C32i
F32i
FE
DS
CS
R/W
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
DTA
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
0
1
2
3
4
5
6
7
TX27/OEI11
TX26/OEI10
TX25/OEI9
TX24/OEI8
TX23/OEI7
TX22/OEI6
TX21OEI5
TX20/OEI4
TX19/OEI3
TX18/OEI2
TX17/OEI1
TX16/OEI0
RX23
89
91
93
95
97
99
101
103
105
107
109
111
90
92
94
96
98
100
102
104
106
108
110
112
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RX22
RX21
RX20
RX19
RX18
RX17
RX16
RX15
RX14
RX13
RX12
RX11
RX10
RX9
RX8
TX15
TX14
TX13
TX12
TX11
TX10
TX9
TX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
RX7
24
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
70
73
74
75
76
77
78
79
80
27
30
33
36
39
42
45
48
51
54
57
60
63
66
69
72
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
D0
RX31
RX30
RX29
RX28
RX27
RX26
RX25
RX24
TX31/OEI15
TX30/OEI14
TX29/OEI13
TX28/OEI12
161
162
163
164
165
166
167
168
RX6
RX5
RX4
RX3
RX2
RX1
RX0
81
83
85
87
82
84
86
88
14
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
Device#2isusedtoswitchoutonTX32-63.LikewiseDevice#3andDevice#4
are used in the same way as Device #1 and Device #2 but switch RX 32-63
to TX0-31 and TX32-63, respectively. With this configuration all possible
combinationsofinputandoutputstreamsarepossible.Inshort,Device#1is
used to switch RX0-31 to TX0-31, Device #2 to switch RX0-31 to TX32-63,
Device #3 to switch RX 32-63 to TX0-31, and Device #4 to switch RX32-63
toTX32-63.
APPLICATIONS
CREATING LARGE SWITCH MATRICES
TocreateaswitchmatrixwithtwicethecapacityofagivenTSIdevice,four
devices mustbeused.Intheexamplebelow,fourIDT72V73260,16Kx16K
channelcapacitydevicesareusedtocreatean32Kx32Kchannelswitchmatrix.
As canbe seen, Device #1andDevice #2willreceive the same incoming
RX0-31dataandthushavethesamecontentsinDataMemory.Ontheoutput
side, however Device #1 is used to switch data out on to TX0-31 where as
RX0-31
Device 1
TX0-31
IDT72V73260
Device 2
IDT72V73260
TX32-63
RX32-63
Device 3
IDT72V73260
Device 4
IDT72V73260
5932 drw07
Figure 4. Creating Larger Switch Matrices
15
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
Using OEI
OEI=1
AOE=0
RX0-15
TX0-15
RX0-15
TX0-15
RX16-31
OEI0-15
AOE=0
OEI=0
RX0-15
TX0-15
TX16-31
RX16-31
TX16-31
AOE=0
OEI=1
RX0-15
TX0-15
RX16-31
OEI0-15
OEI16-31
RX16-31
OEI0-15
AOE=0
OEI=0
RX0-15
TX0-15
RX16-31
TX16-31
AOE=0
RX0
OEI=0
TX0
Using AOE
RX0
TX0
RX31
RX31
TX31
TX31
OEI=0
AOE=1
OEI0
RX0
RX0
OEI0
RX31
RX31
OEI 31
OEI31
5932 drw08
Figure 5. Using All Output Enable (AOE)
16
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATING
CONDITIONS(1)
Symbol Parameter
Min.
Max.
Unit
Symbol
VCC
Parameter
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
VCC
Vi
SupplyVoltage
-0.5
GND -0.3
-50
+4.0
VCC +0.3
50
V
V
Positive Supply
Input HIGH Voltage
InputLOWVoltage
VoltageonDigitalInputs
CurrentatDigitalOutputs
StorageTemperature
VIH
2.0
VCC
0.8
V
IO
mA
° C
W
VIL
-0.3
-40
V
TS
-55
+125
2
TOP
OperatingTemperature
Industrial
25
+85
°C
PD
PackagePowerDissapation
NOTE:
NOTE:
1. Voltages are with respect to Ground unless otherwise stated.
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
DCELECTRICALCHARACTERISTICS
Symbol
Parameter
Min.
Typ.
140
Max.
200
60
Units
mA
µA
µA
V
(2)
ICC
SupplyCurrent
@32.768Mb/s
(3,4)
IIL
InputLeakage(inputpins)
High-ImpedanceLeakage
OutputHIGHVoltage
OutputLOWVoltage
(3,4)
IOZ
60
(5)
VOH
2.4
(6)
VOL
0.4
V
NOTES:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Outputs unloaded.
3. 0 ≤ V ≤ VCC.
4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V).
5. IOH = 10 mA.
6. IOL = 10 mA.
17
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-TIMINGPARAMETER
MEASUREMENTVOLTAGELEVELS
Symbol
VTT
Rating
Level Unit
TTLThreshold
1.5
2.0
0.8
V
V
VHM
TTLRise/FallThresholdVoltageHIGH
TTLRise/FallThresholdVoltageLOW
InputPulseLevels
VLM
V
V
tr,tf
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1
ns
V
V
(1)
CL
50
8
pF
pF
Cin(2)
InputCapacitance
NOTES:
1. JTAG CL is 30 pF
2. For 144 TQFP
3.3v
VDD
330Ω
50Ω
Z0 = 50Ω
D.U.T.
I/O
5932 drw10
30pF*
510Ω
5932 Drw09
Figure 6. Output Load
Figure 7. Output Load
6
5
4
3
2
1
20 30 50 80 100
200
Capacitance (pF)
5932 drw11
Figure 8. Lumped Capacitive Load, Typical Derating
18
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLOCK
Symbol
Parameter
Min.
Typ.
Max.
Units
tFPW
FramePulseWidth
Bit rate = 32.768Mb/s
13
5
31
ns
ns
ns
tFPS
tFPH
tCP
FramePulseSetuptimebeforeC32ifalling
FramePulseHoldTimefromC32ifalling
10
C32iPeriod
Bit rate = 32.768Mb/s
29
13
13
30.5
15
35
20
20
ns
ns
ns
tCH
tCL
C32i Pulse Width HIGH
Bit rate = 32.768Mb/s
C32i Pulse Width LOW
Bit rate = 32.768Mb/s
15
19
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
(1)
tODE
RESET
tZR
tRZ
tRZ
tRS
TX
tODELZ
ODE
5932 drw12
NOTE:
1. To guarantee TX outputs remain in high-Impedance.
Figure 9. Reset and ODE Timing
C32i
(ST-BUS mode)
C32i
(GCI mode)
tSOD
ODE
TX
t
ODEA
tCHZ
tODEL
tODEHZ
Z
TX
TX
VALID DATA
VALID DATA
tCLZ
5932 drw14
tSIH
VALID DATA
5932 drw13
Figure 10. Serial Output and External Control
Figure 11. Output Driver Enable (ODE)
20
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MICROPROCESSORINTERFACETIMING
Symbol
tCSS
Parameter
Min.
0
Typ.
15
Max.
25
Units
ns
CS Setup from DS falling
tRWS
tADS
R/WSetupfromDSfalling
AddressSetupfromDSfalling
CS Hold after DS rising
3
ns
2
ns
tCSH
0
ns
tRWH
tADH
R/W Hold after DS Rising
Address HoldafterDSRising
Data SetupfromDTA LOWonRead
DataHoldonRead
3
ns
2
ns
tDDR
tDHR
tDSW
tSWD
tDHW
tAKD
1
ns
10
10
5
ns
DataSetuponWrite(RegisterWrite)
ValidDataDelayonWrite(ConnectionMemoryWrite)
DataHoldonWrite
0
ns
ns
ns
AcknowledgmentDelay:
Reading/WritingRegisters
Reading/WritingMemory
AcknowledgmentHoldTime
DataStrobeSetupTime
32
80
ns
ns
@32.768Mb/s
tAKH
20
ns
ns
tDSS
6
21
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
C32i GCI
C32i ST-BUS
tDSS
DS
tCSH
tCSS
CS
tRWH
tRWS
R/W
tADH
tADS
VALID ADDRESS
A0-A11
tDHR
D0-D15
READ
VALID READ DATA
tSWD
tDSW
tDHW
D0-D15
WRITE
VALID WRITE DATA
tDDR
tAKH
tAKD
DTA
5932 drw15
NOTE:
1. For quick microprocessor access tDSS must be met. In this case tAKD = tAKD (max) - C32i (period)+ tDSS.
Figure 12. Motorola Non-Multiplexed Bus Timing
22
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
23
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS — SERIAL STREAM (ST-BUS® and GCI)
Symbol
tSIS
Parameter
Min.
2
Typ.
Max.
12
9
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RXSetupTime
tSIH
RXHoldTime
4
tSOD
tCHZ
tCLZ
Clock to Valid Data
4
Clock to High-Z
3
Clock to Low-Z
9
tODE
tODEHZ
tODELZ
tOEI
Output Driver Enable to Reset HIGH
OutputDriverEnable(ODE)toHigh-Z
OutputDriverEnable(ODE)toLow-Z
OutputEnableIndicator
Active toHigh-ZonMasterReset
High-ZtoActive onMasterReset
Resetpulsewidth
5
5
12
12
12
16
8
tRZ
20
6
tZR
tRS
tODEA
OutputDriverEnabletoActive
24
IDT72V732603.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
25
ORDERINGINFORMATION
IDT
XXXXXX
XX
X
Device Type
Package
Process/
Temperature
Range
BLANK
Commercial (-40°C to +85°C)
Plastic Ball Grid Array (PBGA, BB144-1)
Thin Quad Flatpacks (TQFP, DA144-1)
BB
DA
72V73260
16,384 x 16,3843.3V Time Slot Interchange Digital Switch
5932 drw19
DATASHEETDOCUMENTHISTORY
08/15/2001
09/24/2001
12/19/2001
12/21/2001
03/25/2002
08/02/2002
05/27/2003
pgs. 2, 3, 18, 19, 21, 22, 23 and 24.
pgs. 11, 21, 23 and 24.
pgs. 1-7, 9-15, 18-25 and 27.
pgs. 1, 6, 7, 9, 13, 14, 18, 19, 20, 21 and 25.
pgs. 18 and 19.
pg. 9
pgs. 1, 3, 19 and 26.
CORPORATE HEADQUARTERS
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800-345-7015 or 408-727-6116
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for Tech Support:
408-330-1753
email:TELECOMhelp@idt.com
www.idt.com
26
相关型号：
72V73273BBBLANK
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS
IDT
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