ICS843004AGI-04LFT [ICSI]
FEMTOCLOCKS-TM CRYSTAL/LVCMOS-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER; FEMTOCLOCKS -TM CRYSTAL / LVCMOS - TO- 3.3V LVPECL频率合成器
| 型号： | ICS843004AGI-04LFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS-TM CRYSTAL/LVCMOS-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总14页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS843004I-04 is a 4 output LVPECL • Four LVPECL outputs
ICS
HiPerClockS™
Synthesizer optimized to generate clock
frequencies for a variety of high performance
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
applications and is
a member of the
HiPerClocksTM family of high performance
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
clock solutions from ICS. This device can select its input
reference clock from either a crystal input or a single-
ended clock signal. It can be configured to generate 4
outputs with individually selectable divide-by-one or
divide-by-four function via the 4 frequency select pins
(F_SEL[3:0]). The ICS843004I-04 uses ICS’ 3rd
generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter. This
ensures that it will easily meet clocking requirements
for SDH (STM-1/STM-4/STM-16) and SONET (OC-3/
OC12/OC-48). This device is suitable for multi-rate and
multiple port line card applications. The ICS843004I-04
is conveniently packaged in a small 24-pin TSSOP
package.
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.82ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.57ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.94ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PIN ASSIGNMENT
BLOCK DIAGRAM
XTAL_IN
nQ1
Q1
VCCo
Q0
1
2
3
4
5
6
7
8
24
23
22
nQ2
Q2
VCCO
Q3
OSC
0
÷1
÷4
0
1
Q0
XTAL_OUT
CLK
nQ0
21
20
19
18
17
16
15
14
13
Phase
Detector
VCO
Pulldown
nQ0
MR
F_SEL3
nc
nQ3
VEE
F_SEL2
INPUT_SEL
CLK
1
Pulldown
INPUT_SEL
M = ÷32
9
VCCA
Pulldown
Pullup
10
11
12
F_SEL0
VCC
VEE
XTAL_IN
MR
Q1
0
1
F_SEL0
F_SEL1
XTAL_OUT
nQ1
Pullup
Pullup
Pullup
ICS843004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
F_SEL1
Q2
0
1
nQ2
G Package
Top View
F_SEL2
Q3
0
1
nQ3
F_SEL3
843004AGI-04
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REV.A FEBRUARY 15, 2006
1
ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQ1, Q1
VCCO
Type
Output
Description
Differential output pair. LVPECL interface levels.
Output supply pins.
3, 22
4, 5
Power
Ouput
Q0, nQ0
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
6
MR
Input
Input
Pulldown
7,
F_SEL3,
F_SEL0,
F_SEL1,
F_SEL2
10,
12,
18
Pullup Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3.
8
nc
VCCA
VCC
Unused
Power
Power
No connect.
9
Analog supply pin.
Core supply pin.
11
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
13, 14
Input
15, 19
16
VEE
Power
Input
Negative supply pins.
CLK
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or CLK inputs as the the PLL Reference source.
Pulldown Selects XTAL inputs when LOW. Selects CLK when HIGH.
LVCMOS/LVTTL interface levels.
17
INPUT_SEL
Input
20, 21
23, 24
nQ3, Q3
Q2, nQ2
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
TABLE 3. OUTPUT CONFIGURATION AND FREQUENCY RANGE FUNCTION TABLE
Inputs
XTAL (MHz)
Output Frequency (MHz)
VCO
(MHz)
Divider Value
Application
F_SELx
Q0/nQ0:Q3/nQ3
622.08
155.52
600
0
1
0
1
0
1
0
1
19.44
19.44
622.08
622.08
600
÷1
÷4
÷1
÷4
÷1
÷4
÷1
÷4
SONET/SDH
SATA
18.75
18.75
600
150
19.53125
19.53125
20.141601
20.141601
625
625
10 Gigabit Ethernet
625
156.25
644.5312
161.13
644.5312
644.5312
10 Gigabit Ethernet
66B/64B FEC
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 70°C/W (0 mps)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA =VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
120
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
ICCA
ICCO
10
120
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
CLK,
MR, INPUT_SEL
V
CC = VIN = 3.465
150
5
µA
µA
µA
µA
IIH
Input High Current
F_SEL0:F_SEL3
VCC = VIN = 3.465
CC = 3.465V, VIN = 0V
CC = 3.465V, VIN = 0V
CLK,
MR, INPUT_SEL
V
V
-5
IIL
Input Low Current
F_SEL0:F_SEL3
-150
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC =VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
17.5
21.25
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Output Divider = ÷1
Output Divider = ÷4
Minimum Typical Maximum Units
560
140
680
170
75
MHz
MHz
ps
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2, 3
155.52MHz,
Integration Range: 12kHz - 20MHz
156.25MHz,
Integration Range: 1.875MHz - 20MHz
622.08MHz,
Integration Range: 12kHz - 20MHz
0.94
0.57
82
ps
ps
ps
RMS Phase Jitter (Random);
NOTE 4
tjit(Ø)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
175
48
675
52
ps
ꢀ
ꢀ
Output Divider = ÷4
Output Divider = ÷1
40
60
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VCCO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Output skew measurements taken with all outputs in the same divide configuration.
NOTE 4: Please refer to the Phase Noise Plot.
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCCA = 2V
nQx
Qx
SCOPE
VCC,
VCCO
Qx
nQy
Qy
LVPECL
tsk(o)
nQx
VEE
-1.3V 0.165V
3.3V CORE/3.3V OUTPUT LOAD ACTEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
Phase Noise Mask
80%
tF
80%
tR
VSWING
20%
Clock
20%
Outputs
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALLT IME
nQ0:nQ3
Q0:Q3
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSEWIDTH/PERIOD
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843004I-04 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. VCC, VCCA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
capacitor should be connected to each VCCA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843004I-04 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 19.44MHz,
18pF parallel resonant crystal and were chosen to mini-
mize the ppm error.
XTAL_OUT
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS impedance of the driver (Ro) plus the series resistance
signal through an AC couple capacitor. A general interface (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the
diagram is shown in Figure 3. The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as signal in half. This can be done in one of two ways. First,
10ns. For LVCMOS inputs, it is recommended that the R1 and R2 in parallel should equal the transmission line
impedance. For most 50Ω applications, R1 and R2 can be
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to 100Ω. This can also be accomplished by removing R1 and
reduce noise. This configuration requires that the output making R2 50Ω.
VDD
Ro
VDD
R1
R2
.1uf
Rs
Zo = 50
XTAL_IN
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
For applications not requiring the use of the crystal oscillator
LVPECL OUTPUT
input, both XTAL_IN and XTAL_OUT can be left floating. All unused LVPECL outputs can be left floating. We
Though not required, but for additional protection, a 1kΩ recommend that there is no trace attached. Both sides of the
resistor can be tied from XTAL_IN to ground.
differential output pair should either be left floating or
terminated.
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
outputs are designed to drive 50Ω transmission lines.
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUTT ERMINATION
FIGURE 4B. LVPECL OUTPUTTERMINATION
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
SCHEMATIC EXAMPLE
Figure 5 shows a schematic example for ICS843004I-04. In recommended to have one decouple capacitor per power pin.
this example, the input is a 19.44MHz parallel resonant crystal Each decoupling capacitor should be located as close as
with load capacitor CL=18pF. The 22pF frequency fine tuning possible to the power pin. The low pass filter R2, C3 and C4
capacitors are used C1 and C2.This example also shows general should also be located as close to the VCCA pin as possible.
logic control input handling. For decoupling capacitors, it is
MR
F_SEL3
VCC
VCCA
3.3V
R2
10
C3
C4
10uF
0.01u
R3
R5
133
133
VCCO
Zo = 50 Ohm
Zo = 50 Ohm
F_SEL0
VCC
Logic Control Input Examples
+
-
Set Logic
Input to
'1'
Set Logic
Input to
'0'
F_SEL1
VDD
VDD
RU1
1K
RU2
Not Install
U1
843004i-04
R4
82.5
R6
82.5
To Logic
Input
pins
To Logic
Input
pins
RD1
Not Install
RD2
1K
VCC=3.3V
VCCO=3.3V
(U1-3)
(U1-11) (U1-22)
VCC
Zo = 50 Ohm
Zo = 50 Ohm
+
-
C1
0.1uF
C2
0.1uF
C3
0.1uF
X1
19.44MHz
18pF
C2
22pF
VCCO
R5
50
R6
50
VCC
C1
22pF
Q1
R7
50
Optional
Y-Termination
Ro
~ 7 Ohm
R8
43
Zo = 50 Ohm
Driv er_LVCMOS
INPUT_SEL
F_SEL2
FIGURE 5. ICS844004I-04 SCHEMATIC EXAMPLE
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843004I-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843004I-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 415.8mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 415.8 + 120mW = 535.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming an air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.536W * 65°C/W = 119.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 24-LEADTSSOP, FORCED CONVECTION
θ
JA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT ANDT ERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V - 2V))/R ] * (V
))
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV.A FEBRUARY 15, 2006
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ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOWT ABLE FOR 24 LEAD TSSOP
θ
JA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS843004I-04 is: 2273
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12
ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843004AGI-04
www.icst.com/products/hiperclocks.html
REV.A FEBRUARY 15, 2006
13
ICS843004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS843004AGI-04
ICS843004AGI-04T
ICS843004AGI-04LF
ICS843004AGI-04LFT
ICS843004AI04
ICS843004AI04
ICS43004AI04L
ICS43004AI04L
24 Lead TSSOP
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
843004AGI-04
www.icst.com/products/hiperclocks.html
REV.A FEBRUARY 15, 2006
14
相关型号：
ICS843004AGLF
Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
IDT
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