ICS843004AGT [ICSI]
FEMTOCLOCKS⑩ LVCMOS/CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ LVCMOS / CRYSTAL - TO- 3.3V LVPECL频率合成器
| 型号： | ICS843004AGT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS⑩ LVCMOS/CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总16页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™LVCMOS/CRYSTAL- -
TO
3.3V LVPECL FREQUENCY
SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS843004 is a 4 output LVPECL synthesizer • Four 3.3V LVPECL outputs
ICS
optimized to generate Fibre Channel reference
clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
HiPerClockS™
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25, 106.25MHz, 53.125MHz
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz, and
53.125MHz.The ICS843004 uses ICS’3rd generation low phase
noise VCO technology and can achieve 1ps or lower typical
rms phase jitter, easily meeting Fibre Channel jitter requirements.
The ICS843004 is packaged in a small 24-pinTSSOP package.
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.72ps (typical)
• RMS phase noise at 212.5MHz (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -95.0 dBc/Hz
1KHz ..............-114.3 dBc/Hz
10KHz ..............-123.8 dBc/Hz
100KHz ..............-124.6 dBc/Hz
• Full 3.3V supply mode
• -30°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
PIN ASSIGNMENT
nQ1
Q1
1
24
23
22
nQ2
Q2
Inputs
Output
Frequency
(MHz)
2
Input
Frequency
M Divider N Divider
M/N
Divider Value
3
4
5
6
7
8
9
10
11
12
VCCo
Q0
VCCO
Q3
F_SEL1 F_SEL0
Value
24
Value
3
21
20
19
18
17
16
15
14
13
26.5625
26.5625
26.5625
26.5625
26.04166
23.4375
0
0
1
1
0
0
0
1
0
1
1
0
8
6
4
2
6
8
212.5
159.375
106.25
53.125
156.25
187.5
nQ0
MR
nPLL_SEL
nc
nQ3
VEE
nc
nXTAL_SEL
TEST_CLK
VEE
24
24
24
24
24
4
6
VCCA
12
4
F_SEL0
VCC
XTAL_IN
F_SEL1
XTAL_OUT
3
ICS843004
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
BLOCK DIAGRAM
F_SEL[1:0]
Pulldown
2
G Package
TopView
Pulldown
nPLL_SEL
Q0
F_SEL[1:0]
nQO
Pulldown
TEST_CLK
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
1
0
1
0
Q1
26.5625MHz
XTAL_IN
VCO
637.5MHz
(w/26.5625MHz
Reference)
nQ1
Phase
Detector
OSC
XTAL_OUT
Q2
Pulldown
nXTAL_SEL
nQ2
M = 24 (fixed)
Q3
nQ3
Pulldown
MR
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
1
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQ1, Q1
VCCO
Type
Description
Output
Power
Ouput
Differential output pair. LVPECL interface levels.
Output supply pins.
3, 22
4, 5
Q0, nQ0
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
6
MR
Input
Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When
7
nPLL_SEL
Input
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
8, 18
9
nc
Unused
Power
No connect.
VCCA
Analog supply pin.
F_SEL0,
F_SEL1
10, 12
11
Input
Power
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
VCC
Core supply pin.
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
13, 14
15, 19
16
VEE
Power
Input
Negative supply pins.
TEST_CLK
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
17
nXTAL_SEL
Input
20, 21
23, 24
nQ3, Q3
Q2, nQ2
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
51
KΩ
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
2
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
70°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
135
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
Included in IEE
15
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
2
VCC + 0.3
V
V
V
nPLL_SEL, nXTAL_SEL,
F_SEL0, F_SEL1, MR
-0.3
-0.3
0.8
Input
Low Voltage
VIL
TEST_CLK
1.3
TEST_CLK, MR,
Input
High Current
IIH
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
VCC = VIN = 3.465V
150
µA
µA
Input
Low Current
IIL
V
CC = 3.465V, VIN = 0V
-150
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
3
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
26.5625
Mode of Oscillation
Frequency
23.33
28.33
50
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
nPLL_SEL = 1
Minimum Typical Maximum Units
186.67
140
226.66
170
MHz
MHz
MHz
MHz
ns
fOUT
Output Frequency
93.33
46.67
3.0
113.33
56.66
3.8
tPD
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 4
tsk(o)
30
ps
212.5MHz, (637KHz - 10MHz)
159.375MHz, (637KHz - 10MHz)
156.25MHz, (1.875MHz - 20MHz)
106.25MHz, (637KHz - 10MHz)
53.125MHz, (637KHz - 10MHz)
20ꢀ to 80ꢀ
0.70
0.75
0.58
0.81
0.98
ps
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
49
600
51
ps
F_SEL[1:0] ≠ 00
F_SEL[1:0] = 00
ꢀ
45
55
ꢀ
NOTE 1: Measured from the differential input crossing point to the output at VCCO/2.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VCCO/2.
NOTE 3: Please refer to the Phase Noise Plot.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
4
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
TYPICAL PHASE NOISE AT 53.125MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
53.125MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.98ps (typical)
Fibre Channel Jitter Filter
-90
-100
-110
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 106.25MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
106.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.81ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
www.icst.com/products/hiperclocks.html
843004AG
REV. A NOVEMBER 18, 2004
5
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
156.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.58ps (typical)
10Gb Ethernet Jitter Filter
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 159.375MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
159.375MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.75ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
6
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
TYPICAL PHASE NOISE AT 212.5MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
212.5MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.70ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
Phase Noise Result by adding
Fibre Channel Filter to raw data
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
7
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
nQx
SCOPE
Qx
VCC
VCCA, VCCO
,
Qx
nQy
LVPECL
Qy
nQx
VEE
tsk(o)
-1.3V 0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
TEST_CLK
nQ0:nQ3
Q0:Q3
Phase Noise Mask
tPD
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
PROPAGATION DELAY
nQ0:nQ3
Q0:Q3
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
Pulse Width
Clock
Outputs
20ꢀ
tPERIOD
tR
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
8
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™LVCMOS/CRYSTAL- -
TO
3.3V LVPECL FREQUENCY
SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843004 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
capacitor should be connected to each VCCA
.
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 2A and
2B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
F
IGURE 2A. LVPECL OUTPUT
T
ERMINATION
F
IGURE 2B. LVPECL OUTPUT
T
ERMINATION
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
9
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS843004 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 3
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
ICS843004
Figure 3. CRYSTAL INPUt INTERFACE
LAYOUT GUIDELINE
resonant 26.5625MHz crystal is used. The C1=27pF and
C2=33pF are recommended for frequency accuracy.For differ-
ent board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy.
Figure 4 shows a schematic example of the ICS843004. An ex-
ample of LVEPCL termination is shown in this schematic.Addi-
tional LVPECL termination approaches are shown in the LVPECL
Termination Application Note.In this example, an 18pF parallel
3.3V
VCC
VCCA
R3
R5
133
133
R2
10
Zo = 50 Ohm
Zo = 50 Ohm
C3
10uF
C4
0.01u
+
-
VCC
VCCO
C6
0.1u
C7
0.1u
Logic Control Input Examples
R4
82.5
R6
82.5
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
RU1
1K
RU2
Not Install
To Logic
Input
pins
To Logic
Input
pins
VCC=3.3V
3.3V
VCCO=3.3V
U1
RD1
RD2
1K
R7
133
R9
Not Install
ICS843004
133
Zo = 50 Ohm
Zo = 50 Ohm
+
X1
25MHz
18pF
-
C2
33pF
C9
0.1u
R8
82.5
R10
82.5
C1
27pF
C8
0.1u
FIGURE 4. ICS843004 SCHEMATIC EXAMPLE
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
10
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843004.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843004 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.588W * 65°C/W = 123.2°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6.THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION
θ
JA by Velocity (Meters per Second)
0
1
2.5
62°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
11
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW L
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
12
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS843004 is: 2578
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
13
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™LVCMOS/CRYSTAL- -
TO
3.3V LVPECL FREQUENCY
SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
14
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS843004AG
Marking
Package
Count
60 per tube
2500
Temperature
ICS843004AG
ICS843004AG
24 Lead TSSOP
-30°C to 85°C
-30°C to 85°C
ICS843004AGT
24 Lead TSSOP on Tape and Reel
The aforementioned trademark, HiPerClockS™ and FEMTOCLOCKS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
15
ICS843004
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™LVCMOS/CRYSTAL
-TO-
3.3V LVPECL FREQUENCY
SYNTHESIZER
REVISION HISTORY SHEET
Description of Change
Rev
A
Table
Page
1
Date
Added 187.5MHz to the Frequency Selection Function Table.
Added Schematic Layout.
8/26/04
11/18/04
A
10
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
16
相关型号：
ICS843011AM-01LF
Clock Generator, 113.33MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8
IDT
©2020 ICPDF网 联系我们和版权申明