ICS843004AGLF [IDT]
Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24;
| 型号： | ICS843004AGLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 680MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总20页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
ICS843004
General Description
Features
The ICS843004 is a 4 output LVPECL synthesizer
• Four 3.3Vdifferential LVPECL output pairs
S
IC
optimized to generate Fibre Channel reference clock
frequencies and is a member of the HiPerClocksTM
family of high performance clock solutions from IDT.
Using a 26.5625MHz 18pF parallel resonant crystal,
• Selectable crystal oscillator interface
HiPerClockS™
or LVCMOS/LVTTL single-ended clock input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
the following frequencies can be generated based on the 2
frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz,
159.375MHz, 156.25, 106.25MHz, and 53.125MHz. The
ICS843004 uses IDT’s 3rd generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase jitter,
easily meeting Fibre Channel jitter requirements. The ICS843004
is packaged in a small 24-pin TSSOP package.
• VCO range: 560MHz – 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz – 10MHz): 0.72ps (typical)
Offset
Noise Power
100Hz................ -95.0 dBc/Hz
1kHz .................. -114.3 dBc/Hz
10kHz ................ -123.8 dBc/Hz
100kHz .............. -124.6 dBc/Hz
•
Full 3.3V supply mode
• -30°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Table 3A. Bank A Frequency Table
Inputs
Input Frequency (MHz)
26.5625
F_SEL1
F_SEL0
M Div. Value
N Div. Value
M/N Div. Value Output Frequency (MHz)
0
0
1
1
0
0
0
1
0
1
1
0
24
24
24
24
24
24
3
4
8
6
4
2
6
8
212.5
159.375
106.25
53.125
156.25
187.5
26.5625
26.5625
6
26.5625
12
4
26.04166
23.4375
3
Block Diagram
Pin Assignment
2
Pulldown
nQ2
F_SEL[1:0]
nQ1
Q1
1
2
24
23
Q2
Pulldown
nPLL_SEL
Q0
VCCO
Q3
VCCO
Q0
3
4
22
21
F_SEL[1:0]
0 0 ÷3
nQ0
5
6
7
20
19
18
17
nQ3
VEE
nc
nQ0
MR
nPLL_SEL
Pulldown
TEST_CLK
1
0
1
0 1 ÷4
Q1
26.5625MHz
1 0 ÷6
nc
VCO
637.5MHz
(w/26.5625MHz
Reference)
8
nXTAL_SEL
XTAL_IN
nQ1
1 1 ÷12
Phase
Detector
9
VCCA
F_SEL0
VCC
16
15
14
13
TEST_CLK
VEE
XTAL_IN
XTAL_OUT
OSC
0
10
11
12
XTAL_OUT
nXTAL_SEL
Q2
F_SEL1
Pulldown
nQ2
ICS843004
M = 24 (fixed)
Q3
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
nQ3
Pulldown
MR
G Package
Top View
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
Output
Power
Output
Differential output pair. LVPECL interface levels.
Output supply pins.
nQ1, Q1
VCCO
3, 22
4, 5
Differential output pair. LVPECL interface levels.
Q0, nQ0
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
6
7
MR
Input
Input
Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
nPLL_SEL
8, 18
9
Unused
Power
No connect.
nc
VCCA
Analog supply pin.
F_SEL0.
F_SEL1
10, 12
11
Input
Power
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
VCC
13,
14
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
15, 19
16
VEE
Power
Input
Negative supply pins.
TEST_CLK
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Selects between the single-ended TEST_CLK or crystal interface as the PLL
Pulldown reference source. When HIGH, selects TEST_CLK. When LOW, selects
XTAL. LVCMOS/LVTTL interface levels.
17
nXTAL_SEL
Input
20, 21
23, 24
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
nQ3, Q3
Q2, nQ2
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
RPULLDOWN Input Pulldown Resistor
51
kΩ
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
70°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE =0V, TA = -30°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
3.465
135
Units
V
VCC
VCCA
VCCO
IEE
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
3.135
V
3.135
3.3
mA
mA
ICCA
Included in IEE
15
Table 3B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE =0V, TA = -30°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Voltage
2
VCC + 0.3
V
nPLL_SEL, nXTAL_SEL,
MR, F_SEL[0:1]
-0.3
-0.3
0.8
1.3
V
V
Input
Low Voltage
VIL
TEST_CLK
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
Input
High Current
IIH
VCC = VIN = 3.465V
150
µA
µA
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
Input
Low Current
IIL
VCC = 3.465V, VIN = 0V
-5
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Table 3C. LVPECL DC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE =0V, TA = -30°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO – 1.4
VCCO – 2.0
0.6
Typical
Maximum
VCCO – 0.9
VCCO – 1.7
1.0
Units
µA
VOH
Output High Current; NOTE 1
VOL
Output Low Current; NOTE 1
µA
VSWING
Peak-to-Peak Output Voltage Swing
V
NOTE 1: Outputs termination with 50Ω to VCCO – 2V.
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
26.5625
23.33
28.33
50
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = VCCA = VCCO = 3.3V 5%, VEE =0V, TA = -30°C to 85°C
Parameter
Symbol
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum
186.67
140
Typical
Maximum
226.66
170
Units
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency Range
Output Skew; NOTE 1, 2
93.33
113.33
56.66
30
46.67
tsk(o)
212.5MHz,
(637kHz – 10MHz)
0.70
0.75
0.58
ps
ps
ps
159.375MHz,
(637kHz – 10MHz)
RMS Phase Jitter, (Random);
NOTE 3
tjit(Ø)
156.25MHz,
(637kHz – 10MHz)
106.25MHz, (637kHz – 10MHz)
53.125MHz, (637kHz – 10MHz)
20% to 80%
0.81
0.98
ps
ps
ps
%
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
49
600
51
F_SEL[1:0] ≠ 00
F_SEL[1:0] = 00
45
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Typical Phase Noise at 53.125MHz
0
53.125MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.98ps (typical)
-10
-20
-30
-40
-50
-60
-70
Fibre Channel Filter
-80
-90
-100
-110
-120
-130
-140
-150
Raw Phase Noise Data
-160
-170
Phase Noise Result by adding a
Fibre Channel filter to raw data
-180
-190
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Typical Phase Noise at 106.25MHz
0
106.25MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.81ps (typical)
-10
-20
-30
Fibre Channel Filter
-40
-50
-60
-70
-80
-90
-100
-110
Raw Phase Noise Data
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding a
Fibre Channel filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Typical Phase Noise at 156.25MHz
0
156.25MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.58ps (typical)
-10
-20
Fibre Channel Filter
-30
-40
-50
-60
-70
-80
-90
-100
-110
Raw Phase Noise Data
-120
-130
-140
-150
-160
Phase Noise Result by adding a
Fibre Channel filter to raw data
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Typical Phase Noise at 159.375MHz
0
159.375MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.75ps (typical)
-10
-20
-30
-40
-50
-60
-70
Fibre Channel Filter
-80
-90
-100
-110
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding a
Fibre Channel filter to raw data
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Typical Phase Noise at 212.5MHz
0
212.5MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.70ps (typical)
-10
-20
-30
-40
-50
-60
-70
Fibre Channel Filter
-80
-90
-100
-110
Raw Phase Noise Data
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding a
Fibre Channel filter to raw data
10
100
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Parameter Measurement Information
2V%
Phase Noise Plot
SCOPE
V
V
V
CC,
Qx
CCA,
CCO
Phase Noise Mask
LVPECL
nQx
Offset Frequency
f1
f2
VEE
RMS Jitter = Area Under the Masked Phase Noise Plot
-
1.3V ¬ 0.165
-
3.3V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
nQx
Qx
80%
tF
80%
tR
VSWING
20%
nQy
Clock
20%
Outputs
Qy
tsk(o)
Output Skew
Output Rise/Fall Time
nQ0:nQ3
Q0:Q3
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
Output Duty Cycle/Pulse Width/Period
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS843004 provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VCC, VCCA and VCCO should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VCC pin and also shows that VCCA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
TEST_CLK Input
For applications not requiring the use of the clock, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-downs; additional resistance is
not required but can be added for additional protection. A 1kΩ
resistor can be used.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Crystal Input Interface
The ICS843004 has been characterized with 18pF parallel
were determined using a 26.5625MHz, 18pF parallel resonant
resonant crystals. The capacitor values shown in Figure 2 below
crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
33p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
VCC
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Layout Guideline
Figure 4 shows a schematic example of the ICS843004. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18 pF
parallel resonant 26.5625MHz crystal is used. The C1= 27pF and
C2 = 33pF are recommended for frequency accuracy. For a
different board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy.
Figure 4. ICS843004 Schematic Example
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843004.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843004 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.588W * 65°C/W = 123.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 24 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCCO – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCOO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 24 Lead TSSOP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
Transistor Count
The transistor count for ICS843004 is: 2578
Package Outline and Package Dimension
Package Outline - G Suffix for 24 Lead TSSOP
Table 9. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
24
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.5
0.80
0.19
0.09
7.70
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Ordering Information
Table 9. Ordering Information
Part/Order Number
843004AG
843004AGT
843004AGLF
843004AGLFT
Marking
Package
24 Lead TSSOP
24 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
-30°C to 85°C
-30°C to 85°C
-30°C to 85°C
-30°C to 85°C
ICS843004AG
ICS843004AG
ICS843004AGL
ICS843004AGL
“Lead-Free” 24 Lead TSSOP
“Lead-Free” 24 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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Revision History Sheet
Rev
A
Table
Page
1
Description of Change
Date
Added 187.5MHz to the Frequency Selection Function Table.
Added Schematic Layout.
8/26/04
11/18/04
A
10
1
15
Features Section - added Lead-Free bullet.
Ordering Information Table - added Lead-Free part number.
A
B
3/21/05
5/5/05
T9
T5
4
3
AC Characteristics Table - deleted Propagation Delay row.
T3B
LVCMOS/LVTTL DC Characteristics Table - corrected IIL spec. from -150µA min. to
-5µA min.
C
C
11
12
14
Added Recommendations for Unused Input and Output Pins section.
Added LVCMOS to XTAL Interface section.
Corrected Figure 4, Schematic Example, Pin 18 from VCC to nc.
3/4/08
1
4
20
Frequency Select Function Table - corrected F_SEL0 column, last 2 rows.
AC Characteristics Table - Added Thermal Note.
Contact Information - Updated
T5
1/19/09
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contact IDT
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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