ICS840004AGI-01 [ICSI]
FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL -TO LVCMOS / LVTTL频率合成器
| 型号： | ICS840004AGI-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总10页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
• Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
The ICS840004I-01 is a 4 output LVCMOS/LVTTL
ICS
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
the HiPerClocksTM family of high performance
clock solutions from ICS. Using a 25MHz, 18pF
• Selectable crystal oscillator interface
or LVCMOS single-ended input
HiPerClockS™
• Supports the following output frequencies:
156.25MHz, 125MHz and 62.5MHz
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
156.25MHz, 125MHz, and 62.5MHz.The ICS840004I-01 uses
ICS’ 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS840004I-01 is
packaged in a small 20-pin TSSOP package.
• RMS phase jitter @ 156.25MHZ (1.875MHz - 20MHz):
0.52ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
Inputs
Output Frequency (MHz)
(25MHz Ref.)
M Divider N Divider
M/N
Ratio Value
F_SEL1 F_SEL0
Value
Value
0
0
1
1
0
1
0
1
25
4
6.25
156.25
125
25
25
25
5
10
5
5
2.5
5
62.5
125
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
F_SEL0
nc
2
3
4
5
6
7
8
9
2
Pullup:Pullup
F_SEL1:0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
Pulldown
nPLL_SEL
Pulldown
nXTAL_SEL
25MHz
XTAL_IN
nc
VDD
F_SEL1:0
N
0
Q0
Q1
10
OSC
1
0
0 0 ÷4
XTAL_OUT
Pulldown
ICS840004I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
0 1 ÷5
1 0 ÷10
1 1 ÷5
Phase
Detector
1
TEST_CLK
VCO
Q2
Q3
G Package
Top View
M = ÷25 (fixed)
Pulldown
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840004AGI-01
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REV. A JUNE 28, 2005
1
PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 20
Name
Type
Description
F_SEL0,
F_SEL1
Input
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
2, 9
nc
Unused
Input
No connect.
Selects between the crystal or TEST_CLK inputs as the PLL reference
Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inpus. LVCMOS/LVTTL interface levels.
3
nXTAL_SEL
4
5
TEST_CLK
OE
Input
Input
Pulldown Single-ended LVCMOS/LVTTL clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
Pullup
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the otuputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
6
7
MR
Input
Input
When HIGH, the PLL is bypassed and the output frequency =
nPLL_SEL
Pulldown
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
8
VDDA
VDD
Power
Power
Analog supply pin.
10
Core supply pin.
11,
12
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Input
Power
Output
Power
13, 19
GND
Power supply ground.
14, 15
17, 18
Q3, Q2,
Q1, Q0
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
15Ω typical output impedence.
Output supply pin.
16
VDDO
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
pF
kΩ
kΩ
Ω
VDD, VDDA, VDDO = 3.465V
Power Dissipation Capacitance VDD, VDDA = 3.465V, VDDO = 2.625V
VDD, VDDA, VDDO = 2.625V
TBD
TBD
TBD
51
CPD
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
51
ROUT
Output Impedance
15
840004AGI-01
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REV. A JUNE 28, 2005
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PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
3.3
3.3
2.5
90
Maximum Units
VDD
Core Supply Voltage
3.465
3.465
3.465
2.625
V
V
VDDA
Analog Supply Voltage
3.135
3.135
V
VDDO
Output Supply Voltage
2.375
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
8
5
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
2.5
2.5
80
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.625
2.625
2.625
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.375
2.375
V
mA
mA
mA
IDDA
IDDO
8
5
840004AGI-01
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REV. A JUNE 28, 2005
3
PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, OR
VDD = VDDA = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
VDD = 2.5V
1.7
-0.3
-0.3
VDD = 3.3V
Input Low Voltage
VDD = 2.5V
VDD = VIN = 3.465V or
2.625V
0.7
OE, F_SEL0:1
5
µA
µA
Input
High Current
IIH
V
DD = VIN = 3.465V or
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
150
2.625V
V
DD = 3.465V or 2.5V,
OE, F_SEL0:1
-150
-5
µA
µA
VIN = 0V
Input
Low Current
IIL
VDD = 3.465V or 2.5V,
IN = 0V
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
V
VDDO = 3.3V 5ꢀ
VDDO = 2.5V 5ꢀ
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 3.3V or 2.5V 5ꢀ
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pf parallel resonant crystal.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
156.25
125
MHz
MHz
MHz
ps
fOUT
Output Frequency
62.5
TBD
0.52
0.65
0.55
TBD
400
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tL
PLL Lock Time
ms
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
50
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
840004AGI-01
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REV. A JUNE 28, 2005
4
PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
156.25
125
MHz
MHz
MHz
ps
fOUT
Output Frequency
62.5
TBD
0.48
0.59
0.53
TBD
450
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tL
PLL Lock Time
ms
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
50
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
156.25
125
MHz
MHz
MHz
ps
fOUT
Output Frequency
62.5
TBD
0.50
0.60
0.51
TBD
450
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tL
PLL Lock Time
ms
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
50
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
840004AGI-01
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REV. A JUNE 28, 2005
5
PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.05V 5ꢀ 1.25V 5ꢀ
1.65V 5ꢀ
SCOPE
SCOPE
VDD
VDDA
,
VDD
VDDA, VDDO
,
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.25V 5ꢀ
-1.65V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
Phase Noise Plot
SCOPE
VDD
,
VDDA, VDDO
Phase Noise Mask
Qx
LVCMOS
GND
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.25V 5ꢀ
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
VDDO
80ꢀ
tF
80ꢀ
tR
Qx
2
20ꢀ
20ꢀ
Clock
Outputs
VDDO
2
Qy
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
VDDO
2
Q0:Q3
tPW
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840004AGI-01
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REV. A JUNE 28, 2005
6
PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS840004I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840004I-01 has been characterized with 18pF paral-
below were determined using a 25MHz 18pF parallel reso-
lel resonant crystals.The capacitor values shown in Figure 2 nant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS840004I-01
Figure 2. CRYSTAL INPUt INTERFACE
840004AGI-01
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REV. A JUNE 28, 2005
7
PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
C2=22pF are recommended for frequency accuracy. For differ-
ent board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. 1KΩ pullup or pulldown resis-
tors can be used for the logic control input pins.
Figure 3 shows a schematic example of the ICS840004I-01. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note.In this example, an 18pF
parallel resonant 25MHz crystal is used. The C1=22pF and
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
VDD=3.3V
VDDO=3.3V
RU1
1K
RU2
Not Install
R3
36
Zo = 50 Ohm
To Logic
Input
pins
To Logic
Input
pins
RD1
Not Install
RD2
1K
U1
VDDO
LVCMOS
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
F_SEL0
nc
nXTAL_SEL
TEST_CLK
OE
F_SEL1
GND
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
VDD
MR
VDD
VDD
nPLL_SEL
VDDA
nc
VDDA
VDD
R2
10
C3
10uF
10
R5
100
VDD
C4
0.01u
C6
Zo = 50 Ohm
0.1u
C5
0.1u
ICS840004i-01
R4
XTAL_OUT
100
C2
LVCMOS
22pF
X1
XTAL_IN
Optional Termination
C1
22pF
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
FIGURE 3. ICS840004I-01 SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840004I-01 is: TBD
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REV. A JUNE 28, 2005
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PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
840004AGI-01
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REV. A JUNE 28, 2005
9
PRELIMINARY
ICS840004I-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS840004AGI-01
ICS840004AGI-01T
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
ICS840004AI01
ICS840004AI01
20 Lead TSSOP
20 Lead TSSOP
2500 tape & reel
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
840004AGI-01
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REV. A JUNE 28, 2005
10
相关型号：
ICS840004AGI-01ILF
Clock Generator, 175MHz, PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
IDT
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