ICS840004AGLF1 [IDT]
PLL/Frequency Synthesis Circuit;
| 型号： | ICS840004AGLF1 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL/Frequency Synthesis Circuit |
| 文件： | 总13页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS840004 is a 4 output LVCMOS/LVTTL • Four LVCMOS/LVTTL outputs, 17Ω typical output imped-
ICS
HiPerClockS™
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
the HiPerClocksTM family of high performance
clock solutions from ICS. Using a 26.5625MHz,
ance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following input frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
18pF parallel resonant crystal, the following frequencies can
be generated based on the 2 frequency select pins
(F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz,
106.25MHz, and 53.125MHz. The ICS840004 uses ICS’ 3rd
generation low phase noise VCO technology and can achieve
1ps or lower typical random rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS840004 is packaged in
a small 20-pin TSSOP package.
• VCO range: 560MHz - 700MHz
• RMS phase jitter @ 212.5MHz (637kHz - 10MHz):
0.49ps typical, VDDO = 3.3V
Phase noise:
Offset
100Hz ............... -88.8 dBc/Hz
1kHz ............. -109.0 dBc/Hz
10kHz ............. -116.1 dBc/Hz
100kHz ............. -117.5 dBc/Hz
Noise Power
• Full 3.3V or mixed 3.3V core/2.5V output supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
FREQUENCY SELECT FUNCTION TABLE
Inputs
Output Frequency
Input Frequency
(MHz)
M Divider
Value
N Divider M/N Ratio
Range (MHz)
F_SEL1 F_SEL0
Value
Value
26.5625
26.5625
26.5625
26.5625
26.04166
0
0
1
1
0
0
1
0
1
1
24
24
24
24
24
3
8
212.5
159.375
4
6
6
4
2
6
106.25
12
4
53.125 (default)
156.25
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
Q0
F_SEL0
nc
2
3
4
5
6
7
8
9
2
Pullup:Pullup
F_SEL1:0
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
VDDA
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
Pulldown
nPLL_SEL
Pulldown
nXTAL_SEL
26.5625MHz
XTAL_IN
nc
VDD
F_SEL1:0
0
Q0
10
OSC
1
0
N
0 0 ÷3
XTAL_OUT
Pulldown
ICS840004
20-LeadTSSOP
0 1 ÷4
Q1
Phase
Detector
1
REF_CLK
VCO
1 0 ÷6
1 1 ÷12 (default)
6.5mm x 4.4mm x 0.92mm
package body
Q2
Q3
G Package
Top View
M = ÷24 (fixed)
Pulldown
MR
840004AG
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REV.A FEBRUARY 28, 2006
1
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
F_SEL0
nc
Type
Description
1
Input
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
2, 9
Unused
No connect.
Selects between the crystal or REF_CLK inputs as the PLL reference
3
nXTAL_SEL
Input
Pulldown source. When HIGH, selects REF_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
4
5
REF_CLK
OE
Input
Input
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
Pullup
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the otuputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
6
7
MR
Input
Input
When HIGH, the PLL is bypassed and the output frequency =
nPLL_SEL
Pulldown
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
8
VDDA
VDD
Power
Power
Analog supply pin.
10
Core supply pin.
11,
12
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Input
Power
Output
13, 19
GND
Power supply ground.
14, 15
17, 18
Q3, Q2,
Q1, Q0
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
17Ω typical output impedance.
16
20
VDDO
Power
Input
Output supply pin.
F_SEL1
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
kΩ
kΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
8
RPULLUP
51
51
17
21
RPULLDOWN Input Pulldown Resistor
VDDO = 3.3V 5%
VDDO = 2.5V 5%
ROUT
Output Impedance
Ω
8400042AG
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REV.A FEBRUARY 28, 2006
2
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V 5%, VDDO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
Core Supply Voltage
3.465
3.465
3.465
2.625
100
V
V
VDDA
Analog Supply Voltage
3.135
3.3
3.135
3.3
V
VDDO
Output Supply Voltage
2.375
2.5
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
12
10
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
2
VDD + 0.3
V
V
-0.3
0.8
5
OE, F_SEL0, F_SEL1,
nPLL_SEL, MR,
nXTAL_SEL, REF_CLK
V
DD = VIN = 3.465V
DD = VIN = 3.465V
µA
Input
High Current
IIH
V
150
µA
µA
µA
OE, F_SEL0, F_SEL1,
nPLL_SEL, MR,
nXTAL_SEL, REF_CLK
VDD = 3.465V, VIN = 0V
-150
-5
Input
Low Current
IIL
V
DD = 3.465V, VIN = 0V
VDDO = 3.3V 5%
VDDO = 2.5V 5%
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 3.3V or 2.5V 5%
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
26.5625
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
840004AG
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REV.A FEBRUARY 28, 2006
3
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum Typical Maximum Units
186.67
140
212.5
159.375
156.25
106.25
226.66
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.66
60
tsk(o)
Output Skew; NOTE 1, 3
212.5MHz (637kHz - 10MHz)
159.375MHz (637kHz - 10MHz)
156.25MHz (1.875MHz - 20MHz)
106.25MHz (637kHz - 10MHz)
53.125MHz (637kHz - 10MHz)
20% to 80%
0.49
0.55
0.56
0.79
0.65
ps
ps
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
41
700
59
ps
F_SEL[1:0] = 00
%
F_SEL[1:0] = 01
43
57
%
F_SEL[1:0] = 10 or 11
48
52
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum Typical Maximum Units
186.67
140
212.5
159.375
156.25
106.25
226.66
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.66
60
tsk(o)
Output Skew; NOTE 1, 3
212.5MHz (637kHz - 10MHz)
159.375MHz (637kHz - 10MHz)
156.25MHz (1.875MHz - 20MHz)
106.25MHz (637kHz - 10MHz)
53.125MHz (637kHz - 10MHz)
20% to 80%
0.46
0.54
0.57
0.73
0.63
ps
ps
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
42
700
58
ps
F_SEL[1:0] = 00
%
F_SEL[1:0] = 01
44
56
%
F_SEL[1:0] = 10 or 11
48
52
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8400042AG
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REV.A FEBRUARY 28, 2006
4
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 53.125MHZ @3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Fibre Channel Filter
53.125MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.65ps (typical)
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 106.25MHZ @3.3V
0
-10
-20
-30
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.79ps (typical)
-40
-50
-60
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Fibre Channel Filter to raw data
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840004AG
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REV.A FEBRUARY 28, 2006
5
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 159.375MHZ @3.3V
0
-10
-20
-30
-40
Fibre Channel Filter
159.375MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.55ps (typical)
-50
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Fibre Channel Filter to raw data
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 212.5MHZ@ 3.3V
0
-10
-20
-30
-40
Fibre Channel Filter
212.5MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.49ps (typical)
-50
-60
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
Phase Noise Result by adding
Fibre Channel Filter to raw data
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
8400042AG
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REV.A FEBRUARY 28, 2006
6
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2.05V 5%
VDDA
= 2.05V 5%
1.25V 5%
1.65V 5%
V
DDA = 1.65V 5%
SCOPE
SCOPE
VDD
VDD,
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VDDO
Qx
Qy
2
Phase Noise Mask
VDDO
2
Offset Frequency
tsk(o)
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT SKEW
RMS PHASE JITTER
VDDO
2
80%
tF
80%
tR
Q0:Q3
tPW
tPERIOD
20%
20%
Clock
Outputs
tPW
x 100%
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840004AG
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REV.A FEBRUARY 28, 2006
7
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS840004 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840004 has been characterized with 18pF parallel below were determined using a 26.5625MHz, 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS840004
Figure 2. CRYSTAL INPUt INTERFACE
8400042AG
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REV.A FEBRUARY 28, 2006
8
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS impedance of the driver (Ro) plus the series resistance
signal through an AC couple capacitor. A general interface (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the
diagram is shown in Figure 3. The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as signal in half. This can be done in one of two ways. First,
10ns. For LVCMOS inputs, it is recommended that the R1 and R2 in parallel should equal the transmission line
impedance. For most 50Ω applications, R1 and R2 can be
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to 100Ω. This can also be accomplished by removing R1 and
reduce noise. This configuration requires that the output making R2 50Ω.
VDD
Ro
VDD
R1
R2
.1uf
Rs
Zo = 50
XTAL_IN
Zo = Ro + Rs
XTAL_OU T
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of the crystal oscillator All unused LVCMOS output can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
840004AG
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REV.A FEBRUARY 28, 2006
9
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
The C1=22pF and C2=22pF are recommended for fre-
quency accuracy. For different board layout, the C1 and C2
may be slightly adjusted for optimizing frequency accuracy.
1kΩ pullup or pulldown resistors can be used for the logic
control input pins.
Figure 4 shows a schematic example of the ICS840004. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in
the LVCMOS Termination Application Note. In this example,
an 18pF parallel resonant 26.5625MHz crystal is used.
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
VDD=3.3V
VDDO=3.3V
RU1
1K
RU2
Not Install
R3
36
Zo = 50 Ohm
To Logic
Input
pins
To Logic
Input
pins
RD1
Not Install
RD2
1K
U1
VDDO
LVCMOS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
F_SEL1
GND
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
VDD
MR
VDD
VDD
nPLL_SEL
VDDA
nc
VDDA
C3
VDD
R2
10
R5
100
VDD
10uF
C4
0.01u
C6
Zo = 50 Ohm
0.1u
C5
0.1u
ICS840004
R4
100
XTAL_OUT
C2
22pF
LVCMOS
X1
XTAL_IN
Optional Termination
C1
22pF
If not using the crystal input, it can be left
floating. For additional protection the XTAL_IN
pin can be tied to ground.
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
FIGURE 4. ICS840004 SCHEMATIC EXAMPLE
8400042AG
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REV.A FEBRUARY 28, 2006
10
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOWT ABLE FOR 20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840004 is: 3796
840004AG
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REV.A FEBRUARY 28, 2006
11
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
8400042AG
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REV.A FEBRUARY 28, 2006
12
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS840004AG
ICS840004AGT
ICS840004AGLF
ICS840004AGLFT
ICS840004AG
ICS840004AG
ICS840004AGL
ICS840004AGL
20 Lead TSSOP
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
20 Lead TSSOP
2500 tape & reel
tube
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
840004AG
www.icst.com/products/hiperclocks.html
REV.A FEBRUARY 28, 2006
13
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ICS840008BR-01LF
Clock Generator, 160MHz, PDSO24, 3.90 X 8.65 MM, 1.50 MM HEIGHT, MO-137, SSOP-24
IDT
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