ICS840008AR01 [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS ？ CRYSTAL - TO- LVCMOS / LVTTL频率合成器
| 型号： | ICS840008AR01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总13页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
FEATURES
GENERAL DESCRIPTION
• Eight LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Output frequency range: 125MHz - 160MHz
• Crystal oscillator interface, 25MHz - 32MHz crystal
• VCO range: 500MHz - 640MHz
The ICS840008-01 is an 8 output LVCMOS/LVTTL
ICS
Synthesizer designed to generate 125MHz for
Gigabit Ethernet applications and is a member of
the HiPerClocksTM family of high performance clock
solutions from ICS.The ICS840008-01 uses ICS’
HiPerClockS™
3rd generation low phase noiseVCO technology and can achieve
1ps or lower typical random rms phase jitter, easily meeting
Gigabit Ethernet jitter requirements. The ICS840008-01 is
packaged in a small 24-pin SSOP package.
• RMS phase jitter (1.875MHz - 20MHz): 0.52ps (typical)
• Output skew: 150ps (maximum) (design target)
• Voltages supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
PIN ASSIGNMENT
BLOCK DIAGRAM
Pulldown
nPLL_SEL
VDDO
nc
XTAL_OUT
XTAL_IN
1
2
3
4
Q0
Q1
GND
Q2
24
23
22
21
5
6
7
8
Q3
VDDO
Q4
Q5
GND
Q6
VDDA
OE
MR
20
19
18
17
16
15
14
13
25MHz
OSC
1
0
÷4 (fixed)
XTAL_IN
nPLL_SEL
VDD
Phase
Detector
VCO
500MHz -
640MHz
XTAL_OUT
9
8
8
Q0:Q7
10
11
12
nc
GND
nc
Q7
VDDO
ICS840008-01
24-Lead SSOP, 150MIL
3.9mm x 8.65mm x 1.5mm
package body
÷20 (fixed)
Pulldown
MR
OE
R Package
TopView
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840008AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
1
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 13, 19
2, 10, 12
Name
VDDO
nc
Type
Power
Description
Output supply pins.
No connect.
Unused
Input
3,
4
XTAL_OUT,
XTAL_IN
Crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
5
6
VDDA
OE
Power
Input
Analog supply pin.
Pullup
Output enable. LVCMOS/LVTTL interface levels
Active HIGH Master Reset. When logic HIGH, the internal dividers are
7
8
MR
Input
Input
Pulldown reset causing the true outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and XTAL as the input to the dividers.
Pulldown When HIGH, selects XTAL. When LOW, selects PLL.
LVCMOS/LVTTL interface levels.
nPLL_SEL
9
VDD
Power
Power
Core supply pin.
11, 16, 22
GND
Power supply ground.
14, 15, 17,
18, 20, 21,
23, 24
Q7, Q6, Q5,
Q4, Q3, Q2,
Q1, Q0
Single-ended outputs.15Ω impedance.
LVCMOS/LVTTL interface levels.
Ouput
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
pF
KΩ
KΩ
Ω
VDDO = 3.63V
TBD
TBD
TBD
51
CPD
Power Dissipation Capacitance
V
DDO = 2.625V
DDO = 1.89V
V
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
51
V
DDO = 3.63V or 2.625V
VDDO = 1.89V
15
ROUT
Output Impedance
TBD
Ω
840001AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
2
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
73.1°C/W (0 mps)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 10ꢀ, VDDO = 3.3V 10ꢀ OR 2.5V 5ꢀ OR 1.8V 5ꢀ,
TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
2.97
Typical
3.3
3.3
3.3
2.5
1.8
65
Maximum Units
VDD
Core Supply Voltage
3.63
3.63
3.63
2.625
1.89
V
V
VDDA
Analog Supply Voltage
Output Supply Voltage
2.97
2.97
V
VDDO
2.375
1.71
V
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
5
4
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, VDDO = 2.5V 5ꢀ OR 1.8V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
2.5
2.5
1.8
60
Maximum Units
VDD
Core Supply Voltage
2.625
2.625
2.625
1.89
V
V
VDDA
Analog Supply Voltage
2.375
2.375
V
VDDO
Output Supply Voltage
1.71
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
5
4
840008AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
3
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
DD = 3.3V 10ꢀ
DD = 2.5V 5ꢀ
DD = 3.3V 10ꢀ
DD = 2.5V 5ꢀ
DD = 3.3V 10ꢀ
DD = 2.5V 5ꢀ
DD = 3.3V 10ꢀ
DD = 2.5V 5ꢀ
VDD = 3.3V 10ꢀ
DD = 2.5V 5ꢀ
DD = 3.3V 10ꢀ
DD = 2.5V 5ꢀ
VDDO = 3.3V 10ꢀ
Minimum Typical Maximum Units
V
2
VDD + 0.3
V
V
OE, MR,
PLL_SEL
VIH
VIL
Input High Voltage
V
1.7
-0.3
-0.3
VDD + 0.3
V
1.3
0.7
150
150
5
V
OE, MR,
PLL_SEL
Input Low Voltage
Input High Current
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
V
MR,
nPLL_SEL
V
IIH
V
OE
V
5
-5
-5
MR,
nPLL_SEL
V
IIL
Input Low Current
V
-150
-150
2.6
1.8
1.5
OE
V
VOH
Output High Voltage; NOTE 1
V
V
DDO = 2.5V 5ꢀ
DDO = 1.8V 5ꢀ
V
V
VOL
Output Low Voltage: NOTE 1
VDDO = 3.3V 10ꢀ or 2.5V 5ꢀ
DDO = 1.8V 5ꢀ
0.5
0.4
V
V
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
MHz
MHz
Ω
25
32
50
7
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
840001AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
4
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 10ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
160
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
TBD
0.52
Integration Range:
1.875MHz - 20MHz
tjit(Ø)
ps
tL
PLL Lock Time
TBD
550
50
ms
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 10ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
160
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
TBD
0.53
Integration Range:
1.875MHz - 20MHz
tjit(Ø)
ps
tL
PLL Lock Time
TBD
600
50
ms
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = 3.3V 10ꢀ, VDDO = 1.8V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
160
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
TBD
0.49
Integration Range:
1.875MHz - 20MHz
tjit(Ø)
ps
tL
PLL Lock Time
TBD
630
50
ms
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840008AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
5
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
TABLE 5D. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
160
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
TBD
0.53
Integration Range:
1.875MHz - 20MHz
tjit(Ø)
ps
tL
PLL Lock Time
TBD
600
50
ms
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5E. AC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, VDDO = 1.8V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
160
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
TBD
0.49
Integration Range:
1.875MHz - 20MHz
tjit(Ø)
ps
tL
PLL Lock Time
TBD
630
50
ms
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840001AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
6
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 125MHZ (3.3V)
0
-10
-20
-30
Gigabit Ethernet Filter
-40
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.52ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Raw Phase Noise Data
Phase Noise Result by adding
Gigabit Ethernet Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840008AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
7
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V 10ꢀ
2.05V 13ꢀ 1.25V 5ꢀ
SCOPE
SCOPE
VDD
VDDA
VDDO
,
VDD
VDDA
,
,
,
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 10ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
2.4V 12ꢀ
0.9V 5ꢀ
SCOPE
SCOPE
VDD
VDDA
VDDO
,
VDD
VDDA
,
,
,
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.25V 5ꢀ
-0.9V 5ꢀ
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V 5ꢀ
0.9V 5ꢀ
Phase Noise Plot
SCOPE
VDD
VDDA
,
,
Phase Noise Mask
VDDO
Qx
LVCMOS
GND
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-0.9V 5ꢀ
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
840001AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
8
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
VDDO
80ꢀ
tF
80ꢀ
tR
Qx
Qy
2
20ꢀ
20ꢀ
VDDO
2
Clock
Outputs
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
VDDO
2
Q0:Q7
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840008AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
9
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS840008-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840008-01 has been characterized with 18pF paral- below were determined using a 25MHz 18pF parallel reso-
lel resonant crystals.The capacitor values shown in Figure 2 nant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS840008-01
Figure 2. CRYSTAL INPUt INTERFACE
840001AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
10
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
73.1°C/W
65.9°C/W
60.5°C/W
TRANSISTOR COUNT
The transistor count for ICS840008-01 is: 3378
840008AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
11
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - R SUFFIX FOR 24 LEAD SSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
1.35
0.10
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
A1
A2
b
0.20
0.18
8.55
5.80
3.80
c
D
E
E1
e
0.635 BASIC
0.84 REF
L
0.40
0°
1.27
8°
α
ZD
Reference Document: JEDEC Publication 95, MO-137
840001AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
12
PRELIMINARY
ICS840008-01
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS840008AR-01
ICS840008AR-01T
Marking
Package
Shipping Packaging
tube
Temperature
0°C to 70°C
0°C to 70°C
ICS840008AR01
ICS840008AR01
24 Lead SSOP
24 Lead SSOP
2500 tape & reel
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
840008AR-01
www.icst.com/products/hiperclocks.html
REV. A APRIL 7, 2005
13
相关型号：
ICS840008BR-01LF
Clock Generator, 160MHz, PDSO24, 3.90 X 8.65 MM, 1.50 MM HEIGHT, MO-137, SSOP-24
IDT
ICS840008BR-01T
Clock Generator, 160MHz, PDSO24, 3.90 X 8.65 MM, 1.50 MM HEIGHT, MO-137, SSOP-24
IDT
ICS840014AGILF
Clock Generator, 106.25MHz, PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS840014AGILFT
Clock Generator, 106.25MHz, PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
©2020 ICPDF网 联系我们和版权申明