ICS840011 [ICSI]
FEMTOCLOCKS CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR; FEMTOCLOCKS CRYSTAL - TOLVCMOS / LVTTL时钟发生器
| 型号： | ICS840011 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR |
| 文件： | 总11页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS840011 is a Fibre Channel Clock • 1 LVCMOS/LVTTL output, 7Ω output impedence
ICS
Generator and a member of the HiPerClocksTM
• Crystal oscillator interface designed for a 26.5625MHz or
family of high performance devices from ICS.
25MHz, 18pF parallel resonant crystal
HiPerClockS™
The ICS840011 uses a 26.5625MHz or 25MHz
crystal to synthesize 106.25MHz or 100MHz
• Output frequency: 106.25MHz (typical)
• VCO range: 560MHz to 680MHz
respectively. The ICS840011 has excellent phase jitter
performance, from 637KHz – 10MHz integration range. The
ICS840011 is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
• RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.780ps (typical)
• RMS phase noise at 106.25MHz (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -95.7 dBc/Hz
1KHz ................ -121 dBc/Hz
10KHz ................ -129 dBc/Hz
100KHz ..............-129.6 dBc/Hz
• 3.3V operating supply
• -30°C to 85°C ambient operating temperature
FREQUENCY TABLE
Inputs
Output Frequency
(MHz)
Crystal Frequency (MHz)
26.5625
25
106.25
100
BLOCK DIAGRAM
PIN ASSIGNMENT
(Pullup)
OE
VDDA
OE
VDD
Q0
1
2
3
4
8
7
6
5
VCO
XTAL_IN
XTAL_OUT
XTAL_IN
GND
nc
Phase
Detector
Q0
OSC
÷6
637.5MHz w/
26.5625MHz Ref.
XTAL_OUT
ICS840011
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
M = ÷24 (fixed)
TopView
840011AG
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REV. A OCTOBER 15, 2004
1
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDDA
Power
Input
Analog supply pin.
Output enable pin. When HIGH, Q0 output is enabled.
2
OE
Pullup
When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
3,
4
XTAL_OUT,
XTAL_IN
Input
5
6
nc
Unused
Power
No connect.
GND
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
7Ω output impedance.
Core supply pin.
7
8
Q0
Output
Power
VDD
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
4
24
51
7
pF
pF
KΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
VDD, VDDA = 3.465V
RPULLUP
ROUT
Output Impedance
5
12
TABLE 3. CONTROL FUNCTION TABLE
Control Inputs
Output
Q0
OE
0
Hi-Z
1
Active
840011AG
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REV. A OCTOBER 15, 2004
2
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
101.7°C/W (0 mps)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.465
3.465
80
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
mA
mA
IDDA
10
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
V
V
Input Low Voltage
-0.3
0.8
5
Input High Current OE
Input Low Current OE
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDD = VIN = 3.465V
µA
µA
V
IIL
VDD = 3.465V, VIN = 0V
-150
2.6
VOH
VOL
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
26.5625
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -30°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
93.33
106.25
113.33
MHz
RMS Phase Jitter (Random);
NOTE 1
fOUT = 106.25MHz,
(637KHz to 10MHz)
tjit(Ø)
0.780
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
250
48
600
52
ps
ꢀ
fOUT = 106.25MHz
All parameters are characterized @ 106.25MHz.
NOTE 1: Please refer to the Phase Noise Plot.
840011AG
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REV. A OCTOBER 15, 2004
3
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
TYPICAL PHASE NOISE AT 106.25MHZ
0
-10
-20
Fibre Channel Filter
106.25MHz
-30
-40
RMS Phase Jitter (Random)
637K to 10MHz = 0.780ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
Raw Phase Noise Data
-170
-180
-190
Phase Noise Result by adding
Fibre Channel Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840011AG
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REV. A OCTOBER 15, 2004
4
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
Phase Noise Plot
SCOPE
VDD
Phase Noise Mask
Qx
LVCMOS
GND
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.65V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
VDD
80ꢀ
tF
80ꢀ
tR
2
Q0
Pulse Width
tPERIOD
20ꢀ
20ꢀ
Clock
Outputs
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
840011AG
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REV. A OCTOBER 15, 2004
5
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
LVCMOS/LVTTL CLOCK
GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS840011 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL.VDD, andVDDA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10µF and a .01µF
bypass capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840011 has been characterized with 18pF parallel parallel resonant crystal and were chosen to minimize the
resonant crystals. The capacitor values, C1 and C2, shown in ppm error. The optimum C1 and C2 values can be slightly
Figure 2 below were determined using a 26.5625MHz, 18pF adjusted for different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
840011AG
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REV. A OCTOBER 15, 2004
6
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS840011. An 106.25MHz output frequency. The C1 = 27pF and C2 = 33pF
example of LVCMOS termination is shown in this schematic. are recommended for frequency accuracy. For different board
layout, the C1 and C2 values may be slightly adjusted for opti-
Additional LVCMOS termination approaches are shown in the
LVCMOSTermination Application Note.In this example, an 18pF mizing frequency accuracy.
parallel resonant 26.5625MHz crystal is used for generating
VDD
VDDA
C3
R2
10
10uF
C4
0.1u
U1
R3
43
VDD
Q
1
8
7
6
5
Zo = 50 Ohm
VDDA
OE
XTAL_OUT
XTAL_I N
VDD
Q0
GND
NC
OE
2
3
4
C2
33pF
X1
C5
0.1u
LVCMOS
ICS840011
C1
27pF
VDD=3.3V
FIGURE 3A. ICS840011 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of P.C. board layout. The crystal
X1 footprint in this example allows either surface mount (HC49S)
or through hole (HC49) package. C3 is 0805. C1 and C2 are
0402. Other resistors and capacitors are 0603.This layout as-
sumes that the board has clean analog power and ground planes.
FIGURE 3B. ICS840011 PC BOARD LAYOUT EXAMPLE
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840011AG
REV. A OCTOBER 15, 2004
7
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters Per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS840011 is: 1521
840011AG
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REV. A OCTOBER 15, 2004
8
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
9
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
CLOCKS™ CRYSTAL- -
TO
LVCMOS/LVTTL CLOCK
GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS840011AG
Marking
Package
Count
Temperature
-30°C to 85°C
-30°C to 85°C
-30°C to 85°C
011A
011A
8 lead TSSOP
100 per tube
2500
ICS840011AGT
ICS840011AGLN
8 lead TSSOP on Tape and Reel
8 lead "Lead Free Annealed" TSSOP
011AN
100 per tube
8 lead "Lead Free Annealed" TSSOP
on Tape and Reel
ICS840011AGLNT
011AN
2500
-30°C to 85°C
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
840011AG
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REV. A OCTOBER 15, 2004
10
ICS840011
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-TO-
LVCMOS/LVTTL CLOCK
GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
T9
Page
Date
A
10
Ordering Information Table - corrected count from 154 per tube to 100.
10/15/04
840011AG
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REV. A OCTOBER 15, 2004
11
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