ICS840004AGL [ICSI]
FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL -TO LVCMOS / LVTTL频率合成器
| 型号： | ICS840004AGL |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总13页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
CLOCKS™ CRYSTAL- -
TO
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS840004 is a 4 output LVCMOS/LVTTL • Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
ICS
Synthesizer optimized to generate Ethernet
• Selectable crystal oscillator interface
HiPerClockS™
reference clock frequencies and is a member of
or LVCMOS single-ended input
the HiPerClocksTM family of high performance
• Supports the following input frequencies:
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and
53.125MHz
clock solutions from ICS. Using a 26.5625MHz,
18pF parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and
53.125MHz.The ICS840004 uses ICS’3rd generation low phase
noise VCO technology and can achieve 1ps or lower typical
random rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS840004 is packaged in a small 20-pin
TSSOP package.
• RMS phase jitter @ 212.5MHz (637KHz - 10MHz):
0.98ps typical
• RMS phase noise at 212.5MHz, VDDO = 3.3V
Phase noise:
Offset
Noise Power
100Hz ............... -88.8 dBc/Hz
1KHz ..............-109.0 dBc/Hz
10KHz ..............-116.1 dBc/Hz
100KHz ..............-117.5 dBc/Hz
• Full 3.3V or 3.3V core/2.5V output supply mode
• 0°C to 70°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
Inputs
Output
Frequency
Range
Input
Frequency
M Divider N Divider
M/N
Ratio Value
F_SEL1 F_SEL0
Value
Value
26.5625
26.5625
26.5625
26.5625
26.04166
0
0
1
1
0
0
1
0
1
1
24
3
8
6
4
2
6
212.5
159.375
106.25
53.125
156.25
24
24
24
24
4
6
12
4
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
20
19
18
17
16
15
14
13
12
11
F_SEL0
nc
F_SEL1
GND
Q0
2
3
4
5
6
7
8
9
2
Pulldown:Pulldown
F_SEL1:0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
Pulldown
nPLL_SEL
Pulldown
nXTAL_SEL
26.5625MHz
XTAL_IN
nc
VDD
F_SEL1:0
0
Q0
Q1
10
OSC
1
0
N
0 0 ÷3
XTAL_OUT
Pulldown
ICS840004
20-LeadTSSOP
6.5mm x 4.4mm x 0.92mm
package body
0 1 ÷4
Phase
Detector
1
TEST_CLK
VCO
1 0 ÷6 (default)
1 1 ÷12
Q2
Q3
G Package
Top View
M = ÷24 (fixed)
Pulldown
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840004AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
1
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
F_SEL0
nc
Type
Description
1
Input
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
No connect.
2, 9
Unused
Selects between the crystal or TEST_CLK inputs as the PLL reference
Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inpus. LVCMOS/LVTTL interface levels.
3
nXTAL_SEL
Input
4
5
TEST_CLK
OE
Input
Input
Pulldown Single-ended LVCMOS/LVTTL clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
Pullup
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the otuputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
6
7
MR
Input
Input
When HIGH, the PLL is bypassed and the output frequency =
nPLL_SEL
Pulldown
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
8
VDDA
VDD
Power
Power
Analog supply pin.
10
Core supply pin.
11,
12
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Input
Power
Output
13, 19
GND
Power supply ground.
14, 15
17, 18
Q3, Q2,
Q1, Q0
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
15Ω typical output impedence.
16
20
VDDO
Power
Input
Output supply pin.
F_SEL1
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
KΩ
KΩ
Ω
VDD, VDDA, VDDO = 3.465V
TBD
TBD
51
CPD
Power Dissipation Capacitance
Input Pullup Resistor
V
DD, VDDA = 3.465V, VDDO = 2.625V
RPULLUP
RPULLDOWN Input Pulldown Resistor
51
ROUT
Output Impedance
15
8400042AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
2
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
3.3
3.3
2.5
87
Maximum Units
VDD
Core Supply Voltage
3.465
3.465
3.465
2.625
V
V
VDDA
Analog Supply Voltage
3.135
3.135
V
VDDO
Output Supply Voltage
2.375
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
8
5
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_SEL1:0, nPLL_SEL,
nXTAL_SEL, OE, MR
TEST_CLK
F_SEL1:0, nPLL_SEL,
nXTAL_SEL, OE, MR
TEST_CLK
OE
F_SEL0:1, nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
OE
F_SEL0:1, nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
2
VDD + 0.3
V
V
V
Input
VIH
High Voltage
2
V
DD + 0.3
0.8
-0.3
-0.3
Input
VIL
Low Voltage
1.3
5
V
VDD = VIN = 3.465V
µA
Input
IIH
High Current
V
DD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
DDO = 3.3V 5ꢀ
VDDO = 2.5V 5ꢀ
VDDO = 3.3V or 2.5V 5ꢀ
150
µA
µA
µA
-150
-5
Input
IIL
Low Current
V
V
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
840004AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
3
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
26.5625
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
NOTE: Characterized using an 18pf parallel resonant crystal.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
212.5
159.375
156.25
106.25
53.125
TBD
MHz
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 3
212.5MHz (637KHz - 10MHz)
159.375MHz (637KHz - 10MHz)
156.25MHz (1.875MHz - 20MHz)
106.25MHz (637KHz - 10MHz)
53.125MHz (637KHz - 10MHz)
0.98
ps
0.84
ps
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
TBD
ps
0.83
ps
1.0
ps
tL
PLL Lock Time
1
ms
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
500
50
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
212.5
159.375
156.25
106.25
53.125
TBD
MHz
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 3
212.5MHz (637KHz - 10MHz)
159.375MHz (637KHz - 10MHz)
156.25MHz (1.875MHz - 20MHz)
106.25MHz (637KHz - 10MHz)
53.125MHz (637KHz - 10MHz)
0.93
ps
0.76
ps
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
TBD
ps
0.81
ps
0.99
ps
tL
PLL Lock Time
1
ms
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
500
50
ꢀ
For notes see above, Table 4A.
8400042AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
4
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
TYPICAL PHASE NOISE AT 53.125MHZ @3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Fibre Channel Filter
53.125MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 1.00ps (typical)
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 53.125MHZ @2.5V
0
-10
-20
Fibre Channel Filter
-30
-40
53.125MHz
RMS Phase Jitter (Random)
-50
637KHz to 10MHz = 0.99ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840004AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
5
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
TYPICAL PHASE NOISE AT 106.25MHZ @3.3V
0
-10
-20
-30
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.83ps (typical)
-40
-50
-60
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 106.25MHZ @ 2.5V
0
-10
-20
-30
-40
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.81ps (typical)
-50
-60
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Fibre Channel Filter to raw data
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
8400042AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
6
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
CLOCKS™ CRYSTAL- -
TO
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
TYPICAL PHASE NOISE AT 159.375MHZ @3.3V
0
-10
-20
-30
-40
Fibre Channel Filter
159.375MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.84ps (typical)
-50
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Fibre Channel Filter to raw data
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 159.375MHZ@ 2.5V
0
-10
-20
-30
-40
-50
Fibre Channel Filter
159.375MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.76ps (typical)
-60
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Fibre Channel Filter to raw data
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840004AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
7
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
TYPICAL PHASE NOISE AT 212.5MHZ@ 3.3V
0
-10
-20
Fibre Channel Filter
-30
212.5MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.98ps (typical)
-40
-50
-60
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
Phase Noise Result by adding
Fibre Channel Filter to raw data
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 212.5MHZ@ 2.5V
0
-10
-20
-30
-40
-50
Fibre Channel Filter
212.5MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.93ps (typical)
-60
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
8400042AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
8
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
- -
TO
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.05V 5ꢀ 1.25V 5ꢀ
1.65V 5ꢀ
SCOPE
SCOPE
VDD
VDDA
,
VDD
VDDA, VDDO
,
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.25V 5ꢀ
-1.65V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VDDO
Qx
Qy
2
Phase Noise Mask
VDDO
2
Offset Frequency
tsk(o)
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT SKEW
RMS PHASE JITTER
VDDO
2
80ꢀ
tF
80ꢀ
tR
Q0:Q3
Pulse Width
tPERIOD
20ꢀ
20ꢀ
Clock
Outputs
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840004AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
9
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
CLOCKS™ CRYSTAL- -
TO
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS840004 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840004 has been characterized with 18pF parallel reso- determined using a 26.5625MHz 18pF parallel resonant crystal and
nant crystals.The capacitor values shown in Figure 2 below were were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS840004
Figure 2. CRYSTAL INPUt INTERFACE
8400042AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
10
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
LAYOUT GUIDELINE
and C2=22pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy. 1KΩ pullup or pulldown re-
sistors can be used for the logic control input pins.
Figure 3 shows a schematic example of the ICS840004. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 26.5625MHz crystal is used.The C1=22pF
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
3.3V
3.3V
R3
RU1
1K
RU2
Not Install
36
Zo = 50 Ohm
To Logic
Input
pins
To Logic
Input
pins
U1
LVCMOS
RD1
RD2
1K
1
2
3
20
19
18
17
16
15
14
13
12
11
F_SEL0
nc
nXTAL_SEL
TEST_CLK
OE
F_SEL1
GND
Q0
Q1
VDDO
Q2
Not Install
4
5
6
3.3V
R4
36
Zo = 50 Ohm
MR
7
8
9
10
nPLL_SEL
VDDA
nc
Q3
GND
XTAL_IN
XTAL_OUT
3.3V
VDDA
C3
3.3V
R2
10
VDD
10uF
C4
C5
0.1u
0.01u
C6
0.1u
LVCMOS
ICS840004
XTAL_OU T
C2
22pF
X1
XTAL_I N
C1
22pF
FIGURE 3. ICS840004 SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840004 is: TBD
840004AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
11
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
8400042AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
12
PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
C
LOCKS™ CRYSTAL
-
TO
-
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS840004AG
Marking
Package
Count
72 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
ICS840004AG
ICS840004AG
20 Lead TSSOP
ICS840004AGT
20 Lead TSSOP on Tape and Reel
The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
840004AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
13
相关型号：
ICS840008AR-01LF
Clock Generator, 160MHz, PDSO24, 3.90 X 8.65 MM, 1.50 MM HEIGHT, MO-137, SSOP-24
IDT
©2020 ICPDF网 联系我们和版权申明