ICS840004AGI-01T [IDT]
FEMTOCLOCKS⑩ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL - TOLVCMOS / LVTTL频率合成器
| 型号： | ICS840004AGI-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FEMTOCLOCKS⑩ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总16页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS840004I-01
FEMTOCLOCKS™ C RYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
• Four LVCMOS/LVTTL outputs,
The ICS840004I-01 is a 4 output LVCMOS/LVTTL
ICS
17Ω typical output impedance
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
the HiPerClocksTM family of high performance
clock solutions from IDT. Using a 25MHz, 18pF
HiPerClockS™
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following output frequencies: 156.25MHz,
125MHz and 62.5MHz
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
156.25MHz, 125MHz, and 62.5MHz.The ICS840004I-01 uses
IDT’s 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS840004I-01 is
packaged in a small 20-pin TSSOP package.
• VCO range: 560MHz - 700MHz
• RMS phase jitter @ 156.25MHZ (1.875MHz - 20MHz):
0.52ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free RoHS
(6) packages
FREQUENCY SELECT FUNCTION TABLE
Inputs
M Divider N Divider
Value
Output Frequency (MHz)
(25MHz Ref.)
M/N
Ratio Value
F_SEL1 F_SEL0
Value
0
0
1
1
0
1
0
1
25
4
6.25
156.25
125
25
25
25
5
10
5
5
2.5
5
62.5
125 (default)
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
Q0
F_SEL0
nc
2
3
4
5
6
7
8
9
2
Pullup:Pullup
F_SEL1:0
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
VDDA
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
Pulldown
nPLL_SEL
Pulldown
nXTAL_SEL
25MHz
XTAL_IN
nc
VDD
F_SEL1:0
N
0
Q0
Q1
10
OSC
1
0 0 ÷4
XTAL_OUT
Pulldown
ICS840004I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
0 1 ÷5
Phase
Detector
1
REF_CLK
VCO
0
1 0 ÷10
1 1 ÷5 (default)
Q2
Q3
G Package
Top View
M = ÷25 (fixed)
Pulldown
MR
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TABLE 1. PIN DESCRIPTIONS
Number
1, 20
Name
F_SEL0,
F_SEL1
Type
Description
Input
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
2, 9
nc
Unused
Input
No connect.
Selects between the crystal or REF_CLK inputs as the PLL reference
Pulldown source. When HIGH, selects REF_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
3
nXTAL_SEL
4
5
REF_CLK
OE
Input
Input
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
Pullup
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the otuputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
6
7
MR
Input
Input
When HIGH, the PLL is bypassed and the output frequency =
nPLL_SEL
Pulldown
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
8
VDDA
VDD
Power
Power
Analog supply pin.
10
Core supply pin.
11,
12
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Input
Power
Output
Power
13, 19
GND
Power supply ground.
14, 15
17, 18
Q3, Q2,
Q1, Q0
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
17Ω typical output impedance.
Output supply pin.
16
VDDO
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
kΩ
kΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
8
RPULLUP
51
51
17
21
RPULLDOWN Input Pulldown Resistor
VDDO = 3.3V 5%
VDDO = 2.5V 5%
ROUT
Output Impedance
Ω
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ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V 5%, VDDO = 3.3V 5% OR 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
Core Supply Voltage
3.465
3.465
3.465
2.625
100
V
V
VDDA
Analog Supply Voltage
3.135
3.3
3.135
3.3
V
VDDO
Output Supply Voltage
2.375
2.5
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
12
10
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.625
2.625
2.625
95
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.375
2.5
2.375
2.5
V
mA
mA
mA
IDDA
IDDO
12
8
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TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5% OR 2.5V 5%, OR
VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
VDD = 2.5V
1.7
-0.3
-0.3
VDD = 3.3V
VDD = 2.5V
DD = VIN = 3.465V or
2.625V
0.7
V
OE, F_SEL0:1
5
µA
µA
Input
High Current
IIH
VDD = VIN = 3.465V or
nPLL_SEL, MR,
nXTAL_SEL, REF_CLK
150
2.625V
V
DD = 3.465V or 2.5V,
OE, F_SEL0:1
-150
-5
µA
µA
VIN = 0V
Input
Low Current
IIL
VDD = 3.465V or 2.5V,
VIN = 0V
nPLL_SEL, MR,
nXTAL_SEL, REF_CLK
V
DDO = 3.3V 5%
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 2.5V 5%
VDDO = 3.3V or 2.5V 5%
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum Typical Maximum Units
140
112
56
156.25
125
175
140
70
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
62.5
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
60
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
0.52
0.65
0.55
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
43
700
57
ps
F_SEL[1:0] = 00 or 01
%
F_SEL[1:0] = 10 or 11
49
51
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
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TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum Typical Maximum Units
140
112
56
156.25
125
175
140
70
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
62.5
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
60
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
0.48
0.59
0.53
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
43
700
57
ps
F_SEL[1:0] = 00 or 01
%
F_SEL[1:0] = 10 or 11
49
51
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum Typical Maximum Units
140
112
56
156.25
125
175
140
70
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
62.5
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
60
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
0.50
0.60
0.51
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
44
700
56
ps
F_SEL[1:0] = 00 or 01
%
F_SEL[1:0] = 10 or 11
49
51
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
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TYPICAL PHASE NOISE AT 62.5MHZ @3.3V
0
-10
-20
-30
1Gb Ethernet Filter
-40
-50
-60
-70
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.55ps
-80
-90
-100
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 62.5MHZ @2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1Gb Ethernet Filter
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.51ps
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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TYPICAL PHASE NOISE AT 125MHZ @3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
10Gb Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.65ps (typical)
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ @2.5V
0
-10
-20
10Gb Ethernet Filter
-30
-40
125MHz
RMS Phase Jitter (Random)
-50
1.875MHz to 20MHz = 0.60ps (typical)
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Raw Phase Noise Data
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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TYPICAL PHASE NOISE AT 156.25MHZ @3.3V
0
-10
-20
10Gb Ethernet Filter
-30
-40
-50
-60
-70
-80
-90
-100
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.52ps (typical)
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ @2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
10Gb Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.50ps (typical)
Raw Phase Noise Data
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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PARAMETER MEASUREMENT INFORMATION
2.05V 5%
VDDA = 2.05V 5%
1.65V 5%
VDDA
= 1.65V 5%
1.25V 5%
SCOPE
SCOPE
VDD,
VDDO
VDD
VDDO
GND
Qx
Qx
LVCMOS
LVCMOS
GND
-1.65V 5%
-1.25V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5%
Phase Noise Plot
V
DDA = 1.25V 5%
SCOPE
VDD,
VDDO
Qx
Phase Noise Mask
LVCMOS
GND
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.25V 5%
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
VDDO
80%
tF
80%
tR
Qx
2
20%
20%
Clock
Outputs
VDDO
2
Qy
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
VDDO
2
Q0:Q3
tPW
tPERIOD
tPW
x 100%
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS840004I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840004I-01 has been characterized with 18pF paral- below were determined using a 25MHz, 18pF parallel reso-
lel resonant crystals.The capacitor values shown in Figure 2 nant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS840004I-01
FIGURE 2. CRYSTAL INPUt INTERFACE
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LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS impedance of the driver (Ro) plus the series resistance
signal through an AC couple capacitor. A general interface (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the
diagram is shown in Figure 3. The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as signal in half. This can be done in one of two ways. First,
10ns. For LVCMOS inputs, it is recommended that the R1 and R2 in parallel should equal the transmission line
impedance. For most 50Ω applications, R1 and R2 can be
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to 100Ω. This can also be accomplished by removing R1 and
reduce noise. This configuration requires that the output making R2 50Ω.
VDD
Ro
VDD
R1
R2
.1uf
Rs
Zo = 50
XTAL_IN
Zo = Ro + Rs
XTAL_OU T
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
OUTPUTS:
LVCMOS OUTPUTS
For applications not requiring the use of the crystal oscillator All unused LVCMOS output can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
REF_CLK INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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LAYOUT GUIDELINE
The C1=22pF and C2=22pF are recommended for fre-
quency accuracy. For different board layout, the C1 and C2
may be slightly adjusted for optimizing frequency accuracy.
1kΩ pullup or pulldown resistors can be used for the logic
control input pins.
Figure 4 shows a schematic example of the ICS840004I-
01. An example of LVCMOS termination is shown in this
schematic. Additional LVCMOS termination approaches are
shown in the LVCMOS Termination Application Note. In this
example, an 18pF parallel resonant 25MHz crystal is used.
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
VDD=3.3V
VDDO=3.3V
RU1
1K
RU2
Not Install
R3
36
Zo = 50 Ohm
To Logic
Input
pins
To Logic
Input
pins
RD1
Not Install
RD2
1K
U1
VDDO
LVCMOS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
F_SEL1
GND
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
VDD
MR
VDD
VDD
nPLL_SEL
VDDA
nc
VDDA
C3
VDD
R2
10
R5
100
VDD
10uF
C4
0.01u
C6
Zo = 50 Ohm
0.1u
C5
0.1u
840004i_01
R4
100
XTAL_OUT
C2
22pF
LVCMOS
X1
XTAL_IN
Optional Termination
C1
22pF
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
FIGURE 4. ICS840004I-01 SCHEMATIC EXAMPLE
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RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOWT ABLE FOR 20 LEAD TSSOP
θ
JA by Velocity (Linear Feet per Minute)
0
200
98.0°C/W
500
88.0°C/W
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840004I-01 is: 3796
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PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS840004AGI-01
ICS840004AGI-01T
ICS840004AGI-01lLF
ICS840004AGI-01LFT
ICS40004AI01
ICS40004AI01
ICS0004AI01L
ICS0004AI01L
20 Lead TSSOP
20 Lead TSSOP
2500 tape & reel
tube
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix tot he part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT.IDT reserves the right to change any circuitry or specifications without notice.IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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FEMTOCLOCKS™ CRYSTAL-TO-
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REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
Ordering Informatin Table - corrected standard marking and added Lead Free
marking.
A
T8
15
10/22/07
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REV.A OCTOBER 22, 2007
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