ICM7363QG [ICMIC]

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS; QUAD 12月10日/ 8-位电压输出DAC


型号：	ICM7363QG
厂家：	IC MICROSYSTEMS
描述：	QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS QUAD 12月10日/ 8-位电压输出DAC 转换器光电二极管输出元件
文件：	总10页 (文件大小：132K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

respectively, with guaranteed monotonic behavior. They

include a 1.25V reference for ease of use and flexibility.

The reference output is available on a separate pin and

can be used to drive the reference input of each DAC.

Alternately, each DAC can be driven by an external

reference. There is a wide operating supply range of 2.7V

to 5.5V.

FEATURES

•

12/10/8-Bit Monotonic Quad DACs in 16 lead

QSOP Package

•

Wide Output Voltage Swing

150 µA per DAC at 5V Supply

100 µA per DAC at 3V Supply

On Board Reference

Three-wire SPI Interface

Serial Data Out for Daisy-Chaining

8µs Full-Scale Settling Time

The input interface is an easy to use three-wire SPI/QSPI

compatible interface. Each DAC can be individually

controlled and has a double buffered digital input. There is

a serial data output to allow for daisy-chaining

applications.

APPLICATIONS

Battery-Powered Applications

Industrial Process Control

Digital Gain and Offset Adjustment

OVERVIEW

The ICM7363, ICM7343 and ICM7323 are Quad 12-Bit,

10-Bit and 8-Bit wide output voltage swing DACs

BLOCK DIAGRAM

V_DD

REF_CREF_B

REF_D

REF_A

REFOUT

ICM 7363/7343/7323

Reference

Input and

DAC Latch

12/10/8 -Bit

DAC A

V_{OUT A}

Input and

DAC Latch

12/10/8 -Bit

DAC B

V_{OUT B}

Input and

DAC Latch

12/10/8 -Bit

DAC C

V_{OUT C}

Input and

DAC Latch

12/10/8 -Bit

DAC D

V_{OUT D}

Input Control Logic, Registers and Latches

SDI

SDO

Power-On-

Reset

SCK

CLR

GND

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

PACKAGE

16-Pin QSOP

V_DD

V_OUTA

REF_A

GND

V_OUTD

REF_D

V_OUTC

REF_C

V_OUTB

REF_B

REFOUT

CLR

SDO

SCK

SDI

PIN DESCRIPTION

Pin No Symbol

Description

V_DD

Supply Voltage

DAC A Output

V_{OUT A}

REF _A

V_{OUT B}

REF _B

REFOUT

CLR

DAC A Reference Input

DAC B Output

DAC B Reference Input

Reference Output (1.25V)

Clear Input (TTL or CMOS)

Serial Data Input (TTL or CMOS)

Serial Clock Input (TTL or CMOS)

Serial Data Output

SDI

SCK

SDO

Chip Select (TTL or CMOS)

DAC C Reference Input

DAC C Output

REF _C

V_{OUT C}

REF _D

V_{OUT D}

GND

DAC D Reference Input

DAC D Output

Ground

ABSOLUTE MAXIMUM RATING

Symbol

Parameter

Value

-0.3 to 7.0

Unit

V_DD

Supply Voltage

I_IN

+/- 25.0

Input Current

V_{IN_}

V_{IN_REF}

T_STG

-0.3 to 7.0

-65 to +150

Digital Input Voltage (SCK, SDI, CS, CLR)

Reference Input Voltage

Storage Temperature

^oC

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

T_SOL

300

^oC

Soldering Temperature

Note: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

ORDERING INFORMATION

Part

Temperature Range

Package

16-Pin QSOP

ICM7363

ICM7343

ICM7323

-40 ^oC to 85 ^oC

DC ELECTRICAL CHARACTERISTICS

(V_{DD =}2.7V to 5.5V, V_{REF IN =}1.25V ; V_OUTunloaded; all specifications T_MINtoT_MAXunless otherwise noted)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

DC PERFORMANCE

ICM7363

DNL

INL

Resolution

Differential Nonlinearity

Integral Nonlinearity

Bits

LSB

(Notes 1 & 3)

0.4

4.0

+1.0

+12.0

ICM7343

Resolution

Bits

LSB

DNL

INL

Differential Nonlinearity

Integral Nonlinearity

(Notes 1 & 3)

0.1

1.0

+1.0

+3.0

ICM7323

Resolution

Bits

LSB

DNL

INL

Differential Nonlinearity

Integral Nonlinearity

(Notes 1 & 3)

0.05

0.25

+1.0

+0.75

Gain Error

Offset Error

+0.5

+25

% of FS

POWER REQUIREMENTS

V_DD

I_DD

Supply Voltage

Supply Current

2.7

5.5

2.5

(Note 4)

1.2

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

OUTPUT CHARACTERISTICS

Output Voltage Range

(Note 3)

V_DD

VO_SC

R_OUT

Short Circuit Current

Amp Output Impedance

1.0

100

150

5.0

200

Ω

At Mid-scale

At Zero-scale

Ω

Output Line Regulation

Vdd=2.7 to 5.5 V

0.4

3.0

mV/V

LOGIC INPUTS

V_IH

V_IL

Digital Input High

Digital Input Low

Digital Input Leakage

(Note 2)

2.4

0.8

µΑ

REFERENCE

R_IN

Reference Input Resistance

Reference Input Range

Reference Output

Reference Output Line

Regulation

kΩ

mV/V

(Note 2)

0.5

1.2

V_DD-1.5

1.3

4.0

V_REFOUT

1.25

0.8

Vdd=2.7 to 5.5 V

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

AC ELECTRICAL CHARACTERISTICS

(V_{DD =}2.7V to 5.5V, V_{REF IN =}1.25V ; V_OUTunloaded; all specifications T_MINtoT_MAXunless otherwise noted)

Symbol Parameter Test Conditions Min Typ Max

Unit

V/µs

Slew Rate

Settling Time

Full-scale settling

µs

Mid-scale Transition Glitch

Energy

nV-S

Note 1: Linearity is defined from code 64 to 4095 (ICM7363)

Linearity is defined from code 16 to 1023 (ICM7343)

Linearity is defined from code 4 to 255 (ICM7323)

Note 2: Guaranteed by design; not tested in production

Note 3: See Applications Information

Note 4: All digital inputs are either at GND or Vdd

TIMING CHARACTERISTICS

(V_{DD =}2.7V to 5.5V; all specifications T_MINtoT_MAXunless otherwise noted)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

SCK Cycle Time

Data Setup Time

Data Hold Time

(Note 2)

SCK Falling edge to CS

Rising Edge

(Note 2)

CS Falling Edge to SCK

Rising Edge

(Note 2)

CS Pulse Width

CLR Pulse Width

SDO Delay

100

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

SCK

SDI

LSB

Input Word for DAC N

SDO

Input Word for DAC N

Figure 1: Serial Interface Timing Diagram

CONTENTS OF INPUT SHIFT REGISTER

ICM7363 (12-Bit DAC)

MSB

LSB

D1 D0

D11

D10

Figure 2: Contents of ICM7363 Input Shift Register

ICM7343 (10-Bit DAC)

MSB

LSB

Figure 3: Contents of ICM7343 Input Shift Register

ICM7323 (8-Bit DAC)

MSB

LSB

Figure 4: Contents of ICM7323 Input Shift Register

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

DATA

DAC

FUNCTION

Data

A-D

Load Input Latch

Update DAC

Load Input Latch and Update DAC

Load Input Latch

Update DAC

Load Input Latch and Update DAC

Load Input Latch

Update DAC

Load Input Latch and Update DAC

Load Input Latch

Update DAC

Load Input Latch and Update DAC

Load Input Latch

Update DAC

Load Input Latch and Update DAC

No Operation

Table 1: Serial Interface Control Command

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

be low before the CS pin is pulled back low. As the CS pin

is pulled high the shift register contents are transferred to

a bank of 16 latches. The 4 bit control word (C3~C0) is

then decoded and the appropriate DAC is updated or

loaded depending on the control word (see Table 1).

DETAILED DESCRIPTION

The ICM7363 is a 12-bit quad voltage output DAC. The

ICM7343 is the 10-bit version of this family and the

ICM7323 is the 8-bit version.

This family of DACs employs a resistor string architecture

a 1.25V

Each DAC has a double-buffered input with an input latch

and a DAC latch. The DAC output will swing to its new

value when data is loaded into the DAC latch. For each

DAC, the user has three options: loading only the input

latch, updating the DAC with data previously loaded into

the input latch or loading the input latch and updating the

DAC at the same time with a new code. The user also has

the ability to perform this operation simultaneously for all

DACs as shown in Table 1.

guaranteeing monotonic behavior. There is

onboard reference and a wide operating supply range of

2.7V to 5.5V.

Reference Input and Output

Each DAC has its own reference input pin which can be

driven from ground to V_DD-1.5V. The input resistance on

each of these pins is typically 41 kΩ. There is a gain of two

in the output amplifiers which means they swing from

ground at code 0 to 2 x V_{REF IN}at full-scale :

Vout = 2 x (V_{REF IN}xD)/2ⁿ

Power-On Reset

There is a power-on reset on board that will clear the

contents of all the latches to all 0s on power-up and the

DAC voltage outputs will go to ground. The CLR pin will

also perform this same operation asynchronously when it

is pulled low.

Where D=digital input (decimal) and n= number of bits, i.e.

12 for ICM7363, 10 for ICM7343 and 8 for ICM7323.

There is also an onboard band-gap reference on all these

parts. This reference output is nominally 1.25V and is

brought out to a separate pin, REFOUT and can be used

to drive the reference input of the DACs. The outputs will

nominally swing from 0 to 2.5V when using this reference.

Output Amplifier

Each DAC has its own output amplifier with a wide output

voltage swing. The actual swing of the output amplifier will

be limited by offset error and gain error. See the

Applications Information Section for

discussion.

a more detailed

The amplifiers are configured in a gain of 2 with internal

gain resistors of about 50 kΩ. The output swing will be

from 0V to 2 x V_{REF IN}at full-scale.

The output amplifier can drive a load of 2.0 kΩ to V_DDor

GND in parallel with a 500 pF load capacitance.

The output amplifier has a full-scale typical settling time of

8 µs and it dissipates about 150 µA with a 5V supply

voltage.

Serial Interface and Input Logic

This quad DAC family uses a standard 3-wire connection

compatible with SPI/QSPI interfaces. There is also a serial

data output pin that allows daisy-chaining. Data is loaded

in 16-bit words which consist of 4 address and control bits

(MSBs) followed by 12 bits of data (see table 1). The

ICM7343 has the last two LSBs as don’t cares and the

ICM7323 has the last 4 LSBs as don’t cares. Each DAC is

double buffered with an input latch and a DAC latch.

All the digital inputs are CMOS/TTL compatible. The

current dissipation of the device however, will be higher

when the inputs are driven at TTL levels.

The output of the 16-bit input shift register is available at

the SDO pin. Data is clocked in on the rising edge of SCK

which has a Schmitt trigger internally to allow for noise

immunity on the SCK pin. This specially eases the use for

opto-coupled interfaces.

The CS pin must be low when data is being clocked into

the part. After the 16^thclock pulse the CS pin must be

pulled high (level-triggered) for the data to be transferred

to an input bank of latches. The CS pin also disables the

SCK pin internally when pulled high and the SCK pin must

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

ground. This is why the linearity is specified for a starting

code greater than zero.

APPLICATIONS INFORMATION

Power Supply Bypassing and Layout Considerations

As in any precision circuit, careful consideration has to be

given to layout of the supply and ground. The return path

from the GND to the supply ground should be short with

low impedance. Using a ground plane would be ideal. The

supply should have some bypassing on it. A 10 µF

tantalum capacitor in parallel with a 0.1 µF ceramic with a

low ESR can be used. Ideally these would be placed as

close as possible to the device. Avoid crossing digital and

analog signals, specially the reference, or running them

close to each other.

Figure 6 illustrates how a gain error or positive offset error

will affect the output when it is close to V_DD. A positive gain

error or positive offset will cause the output to be limited to

the positive supply voltage resulting in a deadband of

codes close to full-scale. This can be avoided by using a

reference voltage slightly less then 0.5 x V_DDensuring that

the full-scale of the DAC is always less than V_DD

Output Swing Limitations

The ideal rail-to-rail DAC would swing from GND to V_DD

however, offset and gain error limit this ability. Figure 5

illustrates how a negative offset error will affect the output.

The output will limit close to ground since this is single

supply part, resulting in a deadband area. As a larger input

is loaded into the DAC the output will eventually rise above

DEADBAND

NEGATIVE

OFFSET

Figure 5: Effect of Negative Offset

OFFSET AND

GAIN ERROR

V_DD

DEADBAND

POSITIVE

OFFSET

Figure 6: Effect of Gain Error and Positive Offset

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

PACKAGE INFORMATION

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363/7343/7323

mic

QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS

IC MICROSYSTEMS

ORDERING INFORMATION

ICM73X3 P G

G = RoHS Compliant Lead-Free package.

Blank = Standard package. Non lead-free.

Device

6 - ICM7363

4 - ICM7343

2 - ICM7323

Package

Q = 16-Lead QSOP

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

ICM7363QG [ICMIC]

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