ICM7521M [ICMIC]
12/10/8-Bit Low Power Single DAC With Serial Interface and Voltage Output; 12月10日/ 8-位低功耗，单DAC，具有串行接口和电压输出
| 型号： | ICM7521M |
| 厂家： | 
IC MICROSYSTEMS |
| 描述： | 12/10/8-Bit Low Power Single DAC With Serial Interface and Voltage Output |
| 文件： | 总9页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICM7561/7541/7521
12/10/8-Bit Low Power Single DAC
With Serial Interface and Voltage Output
IC MICROSYSTEMS
FEATURES
OVERVIEW
The ICM7561, ICM7541 and ICM7521 are 12-Bit, 10-Bit
and 8-Bit Voltage Output, Low Power, Single DACs
respectively, with guaranteed monotonic behavior. These
DACs are available in 8 Lead MSOP package. They have
•
12/10/8-Bit Single DAC in 08 Lead MSOP
Package
•
•
•
•
Ultra-Low Power Consumption
Guaranteed Monotonic
Wide Voltage Output Swing Buffer
Three-wire SPI/QSP and Microwire Interface
Compatible
three
Software-Selectable
Power-Down
Output
Impedances (1 K Ohm, 100 K Ohm and Hi-Z) as additional
safety feature for applications that drive transducers or
valves. The operating supply range is 2.7V to 5.5V.
•
•
Three Software-Selectable Power-Down Output
Impedances (1 K Ohm, 100 K Ohm and Hi-Z)
Schmitt-Triggered Inputs for Direct Interfacing to
Opto-couplers
The input interface is an easy to use three-wire SPI, QSPI
and Microwire compatible interface. The DAC has Schmitt-
Triggered Inputs for Direct Interfacing to Opto-couplers
easily.
APPLICATION
•
•
•
Battery-Powered Applications
Industrial Process Control
Digital Gain and Offset Adjustment
BLOCK DIAGRAM
REFIN
ICM7561/7541/7521
x 2
VO
INPUT
REGISTER
DAC
REGISTER
DAC
RESISTOR
NETWORK
INPUT CONTROL LOGIC, REGISTERS AND LATCHES
POWER DOWN CONTROL
SDI
SCK
CS
Rev. A6
ICmic reserves the right to change specifications without prior notice
1
ICM7561/7541/7521
PACKAGE
08 Lead MSOP
VO
NC
1
2
3
4
8
7
6
5
VDD
GND
REFIN
SDI
CS
SCK
TOP VIEW
PIN DESCRIPTION (8 Lead MSOP)
Pin
Name
I/O
Description
1
2
3
4
5
6
7
8
VO
NC
O
-
I
DAC Output Voltage
No Connection
CS
Active Low Chip Select (CMOS)
Serial Clock Input (CMOS)
Serial Data Input (CMOS)
Reference Voltage Input
Ground
SCK
SDI
I
I
REFIN
GND
VDD
I
I
I
Supply Voltage
Rev. A6
ICmic reserves the right to change specifications without prior notice
2
ICM7561/7541/7521
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VDD
Supply Voltage
Input Current
-0.3 to 7.0
+/- 25.0
V
mA
V
IIN
VIN_
-0.3 to 7.0
-0.3 to 7.0
-65 to +150
300
,
Digital Input Voltage (SCK, SDI , CLR CS )
VIN_REF
TSTG
TSOL
Reference Input Voltage
V
Storage Temperature
oC
oC
Soldering Temperature
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ORDERING INFORMATION
Part
Operating Temperature Range
Package
ICM7561
ICM7541
ICM7521
-40 oC to 85 oC
-40 oC to 85 oC
-40 oC to 85 oC
08-Lead MSOP
08-Lead MSOP
08-Lead MSOP
DC ELECTRICAL CHARACTERISTICS
(VDD =2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DC PERFORMANCE
ICM7561
N
Resolution
12
Bits
LSB
LSB
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
(Notes 1 & 3)
(Notes 1 & 3)
0.4
4.0
+1.0
+12.0
ICM7541
N
Resolution
10
8
Bits
LSB
LSB
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
(Notes 1 & 3)
(Notes 1 & 3)
0.1
1.0
+1.0
+3.0
ICM7521
N
Resolution
Bits
LSB
LSB
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
(Notes 1 & 3)
(Notes 1 & 3)
0.05
0.25
+1.0
+0.75
STATIC ACCURACY
GE
OE
Gain Error
Offset Error
+0.5
+25
% of FS
mV
POWER REQUIREMENTS
VDD
IDD
Supply Voltage
Supply Current
2.7
5
5.5
150
100
V
Full Scale at VDD=5.5
Full Scale at VDD=3.6
90
75
µA
µA
Rev. A6
ICmic reserves the right to change specifications without prior notice
3
ICM7561/7541/7521
DC ELECTRICAL CHARACTERISTICS (continued)
(VDD =2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Vout
VOSC
Rout
Output Voltage Range
Short Circuit Current
Output Impedance
(Note 3)
0
VDD
150
1.1
V
60
1
mA
Power-Down at 1 K Ohm
Power-Down at 100 K Ohm
VDD=2.7V to 5.5V
0.9
90
KΩ
KΩ
mV/V
100
0.4
110
3.0
Output Line Regulation
-3.0
LOGIC INPUTS
VIH
VIL
Digital Input High
(Note 2)
(Note 2)
2.4
V
V
Digital Input Low
0.8
5
Digital Input Leakage
AC ELECTRICAL CHARACTERISTICS
(VDD =2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
SR
Slew Rate
2
8
V/µs
Settling Time
µs
Mid-scale Transition Glitch
Energy
nV-S
40
Note 1:
Linearity is defined from code 110 to 3990 (ICM7561)
Linearity is defined from code 16 to 1023 (ICM7541)
Linearity is defined from code 4 to 255 (ICM7521)
Guaranteed by design; not tested in production
See Applications Information
Note 2:
Note 3:
TIMING CHARACTERISTICS
(VDD =2.7V to 5.5V, all specifications TMIN to TMAX unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
t1
t2
t3
t4
t5
t6
SCK Cycle Time
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
30
10
10
0
ns
ns
ns
ns
ns
ns
Data Setup Time
Data Hold Time
SCK Falling edge to CS Rising
CS Falling Edge to SCK Rising Edge
15
20
Pulse Width
CS
Rev. A6
ICmic reserves the right to change specifications without prior notice
4
ICM7561/7541/7521
SERIAL INTERFACE TIMING AND OPERATION DIAGRAM
t5
t1
t4
t6
CS
SCK
SDI
C3
C2
C1
D0
t2
t3
MSB
LSB
Figure 1. Serial Interface Timing Diagram
(ENABLE
SCK)
(UPDATE
OUTPUT)
CS
SCK
SDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Figure 2. Serial Interface Operation Diagram
CONTENTS OF INPUT SHIFT REGISTER
DEVICE
BIT
CONTROL WORD
MSB
DATA WORD
LSB
ICM7561
ICM7541
ICM7521
12
10
8
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0
C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
X
X
A1 A0
Figure 3. Contents of Input Shift Register
Rev. A6
ICmic reserves the right to change specifications without prior notice
5
ICM7561/7541/7521
DATA
C3 C2 C1 C0
FUNCTION
(D11~D0:7561;D9~D0:7541;D7~D0:7521)
0
0
0
0
Data
Input loaded into DAC, VO updated
Table 1. Serial Interface Input Word
CONTROL
C3 C2 C1 C0
DATA
FUNCTION
D11~D2 D1 D0 (7561)
D9~D0 A1 A0 (7541)
D7~D0 A1 A0 (7521)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
0
0
1
1
0
1
0
1
DAC O/P, wakeup
Floating Output
Output is terminated with 1KΩ
Output is terminated with100 KΩ
Table 2. Power Down Mode Control
DETAILED DESCRIPTION
The output amplifier has a full-scale typical settling time of
8 µs and it dissipates about 100 µA with a 3V supply
voltage.
The ICM7561 is a 12-bit voltage output DAC. The ICM7541
is the 10-bit version of this family and the ICM7521 is the
8-bit version. These devices have a 16-bit input shift
register and the DAC has a double buffered digital input.
Serial Interface and Input Logic
This DAC family uses a standard 3-wire connection
compatible with SPI/QSPI and Microwire interfaces. Data is
always loaded in 16-bit words which consist of 4 control
bits (MSBs) followed by 12 bits (see Figure 3). The
ICM7561 uses the last two LSBs of the DAC data also for
power down control. The ICM7541 and ICM7521 have the
last 2 LSBs as power down control bits only and the data
which gets loaded into the DAC register starts at location
D0 (see tables 1 and 2).
This family of DACs has a guaranteed monotonic behavior.
The operating supply range is from 2.7V to 5.5V.
Reference Input
The reference input accepts positive DC and AC signals.
The voltage at REFIN sets the full-scale output voltage of
the DAC. The reference input voltage range is from 0 to
VDD-1.5V. The impedance at this pin is very high (greater
than 10 M Ohm). The DAC output amplifier is configured in
a gain of 2 configuration. This means that the full-scale
output of the DAC will be 2x VREF. To determine the output
voltage for any code, use the following equation.
Serial Data Input
SDI (Serial Data Input) pin is the data input pin for the DAC.
Data is clocked in on the falling edge of SCK which has a
schmitt trigger internally to allow for noise immunity on the
SCK pin. This specially eases the use for opto-coupled
interfaces.
VOUT = 2 x (VREF x (D / (2n)))
Where D is the numeric value of DAC’s decimal input code,
VREF is the reference voltage and n is number of bits, i.e.
12 for ICM7561, 10 for ICM7541 and 8 for ICM7521.
The Chip Select pin which is the 3rd pin of 8 Lead MSOP
package is active low. This pin frames the input data for
synchronous loading and must be low when data is being
clocked into the part. There is an onboard counter on the
clock input and after the 16th clock pulse the data is
automatically transferred to a 16-bit input latch and the 4
bit control word (C3~C0) is then decoded and the
appropriate command is performed depending on the
control word (see Table 1, 2). Chip Select pin must be
pulled high (level-triggered) and back low for the next data
word to be loaded in. This pin also disables the SCK pin
internally when pulled high.
Output Buffer Amplifier
The DAC has an output amplifier connected in a gain of 2
configuration. This amplifier has a wide output voltage
swing. The actual swing of the output amplifier will be
limited by offset error and gain error. See the Applications
Information Section for a more detailed discussion.
The output amplifier can drive a load of 2.0 K Ω to VDD or
GND in parallel with a 500 pF load capacitance.
Rev. A6
ICmic reserves the right to change specifications without prior notice
6
ICM7561/7541/7521
Power-Down Mode
The DACs have three Software-Selectable Power-Down
Output Impedances (1 K Ohm, 100 K Ohm and Hi-Z) as
additional safety feature for applications that drive
transducers or valves. The power down (or wake up
command) can be done by loading the control word with
1111 (C3 to C0). In power down mode, the selection of the
output impedance of the DAC is controlled by the last two
bits (D0 and D1 for the ICM7561, or A0 and A1 for the
ICM7541/7521). See Table 1 and Table 2 for details of
operation of this function.
DEADBAND
Power-On Reset
NEGATIVE
OFFSET
There is a power-on reset on board that will clear the
contents of all the latches to all 0s on power-up and the
DAC voltage output will go to ground.
APPLICATIONS INFORMATION
Power Supply Bypassing and Layout Considerations
As in any precision circuit, careful consideration has to be
given to layout of the supply and ground. The return path
from the GND to the supply ground should be short with
low impedance. Using a ground plane would be ideal. The
supply should have some bypassing on it. A 10 µF
tantalum capacitor in parallel with a 0.1 µF ceramic with a
low ESR can be used. Ideally these would be placed as
close as possible to the device. Avoid crossing digital and
analog signals, specially the reference, or running them
close to each other.
Figure 4. Effect of Negative Offset
Output Swing Limitations
OFFSET AND
GAIN ERROR
The ideal rail-to-rail DAC would swing from GND to VDD.
However, offset and gain error limit this ability. Figure 4
illustrates how a negative offset error will affect the output.
The output will limit close to ground since this is single
supply part, resulting in a dead-band area. As a larger
input is loaded into the DAC the output will eventually rise
above ground. This is why the linearity is specified for a
starting code greater than zero.
VDD
DEADBAND
POSITIVE
OFFSET
Figure 5 illustrates how a gain error or positive offset error
will affect the output when it is close to VDD. A positive gain
error or positive offset will cause the output to be limited to
the positive supply voltage resulting in a dead-band of
codes close to full-scale.
Figure 5. Effect of Gain Error and Positive Offset
Rev. A6
ICmic reserves the right to change specifications without prior notice
7
ICM7561/7541/7521
PACKAGE INFORMATION
8 Lead MSOP
Rev. A6
ICmic reserves the right to change specifications without prior notice
8
ICM7561/7541/7521
PACKAGE INFORMATION
ICM75X1 P G
G = RoHS Compliant Lead-Free package.
Blank = Standard package. Non lead-free.
Device
6 - ICM7561
4 - ICM7541
2 - ICM7521
Package
M = 8-Lead MSOP
Rev. A6
ICmic reserves the right to change specifications without prior notice
9
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