ICM7377BQG [ICMIC]
Quad 12/10/8-Bit Voltage Output DACs with Serial Interface and Adjustable Output Gain; 四路12月10日/ 8-位电压输出DAC，串行接口和可调输出增益
| 型号： | ICM7377BQG |
| 厂家： | 
IC MICROSYSTEMS |
| 描述： | Quad 12/10/8-Bit Voltage Output DACs with Serial Interface and Adjustable Output Gain |
| 文件： | 总11页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
FEATURES
OVERVIEW
•
12/10/8-Bit Monotonic Quad DAC in 20 Lead
QSOP Package
Adjustable Output Gain
Wide Output Voltage Swing
150 µA per DAC at 5V Supply
100 µA per DAC at 3V Supply
On Board Reference
Serial Interface with three-wire SPI/QSPI and
Microwire Interface Compatible
Serial Data Out for Daisy-Chaining
8 µS Full scale Settling Time
The ICM7377B, ICM7357B and ICM7337B are Quad 12-
Bit, 10-Bit and 8-Bit wide output voltage swing DACs
respectively, with guaranteed monotonic behavior. These
DACs are available in 20 Lead QSOP package. They
include adjustable output gain for ease of use and
flexibility. The reference output is available on a separate
pin and can be used to drive external loads. The operating
supply range is 2.7V to 5.5V.
•
•
•
•
•
•
•
•
The input interface is an easy to use three-wire SPI/QSPI
and Microwire compatible interface. The DAC has a
double buffered digital input. And there is a serial data
output port to allow daisy-chaining applications.
APPLICATION
•
•
•
Battery-Powered Applications
Industrial Process Control
Digital Gain and Offset Adjustment
BLOCK DIAGRAM
REFCD
REFAB
ICM7377B/7357B/7337B
DAC A
INPUT AND DAC LATCH
INPUT AND DAC LATCH
INPUT AND DAC LATCH
INPUT AND DAC LATCH
+
-
VOA
FBA
DAC B
DAC C
DAC D
+
-
VOB
FBB
+
-
VOC
FBC
+
-
VOD
FBD
REFERENCE
INPUT CONTROL LOGIC, REGISTERS AND LATCHES
REFOUT
SDO
SDI
SCK
CS
CLR
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
1
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
PACKAGE
20 Lead QSOP
VDD
FBA
1
2
20
19
18
17
16
15
14
13
12
11
AGND
FBD
VOA
VOB
FBB
3
VOD
4
VOC
5
FBC
REFAB
CLR
CS
6
REFCD
N/C
7
8
REFOUT
SDO
SDI
9
SCK
10
DGND
TOP VIEW
PIN DESCRIPTION (20 Lead QSOP)
Pin
Name
I/O
Description
1
2
VDD
FBA
I
I
Supply Voltage
Inverting Input of The Output Amplifier DAC A. Output Amplifier Feedback Input.
3
VOA
O
O
I
DAC A Output Voltage
4
VOB
DAC B Output Voltage
5
FBB
Inverting Input of The Output Amplifier DAC B. Output Amplifier Feedback Input.
6
REFAB
CLR
I
Reference Voltage Input for DAC A and DAC B
7
I
Active Low Clear Input (CMOS). Resets All Registers to Zero. DAC outputs go to 0 V
8
I
Active Low Chip Select (CMOS)
CS
9
SDI
I
Serial Data Input (CMOS)
10
11
12
13
14
15
16
17
18
19
20
SCK
I
Serial Clock Input (CMOS)
DGND
SDO
REFOUT
N/C
I
Digital Ground
O
O
-
Serial Data Output
Reference Output
No Connection
REFCD
FBC
I
Reference Voltage Input for DAC C and DAC D
Inverting Input of The Output Amplifier DAC C. Output Amplifier Feedback Input.
DAC C Output Voltage
I
VOC
VOD
FBD
O
O
I
DAC D Output Voltage
Inverting Input of The Output Amplifier DAC D. Output Amplifier Feedback Input.
Analog Ground
AGND
I
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
2
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
ABSOLUTE MAXIMUM RATING
Symbol
Parameter
Value
Unit
Supply Voltage
Input Current
-0.3 to 7.0
+/- 25.0
V
V
DD
mA
V
I
IN
-0.3 to 7.0
-0.3 to 7.0
-65 to +150
300
Digital Input Voltage (SCK, SDI, CS , CLR )
Reference Input Voltage
V
V
_
IN
V
_
IN REF
STG
Storage Temperature
oC
oC
T
T
Soldering Temperature
SOL
Note: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ORDERING INFORMATION
Part
Operating Temperature Range
Package
ICM7377B
ICM7357B
ICM7337B
-40 oC to 85 oC
-40 oC to 85 oC
-40 oC to 85 oC
20-Pin QSOP
20-Pin QSOP
20-Pin QSOP
DC ELECTRICAL CHARACTERISTICS
(V = 2.7V to 5.5V; V
DD
unloaded; all specifications T
to T
unless otherwise noted)
MAX
OUT
MIN
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DC PERFORMANCE
ICM7377B
N
Resolution
12
Bits
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
(Notes 1 & 3)
0.4
+1.0
LSB
LSB
(Notes 1 & 3)
4.0
+12.0
ICM7357B
N
Resolution
10
Bits
LSB
LSB
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
(Notes 1 & 3)
(Notes 1 & 3)
0.1
1.0
+1.0
+3.0
ICM7337B
N
Resolution
8
Bits
LSB
LSB
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
(Notes 1 & 3)
(Notes 1 & 3)
0.05
0.25
+1.0
+0.75
GE
OE
Gain Error
+0.5
+25
% of FS
mV
Offset Error
POWER REQUIREMENTS
Supply Voltage
Supply Current
2.7
5.5
1.5
V
V
DD
0.6
mA
I
DD
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
3
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Output Voltage Range
(Note 3)
0
VDD
V
Short Circuit Current
Amp Output Impedance
Output Line Regulation
60
150
mA
VO
SC
At Mid-scale (Note 2)
At 0-scale (Note 2)
1.0
100
5.0
200
Ω
Ω
R
OUT
0.4
3.0
mV/V
V
=2.7 to 5.5 V
DD
LOGIC INPUTS
Digital Input High
(Note 2)
(Note 2)
2.4
1.2
V
V
V
IH
IL
Digital Input Low
0.8
5
V
Digital Input Leakage
µΑ
REFERENCE
Reference Output
1.25
0.8
1.3
4.0
V
V
REFOUT
Reference Output Line
Regulation
mV/V
V
=2.7 to 5.5 V
DD
AC ELECTRICAL CHARACTERISTICS
(V = 2.7V to 5.5V; V
DD
unloaded; all specifications T
to T
unless otherwise noted)
MAX
OUT
MIN
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
SR
Slew Rate
Settling Time
2
8
V/µs
µs
Mid-scale Transition Glitch
Energy
nV-S
40
Note 1: Linearity is defined from code 64 to 4095 (ICM7377B)
Linearity is defined from code 16 to 1023 (ICM7357B)
Linearity is defined from code 4 to 255 (ICM7337B)
Note 2: Guaranteed by design; not tested in production
Note 3: See Applications Information
Note 4: All digital inputs are either at GND or VDD
TIMING CHARACTERISTICS
(V = 2.7V to 5.5V; all specifications T
DD
to T unless otherwise noted)
MAX
MIN
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
SCK Cycle Time
Data Setup Time
Data Hold Time
(Note 2)
(Note 2)
(Note 2)
30
10
10
0
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
1
2
3
4
5
6
(Note 2)
(Note 2)
(Note 2)
SCK Falling edge to CS Rising Edge
Falling Edge to SCK Rising Edge
CS
15
20
Pulse Width
CS
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
4
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
t6
CS
t1
t5
t4
SCK
t2
SDI
C3
D0
t3
DAC INPUT WORD
Figure 1. Serial Interface Timing Diagram
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
5
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
(ENABLE
SCK)
CS
(UPDATE
OUTPUT)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CONTROL WORD
DATA WORD
INPUT WORD W
0
SDO
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C3
INPUT WORD W
INPUT WORD W
-1
0
Figure 2. Serial Interface Operation Diagram
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
6
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
CONTENTS OF INPUT SHIFT REGISTER
ICM7377B (12-Bit DAC)
MSB
LSB
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CONTROL WORD
DATA WORD
Figure 3. Contents of ICM7377B Input Shift Register
ICM7357B (10-Bit DAC)
MSB
LSB
X
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
CONTROL WORD
DATA WORD
X
Figure 4. Contents of ICM7357B Input Shift Register
ICM7337B (8-Bit DAC)
MSB
LSB
X
C3
C2
C1
C0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
CONTROL WORD
DATA WORD
X
Figure 5. Contents of ICM7337B Input Shift Register
C3
C2
C1
C0
DATA (D0 - D11)
FUNCTION
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
X
Load Input Latch DAC A
Update DAC A
Load Input Latch and Update DAC A
Load Input Latch DAC B
Update DAC B
Load Input Latch and Update DAC B
Load Input Latch DAC C
Update DAC C
Load Input Latch and Update DAC C
Load Input Latch DAC D
Update DAC D
Load Input Latch and Update DAC D
Load Input Latch All DACs
Update All DACs
Load Input Latch and Update All DACs
No Operation
Table 1. Serial Interface Input Word
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
7
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
the data to be transferred to an input bank of latches. This
pin also disables the SCK pin internally when pulled high
and the SCK pin must be low before this pin is pulled back
low. As the Chip Select pin is pulled high the shift register
contents are transferred to a bank of 16 latches (see
Figure 2.). The 4 bit control word (C3~C0) is then decoded
and the DAC is updated or loaded depending on the
control word (see Table 1).
DETAILED DESCRIPTION
The ICM7377B is a 12-bit voltage output quad DAC. The
ICM7357B is the 10-bit version of this family and the
ICM7337B is the 8-bit version.
This family of DACs employs a resistor string architecture
a 1.25V
guaranteeing monotonic behavior. There is
onboard reference and an operating supply range of 2.7V
to 5.5V.
The DAC has a double-buffered input with an input latch
and a DAC latch. The DAC output will swing to its new
value when data is loaded into the DAC latch. The user
has three options: loading only the input latch, updating
the DAC with data previously loaded into the input latch or
loading the input latch and updating the DAC at the same
time with a new code.
Reference Input
There are two reference inputs that can be driven from
ground to VDD–1.5V. Determine the output voltage using
the following equation:
V
= V
x (D / (2n))
REF
OUT
Serial Data Output
SDO (Serial Data Output) is the internal shift register’s
output. This pin can be used as the data output pin for
Daisy-Chaining and data readback. And it is compatible
with SPI/QSPI and Microwire interfaces.
Where D is the numeric value of DAC’s decimal input
code, V is the reference voltage and n is number of
bits, i.e. 12 for ICM7377B, 10 for ICM7357B and 8 for
ICM7337B.
REF
Reference Output
Power-On Reset
There is a power-on reset on board that will clear the
contents of all the latches to all 0s on power-up and the
DAC voltage output will go to ground.
The reference output is nominally 1.25V and is brought out
to a separate pin and can be used to drive external loads.
The outputs will nominally swing from 0 to 2.5V.
Output Amplifier
APPLICATIONS INFORMATION
The Quad DAC has 4 output amplifiers with a wide output
swing. The actual swing of the output amplifiers will be
limited by offset error and gain error. See the Applications
Information Section for a more detailed discussion.
Power Supply Bypassing and Layout
Considerations
As in any precision circuit, careful consideration has to be
given to layout of the supply and ground. The return path
from the GND to the supply ground should be short with
low impedance. Using a ground plane would be ideal. The
supply should have some bypassing on it. A 10 µF
tantalum capacitor in parallel with a 0.1 µF ceramic with a
low ESR can be used. Ideally these would be placed as
close as possible to the device. Avoid crossing digital and
analog signals, specially the reference, or running them
close to each other.
The 4 output amplifier’s inverting input of 4 DACs are
available to the user, allowing force and sense capability
for remote sensing and specific gain adjustment. The unity
gain can be provided by connecting the inverting input to
the output.
The output amplifier can drive a load of 2.0 kΩ to V
GND in parallel with a 500 pF load capacitance.
or
DD
Output Swing Limitations
The ideal rail-to-rail DAC would swing from GND to V
The output amplifier has a full-scale typical settling time of
8 µs and it dissipates about 100 µA with a 3V supply
voltage.
.
DD
However, offset and gain error limit this ability. Figure 6
illustrates how a negative offset error will affect the output.
The output will limit close to ground since this is single
supply part, resulting in a dead-band area. As a larger
input is loaded into the DAC the output will eventually rise
above ground. This is why the linearity is specified for a
starting code greater than zero.
Serial Interface and Input Logic
This quad DAC family uses a standard 3-wire connection
compatible with SPI/QSPI and Microwire interfaces. Data
is loaded in 16-bit words which consist of 4 address and
control bits (MSBs) followed by 12 bits of data (see table
1). The ICM7357 has the last 2 LSBs as don’t care and the
ICM7337 has the last 4 LSBs as don’t care. The DAC is
double buffered with an input latch and a DAC latch.
Figure 7 illustrates how a gain error or positive offset error
will affect the output when it is close to V . A positive
DD
gain error or positive offset will cause the output to be
limited to the positive supply voltage resulting in a dead-
band of codes close to full-scale.
Serial Data Input
SDI (Serial Data Input) pin is the data input pin for All
DACs. Data is clocked in on the rising edge of SCK which
has a Schmitt trigger internally to allow for noise immunity
on the SCK pin. This specially eases the use for opto-
coupled interfaces.
The Chip Select pin which is the 8th pin of 20 QSOP
package is active low. This pin must be low when data is
being clocked into the part. After the 16th clock pulse the
Chip Select pin must be pulled high (level-triggered) for
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
8
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
DEADBAND
NEGATIVE
OFFSET
Figure 6. Effect of Negative Offset
OFFSET AND
GAIN ERROR
VDD
DEADBAND
POSITIVE
OFFSET
Figure 7. Effect of Gain Error and Positive Offset
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
9
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
PACKAGE INFORMATION
20 QSOP
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
10
ICM7377B/7357B/7337B
Quad 12/10/8-Bit Voltage Output DACs
with Serial Interface and Adjustable Output Gain
IC MICROSYSTEMS
ORDERING INFORMATION
ICM73X7B P G
Device
G = RoHS Compliant Lead-Free package.
Blank = Standard package. Non lead-free.
7 - ICM7377B
5 - ICM7357B
3 - ICM7337B
Package
Q = 20-Lead QSOP
Rev. A8
ICmic reserves the right to change the specifications without prior notice.
11
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