ICM7361T [ICMIC]

SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS; 一个12 /10/ 8位电压输出DAC
ICM7361T
型号: ICM7361T
厂家: IC MICROSYSTEMS    IC MICROSYSTEMS
描述:

SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS
一个12 /10/ 8位电压输出DAC

输出元件
文件: 总9页 (文件大小:167K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
IC
mic  
ICM7361/7341/7321  
IC MICROSYSTEMS  
SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS  
with guaranteed monotonic behavior. These DACs are  
available in both a tiny 6-pin SOT-23 package and an 8-  
pin MSOP package. They include a 1.25V reference for  
ease of use and flexibility. The reference output is  
available on a separate pin, in the 8-pin package version,  
and can be used to drive external loads. The operating  
supply range is 2.7V to 5.5V.  
FEATURES  
12/10/8-Bit Monotonic DACs in 6 lead SOT-23  
Package  
Wide Output Voltage Swing  
Micro-Power  
On Board 1.25V Reference  
Serial Interface with three-wire SPI/QSPI and  
Microwire Interface Compatible  
8µs Full-Scale Settling Time  
The input interface is an easy to use three-wire SPI/QSPI  
compatible interface. The DAC has a double buffered  
digitalkinput.  
APPLICATIONS  
Battery-Powered Applications  
Industrial Process Control  
Digital Gain and Offset Adjustment  
OVERVIEW  
The ICM7361, ICM7341 and ICM7321 are 12-Bit, 10-Bit  
and 8-Bit wide output voltage swing DACs respectively,  
BLOCK DIAGRAM  
VDD  
ICM 7361/7341/7321  
REFOUT  
Reference  
(MSOP-8  
Package Only)  
Input and  
DAC Latch  
12/10/8 -Bit  
x2  
VOUT  
DAC  
Input Control Logic, Registers and Latches  
SDI  
Power-On-  
Reset  
SCK  
CS  
GND  
PACKAGE  
SOT-23  
8-Pin MSOP  
1
2
3
6
5
4
VOUT  
CS  
1
2
3
4
8
7
6
5
VDD  
REFOUT  
NC  
GND  
SDI  
SCK  
CS  
GND  
VDD  
SCK  
SDI  
VOUT  
Rev. A8  
ICmic reserves the right to change the specifications without prior notice.  
1
IC
mic  
ICM7361/7341/7321  
IC MICROSYSTEMS  
SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS  
PIN DESCRIPTION (MSOP-8 Package)  
Pin No  
Symbol  
Description  
1
2
3
4
VDD  
Supply Voltage  
Reference Output (1.25V)  
No Connect  
REFOUT  
NC  
VOUT  
DAC Output  
5
6
CS  
SCK  
Chip Select (TTL or CMOS)  
Serial Clock Input (TTL or CMOS)  
7
8
SDI  
Serial Data Input (TTL or CMOS)  
Ground  
GND  
PIN DESCRIPTION (SOT-23 Package)  
Pin No  
Symbol  
Description  
1
2
3
VOUT  
DAC Output  
Ground  
GND  
VDD  
Supply Voltage  
4
5
SDI  
Serial Data Input (TTL or CMOS)  
Serial Clock Input (TTL or CMOS)  
SCK  
6
CS  
Chip Select (TTL or CMOS)  
ABSOLUTE MAXIMUM RATING  
Symbol  
Parameter  
Value  
-0.3 to 7.0  
Unit  
VDD  
Supply Voltage  
V
IIN  
Input Current  
+/- 25.0  
mA  
V
VIN_  
VIN_REF  
TSTG  
TSOL  
Digital Input Voltage (SCK, SDI, CS)  
Reference Input Voltage  
Storage Temperature  
Soldering Temperature  
-0.3 to 7.0  
-0.3 to 7.0  
-65 to +150  
300  
V
oC  
oC  
Note: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
Rev. A8  
ICmic reserves the right to change the specifications without prior notice.  
2
IC
mic  
ICM7361/7341/7321  
IC MICROSYSTEMS  
SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS  
ORDERING INFORMATION  
Part  
Temperature Range  
Package  
ICM7361M  
ICM7341M  
ICM7321M  
-40 oC to 85 oC  
-40 oC to 85 oC  
-40 oC to 85 oC  
8-Pin MSOP  
8-Pin MSOP  
8-Pin MSOP  
ORDERING INFORMATION  
Part  
Temperature Range  
Package  
ICM7361T  
ICM7341T  
ICM7321T  
-40 oC to 85 oC  
-40 oC to 85 oC  
-40 oC to 85 oC  
SOT-23  
SOT-23  
SOT-23  
DC ELECTRICAL CHARACTERISTICS  
(VDD = 2.7V to 5.5V ; VOUT unloaded; all specifications TMIN toTMAX unless otherwise noted)  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
DC PERFORMANCE  
ICM7361  
N
DNL  
INL  
Resolution  
Differential Nonlinearity  
Integral Nonlinearity  
12  
Bits  
LSB  
LSB  
(Notes 1 & 3)  
(Notes 1 & 3)  
0.4  
4.0  
+1.0  
+12.0  
ICM7341  
N
Resolution  
10  
8
Bits  
LSB  
LSB  
DNL  
INL  
Differential Nonlinearity  
Integral Nonlinearity  
(Notes 1 & 3)  
(Notes 1 & 3)  
0.1  
1.0  
+1.0  
+3.0  
ICM7321  
N
Resolution  
Bits  
LSB  
LSB  
DNL  
INL  
Differential Nonlinearity  
Integral Nonlinearity  
(Notes 1 & 3)  
(Notes 1 & 3)  
0.05  
0.25  
+1.0  
+0.75  
GE  
OE  
Gain Error  
Offset Error  
+0.5  
+25  
% of FS  
mV  
POWER REQUIREMENTS  
VDD  
IDD  
Supply Voltage  
Supply Current  
2.7  
5.5  
0.5  
V
mA  
(Note 4)  
0.2  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
OUTPUT CHARACTERISTICS  
Output Voltage Range  
(Note 3)  
0
VDD  
V
VOSC  
ROUT  
Short Circuit Current  
Amp Output Impedance  
60  
1.0  
100  
150  
5.0  
200  
mA  
At Mid-scale (Note 2)  
At 0-scale (Note 2)  
Output Line Regulation  
VDD =2.7 to 5.5 V  
0.4  
3.0  
mV/V  
LOGIC INPUTS  
VIH  
VIL  
Digital Input High  
Digital Input Low  
Digital Input Leakage  
(Note 2)  
(Note 2)  
2.4  
V
V
0.8  
5
µΑ  
Rev. A8  
ICmic reserves the right to change the specifications without prior notice.  
3
IC
mic  
ICM7361/7341/7321  
IC MICROSYSTEMS  
SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS  
REFERENCE  
VREFOUT  
Reference Output  
Reference Output Line  
Regulation  
1.2  
1.25  
0.8  
1.3  
4.0  
V
mV/V  
VDD =2.7 to 5.5 V  
AC ELECTRICAL CHARACTERISTICS  
(VDD = 2.7V to 5.5V; VOUT unloaded; all specifications TMIN toTMAX unless otherwise noted)  
Symbol Parameter Test Conditions Min  
Typ  
Max  
Unit  
SR  
Slew Rate  
2
8
V/µs  
Settling Time  
Full-scale settling  
µs  
Mid-scale Transition Glitch  
Energy  
40  
nV-S  
Note 1: Linearity is defined from code 64 to 4095 (ICM7361)  
Linearity is defined from code 16 to 1023 (ICM7341)  
Linearity is defined from code 4 to 255 (ICM7321)  
Note 2: Guaranteed by design; not tested in production  
Note 3: See Applications Information  
Note 4: All digital inputs are either at GND or VDD  
TIMING CHARACTERISTICS  
(VDD = 2.7V to 5.5V; all specifications TMIN toTMAX unless otherwise noted)  
Symbol  
Parameter  
Test Conditions  
Min  
30  
10  
10  
Typ  
Max  
Unit  
t1  
t2  
t3  
SCK Cycle Time  
Data Setup Time  
Data Hold Time  
(Note 2)  
(Note 2)  
(Note 2)  
ns  
ns  
ns  
t4  
SCK Falling edge to CS  
Rising Edge  
(Note 2)  
(Note 2)  
0
ns  
ns  
t5  
CS Falling Edge to SCK  
Rising Edge  
15  
(Note 2)  
t6  
CS Pulse Width  
20  
ns  
Rev. A8  
ICmic reserves the right to change the specifications without prior notice.  
4
IC
mic  
ICM7361/7341/7321  
IC MICROSYSTEMS  
SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS  
t1  
SCK  
t3  
t2  
SDI  
CS  
C3  
C2  
MSB  
t5  
Input Word for DAC N  
t4  
t6  
Figure 1: Serial Interface Timing Diagram  
CONTENTS OF INPUT SHIFT REGISTER  
ICM7361 (12-Bit DAC)  
MSB  
LSB  
D0  
C3  
C2  
C1  
C0  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D1  
X
D2  
D0  
X
D1  
Figure 2: Contents of ICM7361 Input Shift Register  
ICM7341 (10-Bit DAC)  
MSB  
LSB  
X
C3  
C2  
C1  
C0  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
X
Figure 3: Contents of ICM7341 Input Shift Register  
ICM7321 (8-Bit DAC)  
MSB  
LSB  
X
C3  
C2  
C1  
C0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
X
Figure 4: Contents of ICM7321 Input Shift Register  
C3  
C2  
C1  
C0  
DATA  
FUNCTION  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data  
Data  
Data  
X
X
X
X
X
X
X
X
X
X
X
X
X
Load Input Latch  
Update DAC  
Load Input Latch and Update DAC  
No Operation  
No Operation  
No Operation  
No Operation  
No Operation  
No Operation  
No Operation  
No Operation  
No Operation  
No Operation  
No Operation  
No Operation  
No Operation  
Table 1: Serial Interface Control Command  
Rev. A8  
ICmic reserves the right to change the specifications without prior notice.  
5
IC
mic  
ICM7361/7341/7321  
IC MICROSYSTEMS  
SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS  
then decoded and the DAC is updated or loaded  
depending on the control word (see Table 1).  
DETAILED DESCRIPTION  
The ICM7361 is  
a 12-bit voltage output DAC. The  
ICM7341 is the 10-bit version of this family and the  
ICM7321 is the 8-bit version.  
The DAC has a double-buffered input with an input latch  
and a DAC latch. The DAC output will swing to its new  
value when data is loaded into the DAC latch. The user  
has three options: loading only the input latch, updating  
the DAC with data previously loaded into the input latch or  
loading the input latch and updating the DAC at the same  
time with a new code.  
This family of DACs has guaranteed monotonic behavior.  
There is a 1.25V onboard reference and an operating  
supply range of 2.7V to 5.5V.  
Reference Output  
There is an internal bandgap reference of 1.25V on these  
parts and there is a gain of two in the output amplifiers  
which means they swing from ground at code 0 to 2.5V at  
full-scale :  
Power-On Reset  
There is a power-on reset on board that will clear the  
contents of all the latches to all 0s on power-up and the  
DAC voltage output will go to ground.  
Vout = 2 x (1.25 xD)/2n  
Where D=digital input (decimal) and n= number of bits, i.e.  
12 for ICM7361, 10 for ICM7341 and 8 for ICM7321.  
The reference output is nominally 1.25V and is brought out  
to a separate pin, REFOUT (8-pin MSOP package only)  
and can be used to drive external loads. However, it is still  
internally connected to the DAC reference input. The  
outputs will nominally swing from 0 to 2.5V.  
Output Amplifier  
The DAC has an output amplifier with a wide output  
voltage swing. The actual swing of the output amplifier will  
be limited by offset error and gain error. See the  
Applications Information Section for  
discussion.  
a more detailed  
The amplifier is configured in a gain of 2 with internal gain  
resistors of about 50 k. The output swing will be from 0V  
to 2.5V at full-scale.  
The output amplifier can drive a load of 2.0 kto VDD or  
GND in parallel with a 500 pF load capacitance.  
The output amplifier has a full-scale typical settling time of  
8 µs and it dissipates about 100 µA with a 3V supply  
voltage.  
Serial Interface and Input Logic  
This DAC family uses a standard 3-wire connection  
compatible with SPI/QSPI interfaces. Data is loaded in 16-  
bit words which consist of 4 address and control bits  
(MSBs) followed by 12 bits of data (see table 1). The  
ICM7341 has the last two LSBs as don’t cares and the  
ICM7321 has the last 4 LSBs as don’t cares. The DAC is  
double buffered with an input latch and a DAC latch.  
All the digital inputs are CMOS/TTL compatible. The  
current dissipation of the device however, will be higher  
when the inputs are driven at TTL levels.  
Data is clocked in on the rising edge of SCK which has a  
Schmitt trigger internally to allow for noise immunity on the  
SCK pin. This specially eases the use for opto-coupled  
interfaces.  
The CS pin must be low when data is being clocked into  
the part. After the 16th clock pulse the CS pin must be  
pulled high (level-triggered) for the data to be transferred  
to an input bank of latches. The CS pin also disables the  
SCK pin internally when pulled high and the SCK pin must  
be low before the CS pin is pulled back low. As the CS pin  
is pulled high the shift register contents are transferred to  
a bank of 16 latches. The 4 bit control word (C3~C0) is  
Rev. A8  
ICmic reserves the right to change the specifications without prior notice.  
6
IC
mic  
ICM7361/7341/7321  
IC MICROSYSTEMS  
SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS  
input is loaded into the DAC the output will eventually rise  
above ground. This is why the linearity is specified for a  
starting code greater than zero.  
APPLICATIONS INFORMATION  
Power  
Considerations  
Supply  
Bypassing  
and  
Layout  
Figure 6 illustrates how a gain error or positive offset error  
will affect the output when it is close to VDD. A positive gain  
error or positive offset will cause the output to be limited to  
the positive supply voltage resulting in a dead-band of  
codes close to full-scale.  
As in any precision circuit, careful consideration has to be  
given to layout of the supply and ground. The return path  
from the GND to the supply ground should be short with  
low impedance. Using a ground plane would be ideal. The  
supply should have some bypassing on it. A 10 µF  
tantalum capacitor in parallel with a 0.1 µF ceramic with a  
low ESR can be used. Ideally these would be placed as  
close as possible to the device. Avoid crossing digital and  
analog signals, specially the reference, or running them  
close to each other.  
Output Swing Limitations  
The ideal rail-to-rail DAC would swing from GND to VDD  
however, offset and gain error limit this ability. Figure 5  
illustrates how a negative offset error will affect the output.  
The output will limit close to ground since this is single  
supply part, resulting in a dead-band area. As a larger  
DEADBAND  
NEGATIVE  
OFFSET  
Figure 5: Effect of Negative Offset  
OFFSET AND  
GAIN ERROR  
VDD  
DEADBAND  
POSITIVE  
OFFSET  
Figure 6: Effect of Gain Error and Positive Offset  
Rev. A8  
ICmic reserves the right to change the specifications without prior notice.  
7
IC
mic  
ICM7361/7341/7321  
IC MICROSYSTEMS  
SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS  
PACKAGE INFORMATION  
8-Pin MSOP Package  
SOT-23 Package  
Rev. A8  
ICmic reserves the right to change the specifications without prior notice.  
8
IC
mic  
ICM7361/7341/7321  
IC MICROSYSTEMS  
SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS  
ORDERING INFORMATION  
ICM73X1 P G  
G = RoHS Compliant Lead-Free package.  
Blank = Standard package. Non lead-free.  
Device  
6 - ICM7361  
4 - ICM7341  
2 - ICM7321  
Package  
M = 8-Lead MSOP  
S = 6-Lead SOT-23  
Rev. A8  
ICmic reserves the right to change the specifications without prior notice.  
9

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