HD74CBT32160CT [HITACHI]
Bus Driver, CBT/FST/QS/5C/B Series, 1-Func, 16-Bit, True Output, PDSO56, TSSOP-56;
| 型号： | HD74CBT32160CT |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | Bus Driver, CBT/FST/QS/5C/B Series, 1-Func, 16-Bit, True Output, PDSO56, TSSOP-56 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74CBT32160C
16-bit to 32-bit Demux PCI Hot-plug Bus Switch
ADE-205-673 (Z)
Preliminary
Rev. 0
Feb. 2002
Description
The HD74CBT32160C device provides 16-bit to 32-bit demux PCI Hot-plug bus switching. The low on
state resistance of the switch allows connections to be made with minimal propagation delay. Select
control (SEL1, SEL2) inputs, select the appropriate B1 and B2 outputs for the A-input data.
Features
•
•
Minimal propagation delay through the switch.
5 Ω switch connection between two ports.
Pullup on B1 and B2 ports.
•
•
TTL-compatible input levels.
Ultra low quiescent power.
-Ideally suited for notebook applications.
Package type
•
Product code example: HD74CBT32160CTEL
Package type
Package code
Package suffix
Taping code
TSSOP-56pin
TTP-56DAV
T
EL (1,000 pcs / Reel)
Function Table
Inputs
SEL1
SEL2
Function
L
H
L
nA to nB1
H
L
nA to nB2
L
nA to nB1 and nB2
nB1, nB2 = VBIAS
H
H
H:
L:
High level
Low level
HD74CBT32160C
Pin Arrangement
1B1 1
56 1A
2
55 1B2
2B1
2B2
3A
54
53
52
51
50
2A
3
4
3B1
4B1
4A
3B2
4B2
5A
5
6
5B1
6B1
6A
7
8
49 5B2
6B2
7A
9
48
47
46
10
7B1
8B1 11
7B2
12
13
14
15
16
17
8A
GND
Vcc
45 8B2
GND
Vcc
9A
44
43
42
9B1
41 9B2
10B1
10A
10B2
11A
40
39
38
11B1 18
12B1
19
11B2
20
21
22
23
37 12B2
12A
13B1
14B1
14A
13A
36
35
34
33
32
31
30
29
13B2
14B2
15A
15B1 24
25
26
27
16B1
16A
15B2
16B2
VBIAS2
SEL2
VBIAS1
SEL1 28
(Top view)
Rev.0, Feb. 2002, page 2 of 9
HD74CBT32160C
Absolute Maximum Ratings
Item
Symbol
Ratings
−0.5 to 7.0
−0.5 to 7.0
−50
Unit
V
Conditions
Supply voltage range
Input voltage range *1
Input clamp current
Continuous output current
VCC
VI
V
IIK
mA
mA
mA
VI < 0
IO
128
VO = 0 to VCC
Continuous current through
VCC or GND
I
CC or IGND
100
Maximum power dissipation
at Ta = 25°C (in still air) *2
PT
1.32
W
Storage temperature
Tstg
−65 to 150
°C
Notes:
The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded even if the input and output clamp-current
ratings are observed.
2. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
VCC
Min
4.5
1.3
0
Max
5.5
VCC
5.5
5.5
5
Unit
Conditions
Supply voltage range
V
VBIAS
VI
Input voltage range
V
Output voltage range
VI/O
0
V
Input transition rise or fall rate
Operating free-air temperature
∆t / ∆v
Ta
0
ns / V
°C
VCC = 4.5 to 5.5 V
−40
85
Note: Unused or floating inputs must be held high or low.
Rev.0, Feb. 2002, page 3 of 9
HD74CBT32160C
Logic Diagram
VBIAS1
1A
1B1
1B2
VBIAS2
VBIAS1
16A
16B1
16B2
VBIAS2
SEL1
SEL2
Rev.0, Feb. 2002, page 4 of 9
HD74CBT32160C
DC Electrical Characteristics
(Ta = −40 to 85°C)
Item
Symbol
VCC (V)
Min
Typ*1
Max
−1.2
Unit
V
Test conditions
Clamp diode voltage VIK
4.5
IIN = −18 mA
Input voltage
VIH
VIL
4.0 to 5.5 2.0
V
4.0 to 5.5
4.5
0.8
8
On-state switch
resistance *2
RON
5
Ω
VIN = 0 V,
IIN = 48 mA
4.5
10
15
VIN = 2.4 V,
IIN = 15 mA
Input current
IIN
0 to 5.5
5.5
1.0
20
µA
µA
VIN = 5.5 V or GND
A = 5.5 V, VBIAS = 5.5 V
Off-state leakage
current
IOZA
–1.0
A = 0 V, VBIAS = 5.5 V
B = 5.5 V, VBIAS = 5.5 V
B = 0 V, VBIAS = 5.5 V
IOZB
1.0
–0.25
3
–5
mA
Quiescent supply
current
ICC
5.5
5.5
µA
VIN = VCC or GND,
IO = 0 mA
Increase in ICC
per input *3
∆ICC
2.5
mA
One input at 3.4 V,
other inputs at VCC or
GND
Notes:
For condition shown as Min or Max use the appropriate values under recommended operating
conditions.
1. All typical values are at VCC = 5 V (unless otherwise noted), Ta = 25°C.
2. Measured by the voltage drop between the A and B terminals at the indicated current through the
switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals.
3. This is the increase in supply current for each input that is at the specified TTL voltage level
rather than VCC or GND.
Capacitance
(Ta = 25°C)
Item
Symbol VCC (V)
Min
Typ
Max
Unit
Test conditions
Control input
capacitance
CIN
5.0
5
pF
VIN = 0 or 3 V
Input / output A port
CI/O (OFF)
5.0
10
7
pF
VO = 0 or 3 V
SEL1, SEL2 = VCC
capacitance
B port
Note: This parameter is determined by device characterization is not production tested.
Rev.0, Feb. 2002, page 5 of 9
HD74CBT32160C
Switching Characteristics
(Ta = −40 to 85°C)
•
VCC = 5.0 0.5 V, VBIAS = VCC
Test
conditions
FROM
(Input)
TO
(Output)
Item
Symbol
Min
Max
Unit
Propagation delay
time *1
tPLH
tPHL
0.25
ns
CL = 50 pF
RL = 500 Ω
A or B
B or A
A or B
A or B
Enable time
tZH
tZL
2.0
7.0
ns
ns
CL = 50 pF
RL = 500 Ω
SEL
Disable time
tHZ
tLZ
2.0
2.0
6.0
7.0
CL = 50 pF
RL = 500 Ω
SEL
Notes: 1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output
impedance).
Test Circuit
See under table
S1
500 Ω
OPEN
GND
*1
CL = 50 pF
500 Ω
Load circuit for outputs
Symbol
tPLH/ tPHL
tZH / tHZ
tZL / tLZ
S1
OPEN
OPEN
7 V
Note: 1. CL includes probe and jig capacitance.
Rev.0, Feb. 2002, page 6 of 9
HD74CBT32160C
Waveforms – 1
tr
tf
3 V
90 %
1.5 V
90 %
1.5 V
Input
10 %
10 %
tPHL
GND
VOH
tPLH
1.5 V
1.5 V
Output
VOL
Waveforms – 2
tf
tr
3 V
90 %
1.5 V
90 %
1.5 V
Output
Control
10 %
tZL
10 %
GND
3.5 V
tLZ
Waveform - A
Waveform - B
1.5 V
VOL + 0.3 V
VOL
VOH
tZH
tHZ
VOH - 0.3 V
1.5 V
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform - A is for an output with internal conditions such that the output is low except
when disabled by the output control.
3. Waveform - B is for an output with internal conditions such that the output is high except
when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.0, Feb. 2002, page 7 of 9
HD74CBT32160C
Package Dimensions
As of July, 2001
14.0
14.2 Max
Unit: mm
56
29
1
28
0.50
0.08
*0.19 0.05
M
1.0
8.10 0.20
0.65 Max
0˚ – 8˚
0.50 0.1
0.10
Hitachi Code
TTP-56DAV
JEDEC
—
JEITA
—
*Pd plating
Mass (reference value)
0.32 g
Rev.0, Feb. 2002, page 8 of 9
HD74CBT32160C
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
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products.
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Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 5.0
Rev.0, Feb. 2002, page 9 of 9
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