HD74CBT3257 [HITACHI]
4-bit 1-of-2 FET Multiplexer / Demultiplexer; 4位1的- 2 FET多路复用器/多路解复用器
| 型号： | HD74CBT3257 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | 4-bit 1-of-2 FET Multiplexer / Demultiplexer |
| 文件： | 总11页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74CBT3257
4-bit 1-of-2 FET Multiplexer / Demultiplexer
ADE-205-624B (Z)
Rev. 2
Nov. 2001
Description
The HD74CBT3257 is a 4-bit 1-of-2 high-speed TTL-compatible FET multiplexer / demultiplexer. The
low on-state resistance of the switch allows connections to be made with minimal propagation delay.
Output enable (OE) and select control (S) inputs select the appropriate B1 and B2 outputs for the A-input
data.
Features
•
•
•
•
Minimal propagation delay through the switch.
5 Ω switch connection between two ports.
TTL-compatible input levels.
Ultra low quiescent power.
-Ideally suited for notebook applications.
Package type
•
Product code example: HD74CBT3257TELL
Package type
Package code
Package suffix
Taping code
TSSOP-16pin
TTP-16DA
T
ELL(2000pcs / Reel)
Notes: 1. As for the Pb-free package is attached the “V” to the end of package code.
2. As for the Pb-free product is attached the “–E” to the end of product code.
HD74CBT3257
Function Table
Inputs
OE
L
S
L
Function
A port = B1 port
A port = B2 port
Disconnect
L
H
X
H
H:
L:
High level
Low level
Immaterial
X:
Pin Arrangement
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
1B1
1B2
1A
VCC
OE
4B1
4B2
4A
2B1
2B2
2A
3B1
3B2
3A
GND
(Top view)
Rev.2, Nov. 2001, page 2 of 11
HD74CBT3257
Absolute Maximum Ratings
Item
Symbol
Ratings
−0.5 to 7.0
−0.5 to 7.0
−50
Unit
V
Conditions
Supply voltage range
Input voltage range *1
Input clamp current
Continuous output current
VCC
VI
V
IIK
mA
mA
mA
VI < 0
IO
128
VO = 0 to VCC
Continuous current through
VCC or GND
I
CC or IGND
100
Maximum power dissipation
PT
500
mW
TSSOP
at Ta = 25°C (in still air) *2
Storage temperature
Tstg
−65 to 150
°C
Notes:
The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded even if the input and output clamp-current
ratings are observed.
2. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
VCC
Min
4.0
0
Max
5.5
5.5
5.5
5
Unit
V
Conditions
Supply voltage range
Input voltage range
Output voltage range
Input transition rise or fall rate
Operating free-air temperature
VI
V
VI/O
0
V
∆t / ∆v
Ta
0
ns / V
°C
VCC = 4.5 to 5.5 V
−40
85
Note: Unused or floating inputs must be held high or low.
Rev.2, Nov. 2001, page 3 of 11
HD74CBT3257
Block Diagram
2
4
1A
1B1
3
5
1B2
2B1
7
2A
6
2B2
3B1
11
9
3A
10
14
3B2
4B1
12
4A
13
4B2
1
S
15
OE
Rev.2, Nov. 2001, page 4 of 11
HD74CBT3257
DC Electrical Characteristics
(Ta = −40 to 85°C)
Item
Symbol
VCC (V)
Min
Typ*1
Max
−1.2
Unit
V
Test conditions
Clamp diode voltage VIK
4.5
IIN = −18 mA
Input voltage
VIH
VIL
4.0 to 5.5 2.0
V
4.0 to 5.5
4.0
0.8
20
On-state switch
resistance *2
RON
14
Ω
VIN = 2.4 V,
IIN = 15 mA
Typ at VCC = 4.0 V
4.5
4.5
4.5
5
7
VIN = 0 V,
IIN = 64 mA
5
7
VIN = 0 V,
IIN = 30 mA
10
15
VIN = 2.4 V,
IIN = 15 mA
Input current
IIN
0 to 5.5
5.5
1.0
1.0
µA
µA
VIN = 5.5 V or GND
Off-state leakage
current
IOZ
0 ≤ A, B ≤ VCC
Quiescent supply
current
ICC
5.5
5.5
3
µA
VIN = VCC or GND,
IO = 0 mA
Increase in ICC
per input *3
∆ICC
2.5
mA
One input at 3.4 V,
other inputs at VCC or
GND
Notes:
For condition shown as Min or Max use the appropriate values under recommended operating
conditions.
1. All typical values are at VCC = 5 V (unless otherwise noted), Ta = 25°C.
2. Measured by the voltage drop between the A and B terminals at the indicated current through the
switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals.
3. This is the increase in supply current for each input that is at the specified TTL voltage level
rather than VCC or GND.
Capacitance
(Ta = 25°C)
Item
Symbol VCC (V)
Min
Typ
Max
Unit
Test conditions
Control input
capacitance
CIN
5.0
3.5
pF
VIN = 0 or 3 V
Input / output
capacitance
A port CI/O (OFF)
B port
5.0
5.0
9
5
pF
VO = 0 or 3 V
OE = VCC
Note: This parameter is determined by device characterization is not production tested.
Rev.2, Nov. 2001, page 5 of 11
HD74CBT3257
Switching Characteristics
(Ta = −40 to 85°C)
•
VCC = 4.0 V
Test
conditions
FROM
(Input)
TO
(Output)
Item
Symbol
Min
Max
Unit
Propagation delay
time *1
tPLH
tPHL
0.35
ns
CL = 50 pF
RL = 500 Ω
A or B
B or A
Propagation delay
time
tPLH
tPHL
5.5
ns
ns
CL = 50 pF
RL = 500 Ω
S
A
Enable time
tZH
tZL
5.7
5.6
5.2
5.5
5.2
6.4
CL = 50 pF
RL = 500 Ω
S
B
OE
S
A or B
B
Disable time
tHZ
ns
CL = 50 pF
RL = 500 Ω
OE
S
A or B
B
tLZ
OE
A or B
•
VCC = 5.0 0.5 V
Test
conditions
FROM
(Input)
TO
(Output)
Item
Symbol
Min
Max
Unit
Propagation delay
time *1
tPLH
tPHL
0.25
ns
CL = 50 pF
RL = 500 Ω
A or B
B or A
Propagation delay
time
tPLH
tPHL
1.6
5.0
ns
ns
CL = 50 pF
RL = 500 Ω
S
A
Enable time
tZH
tZL
1.6
1.8
1.0
2.2
1.0
2.2
5.2
5.1
5.0
5.5
5.0
6.8
CL = 50 pF
RL = 500 Ω
S
B
OE
S
A or B
B
Disable time
tHZ
ns
CL = 50 pF
RL = 500 Ω
OE
S
A or B
B
tLZ
OE
A or B
Note: 1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output
impedance).
Rev.2, Nov. 2001, page 6 of 11
HD74CBT3257
Test Circuit
See under table
OPEN
GND
S1
500 Ω
*1
CL = 50 pF
500 Ω
Load circuit for outputs
Symbol
tPLH/ tPHL
tZH / tHZ
tZL / tLZ
S1
OPEN
OPEN
7 V
Note: 1. CL includes probe and jig capacitance.
Rev.2, Nov. 2001, page 7 of 11
HD74CBT3257
Waveforms – 1
tr
tf
3 V
90 %
1.5 V
90 %
1.5 V
Input
10 %
10 %
tPHL
GND
VOH
tPLH
1.5 V
1.5 V
Output
VOL
Waveforms – 2
tf
tr
3 V
90 %
90 %
1.5 V
1.5 V
Output
Control
10 %
tZL
10 %
GND
3.5 V
tLZ
Waveform - A
Waveform - B
1.5 V
VOL + 0.3 V
VOH - 0.3 V
VOL
VOH
tZH
tHZ
1.5 V
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform - A is for an output with internal conditions such that the output is low except
when disabled by the output control.
3. Waveform - B is for an output with internal conditions such that the output is high except
when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.2, Nov. 2001, page 8 of 11
HD74CBT3257
Package Dimensions
As of July, 2001
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
+ 0.08
– 0.07
*0.ꢀꢀ
0.ꢀ0 0.06
6.40 0.ꢀ0
0˚ – 8˚
0.50 0.10
0.10
Hitachi Code
JEDEC
TTP-16DA
—
JEITA
Mass (reference value)
—
0.05 g
*Dimension including the plating thickness
Base material dimension
Rev.2, Nov. 2001, page 9 of 11
HD74CBT3257
As of July, 2001
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
*
0.ꢀ0 0.05
6.40 0.ꢀ0
0˚ – 8˚
0.50 0.10
0.10
Hitachi Code
JEDEC
TTP-16DAV
—
JEITA
—
*Pd plating
Mass (reference value)
0.05 g
Rev.2, Nov. 2001, page 10 of 11
HD74CBT3257
Disclaimer
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 5.0
Rev.2, Nov. 2001, page 11 of 11
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