MB90V820B [FUJITSU]
16-bit Microcontroller; 16位微控制器
| 型号： | MB90V820B |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Microcontroller |
| 文件： | 总56页 (文件大小：1645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13751-2E
16-bit Microcontroller
CMOS
F2MC-16LX MB90820B Series
MB90822B/823B/F822B/F823B/F828B/V820B
■ DESCRIPTION
The MB90820B series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control
applications which require high-speed real-time processing, such as consumer products.
While inheriting the AT architecture of the F2MC family, the instruction set for the F2MC-16LX CPU core of the
MB90820B series incorporates additional instructions for high-level languages, supports extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90820B series has an on-chip 32-bit accumulator which
enables processing of long-word data.
The peripheral resources integrated in the MB90820B series include : an 8/10-bit A/D converter, 8-bit D/A con-
verters, UARTs (SCI) 0, 1, multi-functional timer (16-bit free-run timer, input capture units (ICUs) 0 to 3, output
compare units (OCUs) 0 to 5, 16-bit PPG timer 0, waveform generator), 16-bit PPG timer 1, 2, PWC 0, 1, 16-bit
reload timer 0, 1 and DTP/external interrupt.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Minimum execution time of instruction : 42 ns / 4 MHz oscillation (uses PLL clock multiplication) maximum
multiplier = 6
• Maximum memory space 16 M bytes, Linear/bank access
• Instruction set optimized for controller applications
Supported data types : bit, byte, word, and long-word types
Standard addressing modes : 23 types
32-bit accumulator enhancing high-precision operations
Signed multiplication/division instructions and enhanced RETI instructions
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.1
MB90820B Series
(Continued)
• Enhanced high level language (C) and multi-tasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
• Program patch function (for two address pointers)
• Increased execution speed : 4-byte instruction queue
• Powerful interrupt function
Up to eight priority levels programmable
External interrupt inputs : 8 channels
• Automatic data transmission function independent of CPU operation
Up to 16 channels for the extended intelligent I/O service
DTP request inputs : 8 channels
• Internal ROM
Flash memory : 64 K/128 K bytes with flash security
MASK ROM : 64 K/128 K bytes
• Internal RAM
Evaluation product : 16 K bytes
Flash memory : 4 K/8 K bytes
MASK ROM : 4 K bytes
• General-purpose ports
Up to 66 channels (ports where pull-up resistor can be configured : 32 channels)
• A/D Converter (RC) : 16 channels
8/10-bit resolution selectable
Conversion time : Min 3 µs (24 MHz operation, including sampling time)
• 8-bit D/A Converter : 2 channels
• UART : 2 channels
• 16-bit PPG timer : 3 channels
Mode switching function provided (PWM mode or one-shot mode)
ch.0 can be worked with multi-functional timer or independently
• 16-bit reload timer : 2 channels
• 16-bit PWC timer : 2 channels
• Clock supervisor
• Multi-functional timer
Input capture : 4 channels
Output compare with selectable buffer : 6 channels
Free-run timer with up or up-down mode selection and selectable buffer: 1 channel
16-bit PPG timer : 1 channel
Waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time)
• Time-base timer/watchdog timer : 18-bit
• Low-power consumption mode :
Sleep mode
Stop mode
CPU intermittent operation mode
• Package :
LQFP-80 (FPT-80P-M21 : 0.50 mm pitch)
LQFP-80 (FPT-80P-M22 : 0.65 mm pitch)
QFP-80 (FPT-80P-M06 : 0.80 mm pitch)
• CMOS technology
2
DS07-13751-2E
MB90820B Series
■ PRODUCT LINEUP
Part number
Item
MB90V820B MB90F822B MB90F823B MB90F828B MB90822B
MB90823B
Evaluation
product
Flash memory product
with flash security
Classification
MASK ROM product
ROM size
RAM size
—
64 K bytes
128 K bytes
128 K bytes
8 K bytes
64 K bytes
128 K bytes
4 K bytes
16 K bytes
4 K bytes
Number of instruction : 351
Minimum execution time : 42 ns / 4 MHz (PLL × 6)
Addressing mode : 23
Data bit length : 1, 8, 16 bits
CPU function
I/O port
Maximum memory space: 16 M bytes
I/O port (CMOS) : 66
Pulse width counter timer : 2 channels
Timer function (select the counter timer from three internal clocks)
PWC
Various pulse width measuring function (“H” pulse width, “L” pulse width, rising edge to fall-
ing edge period, falling edge to rising edge period, rising edge to rising edge period and fall-
ing edge to falling edge period)
UART : 2 channels
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be
selected and used.
UART
Transmission can be one-to-one (bidirectional communication) or one-to-n (master-slave
communication).
16-bit
Reload timer : 2 channels
reload timer
Reload mode, single-shot mode or event count mode selectable
PPG timer : 3 channels
16-bit
PPG timer
PWM mode or single-shot mode selectable
Ch.0 can be worked with multi-functional timer or independently.
16-bit free-run timer with up or up-down mode selection and buffer : 1 channel
16-bit output compare : 6 channels
16-bit input capture : 4 channels
16-bit PPG timer : 1 channel
Waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time)
Multi-functional
timer
(for AC/DC
motor control)
8/10-bit
8/10-bit resolution (16 channels)
A/D converter
Conversion time : Min 3 µs (24 MHz internal clock, including sampling time)
8-bit
D/A converter
8-bit resolution (2 channels)
DTP/External
interrupt
8 independent channels
Interrupt trigger : Rising edge, falling edge, “L” level or “H” level
Clock supervisor
No
Yes
No
Low-power
consumption
Stop mode / Sleep mode / CPU intermittent operation mode
(Continued)
DS07-13751-2E
3
MB90820B Series
(Continued)
Part number
MB90V820B MB90F822B MB90F823B MB90F828B MB90822B
MB90823B
Item
LQFP-80 (FPT-80P-M21 : 0.50 mm pitch)
LQFP-80 (FPT-80P-M22 : 0.65 mm pitch)
QFP-80 (FPT-80P-M06 : 0.80 mm pitch)
Package
PGA-299
3.5 V to 5.5 V : Normal operation when A/D converter and
D/A converter are not used
4.0 V to 5.5 V : Normal operation when D/A converter is not
used
4.5 V to 5.5 V : Normal operation when A/D converter and
D/A converter are used
Power supply
voltage for
operation
4.5 V to
5.5 V*1
Process
CMOS
Emulator power
supply*2
Included
⎯
*1 : MB90V820B is operating guaranteed temperature 0 °C to + 25 °C.
*2 : Configured by a jumper switch (TOOL VCC) when emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
switching) about details.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
PGA-299
MB90V820B MB90F822B MB90F823B MB90F828B MB90822B
MB90823B
X
X
X
X
X
FPT-80P-M21
FPT-80P-M22
FPT-80P-M06
X
X
X
: Available
X : Not available
Note: For more information about each package, refer to “■ PACKAGE DIMENSIONS”.
4
DS07-13751-2E
MB90820B Series
■ DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V820B does not have an internal ROM, however, operations equivalent to chips with an internal
ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of
the development tool.
• In the MB90V820B, images from FF8000H to FFFFFFH are mapped to bank 00, and FE0000H to FF7FFFH are
mapped to bank FE and bank FF only. (This setting can be changed by configuring the development tool.)
• In the MB90822B/F822B/F828B, images from FF8000H to FFFFFFH are mapped to bank 00, and FF0000H to
FF7FFFH are mapped to bank FF only. In the MB90823B/F823B/F828B, images from FF8000H to FFFFFFH
are mapped to bank 00, and FE0000H to FF7FFFH are mapped to bank FE and bank FF only.
Clock Supervisor Function
The clock supervisor is built-in in MB90F828B only. Note that the evaluation products and products actually used
are different when evaluating evaluation products. Please contact the sales representatives for more information
on evaluation of this function.
Modify ROM data
The registers include this function between 001FF0H and 001FF5H which overlap the RAM area of MB90F828B.
Do not access to the RAM when using this function in MB90F282B.
DS07-13751-2E
5
MB90820B Series
■ PIN ASSIGNMENT
(TOP VIEW)
AVR
AVcc
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
C
2
Vss
Vcc
AVss
3
P00 *
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P51/INT7
P50/PPG2
P47/PWO1
P46/PWI1
P45/SIN0
P44/SOT0
P43/SCK0
RST
4
P01 *
5
P02 *
6
P03 *
7
8
P04 *
P05 *
9
P06/PWI0 *
P07/PWO0 *
P10/INT0/DTTI
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
QFP-80
P42/TO0
P41/TIN0
Vss
P20/TIN1
P21/TO1
P22
Vcc
X0
P23
X1
(FPT-80P-M06)
* : High current pin.
(Continued)
6
DS07-13751-2E
MB90820B Series
(Continued)
(TOP VIEW)
AVss
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P51/INT7
P50/PPG2
P47/PWO1
P46/PWI1
P45/SIN0
P44/SOT0
P43/SCK0
RST
1
Vcc
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P00 *
2
P01 *
3
P02 *
4
P03 *
5
P04 *
6
7
P05 *
P06/PWI0 *
P07/PWO0 *
P10/INT0/DTTI
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17
8
9
10
11
12
13
14
15
16
17
18
19
20
LQFP-80
P20/TIN1
P21/TO1
P22
P42/TO0
P41/TIN0
Vss
(FPT-80P-M22)
(FPT-80P-M21)
* : High current pin.
DS07-13751-2E
7
MB90820B Series
■ PIN DESCRIPTION
Pin no.
Pin status
during
I/O
Pin name
Function
circuit *3
LQFP *1
QFP *2
reset
21, 22
23, 24
X0,X1
RST
A
B
C
Oscillating Oscillation pins.
Reset
17
19
External reset input pin.
input
59 to 54 61 to 56 P00 to P05
P06
General-purpose I/O ports.
General-purpose I/O port.
53
55
C
C
PWI0
P07
PWC ch.0 signal input pin.
General-purpose I/O port.
52
54
PWO0
P10
PWC ch.0 signal output pin.
General-purpose I/O port.
INT0
External interrupt request input ch.0 pin.
51
53
D
RTO0 to RTO5 pins for fixed-level input. This func-
tion is enabled when the waveform generator spec-
ifies its input bits.
DTTI
P11 to P16
INT1 to INT6
P17
General-purpose I/O ports.
50 to 45 52 to 47
D
D
D
External interrupt request input ch.1 to ch.6 pins.
General-purpose I/O port.
44
43
46
45
P20
General-purpose I/O port.
Port input
TIN1
External clock input pin for reload timer ch.1.
General-purpose I/O port.
P21
42
44
D
TO1
Event output pin for reload timer ch.1.
41,
43,
P22 to P27
D
E
General-purpose I/O ports.
39 to 35 41 to 37
34 to 28 36 to 30 P30 to P36
P37
General-purpose I/O ports.
General-purpose I/O port.
27
26
19
18
29
28
21
20
E
F
F
F
PPG0
P40
Output pin for PPG timer ch.0.
General-purpose I/O port.
PPG1
P41
Output pin for PPG timer ch.1.
General-purpose I/O port.
TIN0
P42
External clock input pin for reload timer ch.0.
General-purpose I/O port.
TO0
Event output pin for reload timer ch.0.
(Continued)
8
DS07-13751-2E
MB90820B Series
Pin no.
Pin status
during
I/O
Pin name
Function
circuit *3
LQFP *1
QFP *2
reset
P43
SCK0
P44
General-purpose I/O port.
16
15
18
F
F
G
F
F
F
F
H
Serial clock I/O pin for UART ch.0.
General-purpose I/O port.
17
16
SOT0
P45
Serial data output pin for UART ch.0.
General-purpose I/O port.
14
SIN0
Serial data input pin for UART ch.0.
General-purpose I/O port.
P46
13
15
Port Input
PWI1
P47
PWC ch.1 signal input pin.
General-purpose I/O port.
12
14
PWO1
P50
PWC ch.1 signal output pin.
General-purpose I/O port.
11
13
PPG2
P51
Output pin for PPG timer ch.2.
General-purpose I/O port.
10
12
INT7
External interrupt request input ch.7 pin.
General-purpose I/O ports.
P60 to P67
AN0 to AN7
P70, P71
DA0, DA1
AN8, AN9
P72
9 to 2
11 to 4
A/D converter analog input pins.
General-purpose I/O ports.
78, 77
76
80, 79
78
I
D/A converter analog output pins.
A/D converter analog input pins.
General-purpose I/O port.
SIN1
J
Serial data input pin for UART ch.1.
A/D converter analog input pin.
General-purpose I/O port.
AN10
P73
Analog
input
75
77
SOT1
AN11
P74
K
K
K
Serial data output pin for UART ch.1.
A/D converter analog input pin.
General-purpose I/O port.
74
76
SCK1
AN12
P75
Serial clock I/O pin for UART ch.1.
A/D converter analog input pin.
General-purpose I/O port.
73
75
FRCK
AN13
External clock input pin for free-run timer.
A/D converter analog input pin.
(Continued)
DS07-13751-2E
9
MB90820B Series
(Continued)
Pin no.
Pin status
during
I/O
Pin name
Function
General-purpose I/O ports.
circuit *3
LQFP *1
QFP *2
reset
P76, P77
IN0, IN1
Analog
input
72, 71
74, 73
K
Trigger input pins for input capture ch.0, ch.1.
A/D converter analog input pins.
AN14, AN15
P80, P81
IN2, IN3
General-purpose I/O ports.
70, 69
72, 71
F
L
Trigger input pins for input capture ch.2, ch.3.
General-purpose I/O ports.
Port input
P82 to P87
68 to 63 70 to 65
RTO0 (U) to
RTO5 (Z)
Waveform generator output pins. (U) to (Z) represent
the coils for controlling a 3-phase motor.
25
24, 23
80
27
26, 25
2
MD2
MD1, MD0
AVCC
M
N
Input pin for operation mode specification.
Input pins for operation mode specification.
Analog power supply pin.
Mode input
⎯
Vref + pin for the A/D converter.
Vref - is fixed to AVss internally.
79
1
AVR
⎯
1
3
AVSS
Vss
Vcc
⎯
⎯
⎯
Analog power supply (Ground) pin.
Power (Ground) pins.
Power pins.
⎯
20, 61
40, 60
22, 63
42, 62
Connect pin for smoothing capacitor to stabilize
internal power supply.
62
64
C
⎯
*1 : FPT-80P-M21,
FPT-80P-M22
*2 : FPT-80P-M06
*3 : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types.
10
DS07-13751-2E
MB90820B Series
■ I/O CIRCUIT TYPE
Classification
Type
Remarks
A
Oscillation feedback resistor :
approx. 1 MΩ
X1
Clock
input
P-ch
N-ch
X0
Standby control signal
B
C
• Hysteresis input
• Pull-up resistor : approx. 50 kΩ
R
• CMOS output
R
P-ch
• Hysteresis input
• Selectable pull-up resistor :
approx. 50 kΩ
Pull-up control
P-ch
Digital output
Digital output
• IOL = 12 mA
N-ch
Hysteresis input
Standby mode control
D
• CMOS output
R
P-ch
• Hysteresis input
• Selectable pull-up resistor :
approx. 50 kΩ
Pull-up control
P-ch
Digital output
Digital output
• IOL = 4 mA
N-ch
Hysteresis input
Standby mode control
E
• CMOS output
• CMOS input
R
P-ch
Pull-up control
• With pull-up control
• IOL = 4 mA
P-ch
Digital output
Digital output
N-ch
CMOS input
Standby mode control
(Continued)
DS07-13751-2E
11
MB90820B Series
Classification
Type
Remarks
• CMOS output
• Hysteresis input
• IOL = 4 mA
F
P-ch
Digital output
Digital output
N-ch
Hysteresis input
Standby mode control
G
• CMOS output
• Hysteresis input
• CMOS input (selectable for
UART ch.0 data input pin)
• IOL = 4 mA
P-ch
Digital output
Digital output
N-ch
Hysteresis input
CMOS input
Standby mode control
H
• CMOS output
• CMOS input
• Analog input
• IOL = 4 mA
P-ch
Digital output
Digital output
N-ch
CMOS input
Analog input control
Analog input
I
• CMOS output
• Hysteresis input
• Analog output
• Analog input
• IOL = 4 mA
P-ch
Digital output
Digital output
N-ch
Hysteresis input
Analog I/O control
Analog output
Analog input
(Continued)
12
DS07-13751-2E
MB90820B Series
(Continued)
Classification
Type
Remarks
J
• CMOS output
• Hysteresis input
• CMOS input (selectable for
UART ch.1 data input pin)
• IOL = 4 mA
P-ch
N-ch
Digital output
Digital output
Hysteresis input
CMOS input
Analog input control
Analog input
K
• CMOS output
• Hysteresis input
• Analog input
• IOL = 4 mA
P-ch
N-ch
Digital output
Digital output
Hysteresis input
Analog input control
Analog input
L
• CMOS output
• Hysteresis input
• IOL = 12 mA
P-ch
N-ch
Digital output
Digital output
Hysteresis input
Standby mode control
M
MASK ROM / evaluation product
• Hysteresis input
• Pull-down resistor :
approx. 50 kΩ
Flash memory product
• CMOS input
R
• No pull-down resistor
N
MASK ROM / evaluation product
• Hysteresis input
Flash memory product
• CMOS input
DS07-13751-2E
13
MB90820B Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Stabilization of supply voltage
• Treatment of unused pins
• Using external clock
• Power supply pins (VCC /VSS )
• Pull-up/pull-down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on turning the power on
• Notes on During Operation of PLL Clock Mode
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
In using the devices, take sufficient care to avoid exceeding maximum ratings.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital
power-supply voltage.
2. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operation range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at
commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of
fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
3. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
4. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90820B series
X0
Open
X1
14
DS07-13751-2E
MB90820B Series
5. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS pins to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS pins in the vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
MB90820B
Series
VCC
VCC
VSS
VCC
VSS
6. Pull-up/pull-down resistors
The MB90820B series does not support internal pull-up/pull-down resistors option (Port 0 to Port 3 : built-in pull-
up resistors) . Use external components where needed.
7. Crystal oscillator circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits while you
design a printed circuit board.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
8. Turning-on sequence of power supply to A/D converter and D/A converter, and analog
inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVR) and
analog inputs (AN0 to AN15) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter power supply, D/A converter power supply, and
analog inputs. In this case, make sure that the voltage not exceed AVR or AVCC (turning on/off the analog and
digital power supplies simultaneously is acceptable).
9. Pin connections when A/D converter and D/A converter are unused
When the A/D converter and D/A converter are not used, connect AVCC = VCC, AVSS = AVRH = AVRL = VSS.
DS07-13751-2E
15
MB90820B Series
10. Notes on turning the power on
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power on at 50 µs
or more (0.2 V to 2.7 V) .
11. Notes on During Operation of PLL Clock Mode
If the PLL clock mode is selected, the microcontroller may continue to operate at the free-running frequency of
the self-oscillating circuit within the PLL even if the external oscillator is disconnected or external clock input is
stopped. Performance of this operation, however, cannot be guaranteed.
12. Internal CR Oscillation Circuit
Rating
Parameter
Symbol
Unit
Min
50
Typ
100
⎯
Max
200
100
Oscillation frequency
Oscillation stabilization waiting time
fRC
kHz
tstab
⎯
µs
16
DS07-13751-2E
MB90820B Series
■ SECTOR CONFIGURATION OF FLASH MEMORY
The flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper
and lower addresses of each sector.
When 512K bits flash memory is accessed from the CPU, SA0 to SA3 are allocated in the FF bank.
CPU address
FFFFFFH
Flash memory
*Writer address
7FFFFH
SA3 (16K bytes)
FFC000H
FFBFFFH
7C000H
7BFFFH
SA2 (8K bytes)
SA1 (8K bytes)
SA0 (32K bytes)
FFA000H
FF9FFFH
7A000H
79FFFH
FF8000H
FF7FFFH
FF0000H
78000H
77FFFH
70000H
When 1024K bits flash memory is accessed from the CPU, SA0 to SA4 are allocated in the FE and FF bank.
CPU address
FFFFFFH
Flash memory
*Writer address
7FFFFH
SA4 (16K bytes)
FFC000H
FFBFFFH
7C000H
7BFFFH
SA3 (8K bytes)
SA2 (8K bytes)
SA1 (32K bytes)
SA0 (64K bytes)
FFA000H
FF9FFFH
7A000H
79FFFH
FF8000H
FF7FFFH
78000H
77FFFH
FF0000H
FEFFFFH
70000H
6FFFFH
FE0000H
60000H
* : The writer address is the address corresponding to the CPU address when writing data from a parallel flash
memory writer. Use the writer address when programming or erasing using a general-purpose parallel writer.
DS07-13751-2E
17
MB90820B Series
■ BLOCK DIAGRAM
CR oscillation
circuit *1
Other pins
SS × 2, VCC × 2, MD0 to MD2, C
CPU
X0
V
Clock control circuit,
F2MC-16LX core
monitor circuit *1
X1
Time-base timer
Reset circuit
(Watchdog timer)
RST
Delayed interrupt generator
Interrupt controller
7
4
P30 to P36
P37/PPG0
Multi-functional timer
8
DTP/External
P51/INT7
16-bit PPG timer
interrupt
(ch.0)
P16/INT6 to
P11/INT1
6
P76/IN0/AN14
P77/IN1/AN15
P80/IN2
16-bit input capture
(ch.0 to ch.3)
4
P45/SIN0
P44/SOT0
P43/SCK0
UART
(ch.0)
P81/IN3
16-bit free-run
P75/FRCK/AN13
P72/SIN1/AN10
P73/SOT1/AN11
P74/SCK1/AN12
timer
UART
(ch.1)
P82/RTO0 (U) *2
P83/RTO1 (X) *2
P84/RTO2 (V) *2
P85/RTO3 (Y) *2
P86/RTO4 (W) *2
P87/RTO5 (Z) *2
16-bit output
compare
(ch.0 to ch.5)
16-bit PPG
P40/PPG1
P50/PPG2
(ch.1)
Waveform
generator
16-bit PPG
P10/INT0/DTTI
P17
(ch.2)
P06/PWI0 *2
P07/PWO0 *2
PWC
(ch.1)
P46/PWI1
P47/PWO1
PWC
(ch.0)
6
P00 to P05 *2
CMOS I/O port 0, 1, 3, 7, 8
CMOS I/O port 6
16-bit reload timer
P42/TO0
P41/TIN0
(ch.0)
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVR
16-bit reload timer
P21/TO1
P20/TIN1
(ch.1)
A/D converter
16
6
(8/10-bit)
P22 to P27
CMOS I/O port 1, 2, 4, 5, 7
RAM
ROM
AVCSCS
AV
P70/DA0/AN8
8-bit D/A converter
CMOS I/O port 7
P71/DA1/AN9
ROM correction
ROM mirroring
Note : P00 to P07, P10 to P17, P20 to P27 and P30 to P37: With build-in resistors that can be used
as input pull-up resistors.
*1 : MB90F828B
*2 : High current drive pin.
18
DS07-13751-2E
MB90820B Series
■ MEMORY MAP
FFFFFFH
ROM area
Address #1
Address #1 - 1H
010000H
00FFFFH
ROM area*
(FF bank image)
Address #2
: Internal access memory
: Access not allowed
Address #2 - 1H
Address #3 + 1H
Address #3
000100H
RAM
Register
area
0000FFH
0000F0H
0000EFH
000000H
Peripheral area
* : In Single chip mode, the mirror function is supported.
Parts no.
MB90822B
MB90823B
MB90F822B
MB90F823B
MB90F828B
MB90V820B
Address#1
FF0000H
FE0000H
FF0000H
FE0000H
FE0000H
(FE0000H)
Address#2
008000H
008000H
008000H
008000H
008000H
008000H
Address#3
0010FFH
0010FFH
0010FFH
0010FFH
0020FFH
0040FFH
Note: The ROM data of bank FF is reflected to the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on
the ROM without stating “far”. For example, if an attempt has been made to access 00C000H, the contents
of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 32 K bytes, the
whole area cannot be reflected in the image for the 00 bank. The ROM data at FF8000H to FFFFFFH looks,
therefore, as if it were the image for 008000H to 00FFFFH. Thus, it is recommended that the ROM data table
be stored in the area of FF8000H to FFFFFFH.
DS07-13751-2E
19
MB90820B Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
: Accumulator (A)
AH
AL
Dual 16-bit register used for storing results of calculation
etc. The two 16-bit registers can be combined to be used as
a sequence of 32-bit register.
: User stack pointer (USP)
The 16-bit pointer indicating the user stack address.
USP
SSP
: System stack pointer (SSP)
The 16-bit pointer indicating the system stack address.
: Processor status (PS)
The 16-bit register indicating the system status.
PS
PC
: Program counter (PC)
The 16-bit register indicating storing location of the current
instruction code.
: Direct page register (DPR)
DPR
The 8-bit register indicating bit 8 through 15 of the operand
address in executing of the short direct addressing.
: Program bank register (PCB)
The 8-bit register indicating the program space.
PCB
DTB
USB
SSB
: Data bank register (DTB)
The 8-bit register indicating the data space.
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
: Additional data bank register (ADB)
The 8-bit register indicating the additional space.
ADB
8-bit
16-bit
32-bit
20
DS07-13751-2E
MB90820B Series
• General-purpose registers
Maximum of 32 banks
R7
R5
R3
R1
R6
R4
R2
R0
RW7
RW6
RW5
RW4
RL3
RL2
RL1
RL0
RW3
RW2
RW1
RW0
000180H + (RP × 10H)
16-bit
• Processor status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PS
ILM2 ILM1 ILM0 B4
B3
B2
0
B1
0
B0
0
I
S
T
X
N
X
Z
X
V
X
C
X
Initial value
0
0
0
0
0
0
1
: Unused
X
: Undefined
DS07-13751-2E
21
MB90820B Series
■ I/O MAP
Byte
Word
Initial
value
Address
Abbreviation
Register
Resource name
access access
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
000009H
to
Prohibited area
00000FH
000010H
000011H
000012H
000013H
000014H
000015H
000016H
000017H
000018H
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
Port 0 data direction register
Port 1 data direction register
Port 2 data direction register
Port 3 data direction register
Port 4 data direction register
Port 5 data direction register
Port 6 data direction register
Port 7 data direction register
Port 8 data direction register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
00000000B
00000000B
00000000B
00000000B
00000000B
XXXXXX00B
00000000B
00000000B
00000000B
000019H
to
00001FH
Prohibited area
R/W
000020H
000021H
SMR0
SCR0
Serial mode register ch.0
Serial control register ch.0
R/W
00000000B
00000100B
W, R/W W, R/W
UART ch.0
UART ch.1
SIDR0 /
SODR0
Serial input data register ch.0 /
Serial output data register ch.0
000022H
R/W
R/W
XXXXXXXXB
000023H
000024H
000025H
SSR0
SMR1
SCR1
Serial status register ch.0
Serial mode register ch.1
Serial control register ch.1
R, R/W R, R/W
R/W R/W
W, R/W W, R/W
00001000B
00000000B
00000100B
SIDR1 /
SODR1
Serial input data register ch.1 /
Serial output data register ch.1
000026H
000027H
R/W
R/W
XXXXXXXXB
SSR1
Serial status register ch.1
R, R/W R, R/W
00001000B
(Continued)
22
DS07-13751-2E
MB90820B Series
Byte
Word
Initial
value
Address Abbreviation
Register
Resource name
access access
000028H
000029H
00002AH
00002BH
00002CH
PWCSL1
PWCSH1
R/W
R/W
00000000B
00000000B
PWC control status register ch.1
R, R/W R, R/W
PWC timer ch.1 XXXXXXXXB
XXXXXXXXB
PWC1
DIV1
PWC data buffer register ch.1
Divide ratio control register ch.1
⎯
R/W
R/W
R/W
XXXXXX00B
00002DH,
00002EH
Prohibited area
W
00002FH
000030H
000031H
PCKCR
ENIR
PLL clock control register
W
PLL
XXXX0000B
00000000B
XXXXXXXXB
DTP / Interrupt enable register
DTP / Interrupt cause register
R/W
R/W
R/W
R/W
EIRR
DTP/
Request level setting register
(lower byte)
external interrupt
ch.0 to ch.7
000032H
ELVRL
ELVRH
R/W
R/W
R/W
R/W
00000000B
00000000B
Request level setting register
(higher byte)
000033H
000034H
000035H
000036H
000037H
Prohibited area
Clock division ratio control register
ch.0
Communication
prescaler ch.0
CDCR0
R/W
R/W
00XXX000B
00XXX000B
Prohibited area
Clock division ratio control register
ch.1
Communication
prescaler ch.1
CDCR1
PDCR0
R/W
R/W
R
000038H
000039H
00003AH
00003BH
00003CH
00003DH
00003EH
00003FH
000040H
000041H
000042H
000043H
000044H
000045H
000046H
000047H
11111111B
11111111B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XX000000B
00000000B
11111111B
11111111B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XX000000B
00000000B
(Continued)
PPG down counter register ch.0
PPG cycle setting register ch.0
PPG duty setting register ch.0
PPG control status register ch.0
PPG down counter register ch.1
PPG cycle setting register ch.1
PPG duty setting register ch.1
PPG control status register ch.1
⎯
PCSR0
PDUT0
⎯
⎯
W
W
16-bit PPG timer
ch.0
PCNTL0
PCNTH0
R/W
R/W
R/W
R/W
PDCR1
PCSR1
PDUT1
⎯
⎯
⎯
R
W
W
16-bit PPG timer
ch.1
PCNTL1
PCNTH1
R/W
R/W
R/W
R/W
DS07-13751-2E
23
MB90820B Series
Byte
Word
Initial
value
Address Abbreviation
Register
Resource name
access access
000048H
PDCR2
000049H
11111111B
11111111B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XX000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
PPG down counter register
ch.2
⎯
⎯
⎯
R
W
W
00004AH
PCSR2
PPG cycle setting register ch.2
PPG duty setting register ch.2
00004BH
16-bit PPG timer
ch.2
00004CH
PDUT2
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
PCNTL2
PCNTH2
R/W
R/W
R/W
R/W
PPG control status register
ch.2
TMRR0
TMRR1
TMRR2
16-bit timer register ch.0
16-bit timer register ch.1
16-bit timer register ch.2
⎯
⎯
⎯
R/W
R/W
R/W
Waveform generator
16-bit timer control register
ch.0
000056H
000057H
000058H
DTCR0
DTCR1
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
16-bit timer control register
ch.1
16-bit timer control register
ch.2
DTCR2
SIGCR
R/W
R/W
R/W
R/W
000059H
00005AH
00005BH
00005CH
00005DH
Waveform control register
00000000B
11111111B
11111111B
00000000B
00000000B
CPCLRB / Compare clear buffer register/
CPCLR
⎯
⎯
R/W
R/W
Compare clear register
TCDT
Timer data register
16-bit free-run timer
Timer control status register
(lower)
00005EH
00005FH
TCCSL
TCCSH
R/W
R/W
R/W
R/W
X0100000B
00000000B
Timer control status register
(upper)
000060H
000061H
000062H
000063H
000064H
000065H
000066H
000067H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
IPCP0
IPCP1
IPCP2
IPCP3
Input capture data register ch.0
Input capture data register ch.1
Input capture data register ch.2
Input capture data register ch.3
⎯
⎯
⎯
⎯
R
R
R
R
16-bit input capture
(ch.0 to ch.3)
24
DS07-13751-2E
MB90820B Series
Byte
Word
Initial
value
Address Abbreviation
Register
Resource name
access access
Input capture control status
register ch.0,ch.1 (lower)
000068H
000069H
PICSL01
PICSH01
R/W
R/W
00000000B
00000000B
PPG output control / Input
capture control status register R, R/W R, R/W
ch.0,ch.1 (upper)
16-bit input capture
(ch.0 to ch.3)
Input capture control status
register ch.2,ch.3 (lower)
00006AH
00006BH
ICSL23
ICSH23
R/W
R
R/W
R
00000000B
XXXXXX00B
Input capture control status
register ch.2,ch.3 (upper)
00006CH
to
00006EH
Prohibited area
W
ROM mirroring function
selection register
ROM mirroring
function
00006FH
ROMM
W
XXXXXXX1B
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
000081H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00001100B
X1100000B
00001100B
X1100000B
00001100B
X1100000B
OCCPB0 / Output compare buffer register /
OCCP0 Output compare register ch.0
⎯
⎯
⎯
⎯
⎯
⎯
R/W
OCCPB1 / Output compare buffer register /
OCCP1 Output compare register ch.1
R/W
R/W
R/W
R/W
R/W
OCCPB2 / Output compare buffer register /
OCCP2 Output compare register ch.2
OCCPB3 / Output compare buffer register /
OCCP3 Output compare register ch.3
OCCPB4 / Output compare buffer register /
OCCP4 Output compare register ch.4
Output compare
(ch.0 to ch.5)
OCCPB5 / Output compare buffer register /
OCCP5
Output compare register ch.5
OCS0
OCS1
OCS2
OCS3
OCS4
OCS5
Compare control register ch.0
Compare control register ch.1
Compare control register ch.2
Compare control register ch.3
Compare control register ch.4
Compare control register ch.5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer control status register
ch.0 (lower)
000082H
000083H
TMCSRL0
TMCSRH0
R/W
R/W
R/W
R/W
00000000B
XXX10000B
Timer control status register
ch.0 (upper)
16-bit reload timer
(ch.0)
000084H
000085H
XXXXXXXXB
XXXXXXXXB
TMR0 /
TMRD0
16 bit timer register ch.0 /
16-bit reload register ch.0
⎯
R/W
R/W
Timer control status register
ch.1 (lower)
16-bit reload timer
(ch.1)
000086H
TMCSRL1
R/W
00000000B
(Continued)
DS07-13751-2E
25
MB90820B Series
Abbrevia-
Byte
Word
Initial
value
Address
tion
Register
Resource name
access access
Timer control status register
ch.1 (upper)
000087H
TMCSRH1
R/W
R/W
R/W
⎯
XXX10000B
16-bit reload timer
(ch.1)
000088H
000089H
XXXXXXXXB
XXXXXXXXB
TMR1 /
TMRD1
16 bit timer register ch.1 /
16-bit reload register ch.1
⎯
Clock supervisor control
register*
00008AH
00008BH
00008CH
CSVCR
R, R/W
Prohibited area
R/W
Clock supervisor 00011100B
Port 0 pull-up resistor setting
register
RDR0
RDR1
RDR2
RDR3
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
00000000B
00000000B
00000000B
00000000B
Port 1 pull-up resistor setting
register
00008DH
00008EH
00008FH
R/W
R/W
R/W
Port 2 pull-up resistor setting
register
Port 3 pull-up resistor setting
register
000090H
to
Prohibited area
00009DH
Program address detection
control status register
Address match
detection
00009EH
00009FH
PACSR
DIRR
R/W
R/W
R/W
R/W
XXXX0000B
Delayed interrupt cause /
clear register
Delayed interrupt XXXXXXX0B
Low-power consumption mode
control register
Low-power
consumption
control register
0000A0H
0000A1H
LPMCR
CKSCR
W, R/W W, R/W
R, R/W R, R/W
00011000B
Clock selection register
11111100B
0000A2H
to
Prohibited area
0000A7H
0000A8H
0000A9H
WDTC
TBTC
Watchdog timer control register R, W
R, W
Watchdog timer XXXXX111B
Time-base timer control register W, R/W W, R/W Time-base timer 1XX00100B
0000AAH
to
Prohibited area
0000ADH
Flash memory control status
register
Flash memory
interface circuit
0000AEH
0000AFH
FMCS
R, R/W R, R/W
Prohibited area
000X0000B
(Continued)
26
DS07-13751-2E
MB90820B Series
Byte
Word
Initial
Resource name
value
Address Abbreviation
Register
access access
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
0000C0H
0000C1H
0000C2H
0000C3H
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
PWCSL0
PWCSH0
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
Interrupt
controller
Interrupt
controller
PWC control status register
ch.0
R, R/W R, R/W
PWC data buffer register
ch.0
PWC timer (ch.0)
Port 6, A/D
PWC0
DIV0
⎯
R/W
R/W
Divide ratio control register
ch.0
0000C4H
R/W
XXXXXX00B
0000C5H
0000C6H
0000C7H
0000C8H
0000C9H
0000CAH
0000CBH
0000CCH
0000CDH
0000CEH
0000CFH
0000D0H
ADER0
ADCS0
ADCS1
ADCR0
ADCR1
ADSR0
ADSR1
DAT0
A/D input enable register 0
A/D control status register 0
R/W
R/W
R/W
R/W
11111111B
000XXXX0B
0000000XB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXX0B
XXXXXXX0B
11111111B
A/D control status register 1 W, R/W W, R/W
A/D data register 0
R
R
8/10-bit A/D converter
A/D data register 1
R
R
A/D setting register 0
A/D setting register 1
D/A data register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DAT1
D/A data register 1
8-bit D/A converter
Port 7, A/D
DACR0
DACR1
ADER1
D/A control register 0
D/A control register 1
A/D input enable register 1
0000D1H
to
Prohibited area
0000EFH
(Continued)
DS07-13751-2E
27
MB90820B Series
(Continued)
Abbrevia-
Byte
Word
Initial
value
Address
Register
Resource name
tion
access access
0000F0H
to
External area
0000FFH
Program address detection
register 0 (lower)
001FF0H
001FF1H
001FF2H
001FF3H
001FF4H
001FF5H
PADRL0
PADRM0
PADRH0
PADRL1
PADRM1
PADRH1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address match
detection
Program address detection
register 0 (middle)
Program address detection
register 0 (higher)
Program address detection
register 1 (lower)
Address match
detection
Program address detection
register 1 (middle)
Program address detection
register 1 (higher)
* : For MB90F828B only. Prohibited for the other products.
• Meaning of abbreviations used for reading and writing
R/W: Read and write enabled
R
W
: Read-only
: Write-only
• Explanation of initial values
0
1
X
: The bit is initialized to “0”.
: The bit is initialized to “1”.
: The initial value of the bit is undefined.
28
DS07-13751-2E
MB90820B Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
EI2OS
support
Interrupt vector
Number Address
register
Interrupt cause
Priority
ICR
⎯
⎯
Address
High
Reset
#08
#09
#10
#11
#12
08H
09H
0AH
0BH
0CH
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
⎯
⎯
⎯
INT9 instruction
Exception processing
⎯
A/D converter conversion complete
Output compare ch.0 match
ICR00
0000B0H
End of measurement by PWC timer ch.0 /
PWC timer ch.0 overflow
#13
0DH
FFFFC8H
ICR01
0000B1H
16-bit PPG timer ch.0
#14
#15
#16
#17
#18
#19
0EH
0FH
10H
11H
12H
13H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
Output compare ch.1 match
16-bit PPG timer ch.1
ICR02
ICR03
0000B2H
0000B3H
Output compare ch.2 match
16-bit reload timer ch.1 underflow
Output compare ch.3 match
DTP/ext. interrupt ch.0/ch.1 detection
DTTI
ICR04
ICR05
ICR06
0000B4H
0000B5H
0000B6H
#20
14H
FFFFACH
Output compare ch.4 match
DTP/ext. interrupt ch.2/ch.3 detection
Output compare ch.5 match
#21
#22
#23
15H
16H
17H
FFFFA8H
FFFFA4H
FFFFA0H
End of measurement by PWC timer ch.1 /
PWC timer ch.1 overflow
#24
18H
FFFF9CH
DTP/ext. interrupt ch.4 detection
DTP/ext. interrupt ch.5 detection
DTP/ext. interrupt ch.6 detection
DTP/ext. interrupt ch.7 detection
#25
#26
#27
#28
19H
1AH
1BH
1CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
ICR07
ICR08
0000B7H
0000B8H
Waveform generator 16-bit timers ch.0/
ch.1/ch.2 underflow
#29
1DH
FFFF88H
ICR09
0000B9H
16-bit reload timer ch.0 underflow
16-bit free-run timer zero detect
16-bit PPG timer ch.2
#30
#31
#32
#33
#34
#35
#36
#37
#38
#39
#40
#41
#42
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
Input capture ch.0/ch.1
16-bit free-run timer compare clear
Input capture ch.2/ch.3
Time-base timer
UART ch.1 receive
UART ch.1 send
UART ch.0 receive
UART ch.0 send
Flash memory status
Low
Delayed interrupt generator module
: Can be used and support the EI2OS stop request.
: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
: Cannot be used.
: Usable when an interrupt cause that shares the ICR is not used.
DS07-13751-2E
29
MB90820B Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Max
Symbol
Unit
Remarks
Parameter
Min
VCC
AVCC
AVR
VI
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
Power supply voltage*1
VCC = AVCC *2
V
AVCC ≥ AVR, AVR ≥ AVss
Input voltage*1
Output voltage*1
V
*3
*3
*5
*5
VO
V
Maximum clamp current
Total maximum clamp current
ICLAMP
Σ | ICLAMP |
− 2.0
+ 2.0
20
mA
mA
⎯
“L” level maximum output
current
IOL
⎯
15
mA
*4
IOLAV1
IOLAV2
⎯
⎯
4
mA
mA
Except for P00 to P07, P82 to P87
P00 to P07, P82 to P87
“L” level average output current
12
“L” level total maximum output
current
ΣIOL
⎯
⎯
100
50
mA
mA
“L” level total average
output current
ΣIOLAV
“H” level maximum output
current
IOH
⎯
⎯
⎯
−15
−4
mA
mA
mA
*4
“H” level average output current
IOHAV
ΣIOH
“H” level total maximum output
current
−100
“H” level total average
output current
ΣIOHAV
⎯
−50
mA
Power consumption
Operating temperature
Storage temperature
PD
TA
⎯
430
+85
mW
°C
−40
−55
Tstg
+150
°C
*1 : This parameter is based on VSS = AVSS = 0.0 V.
*2 : AVCC must never exceed VCC when the power is turned on.
*3 : VI and VO must never exceed VCC + 0.3 V. However if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*4 : The maximum output current is a peak value for a corresponding pin.
(Continued)
30
DS07-13751-2E
MB90820B Series
(Continued)
*5 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50, P51, P80 to P87.
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The +B signal is an input signal exceeding VCC voltage. The +B signal should always be applied a limiting
resistance placed between the +B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins (LCD drive pins and comparator input pins, etc.) other than the
A/D input pins cannot accept +B input.
• Sample recommended circuits:
Input/output equivalent circuits
Protective diode
Vcc
P-ch
Limiting
resistance
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-13751-2E
31
MB90820B Series
2. Recommended Operating Conditions
Sym-
(VSS = AVSS = 0.0 V)
Value
Condi-
tion
Pin name
Unit
Remarks
Parameter
bol
Min
Max
At normal operation
TA = −40 °C to +85 °C
⎯
⎯
⎯
4.5
5.5
V
Normal operation when
D/A converter is not used
TA = −40 °C to +85 °C
⎯
⎯
4.0
5.5
V
V
Power
supply
voltage
VCC
AVCC
Normal operation when
A/D converter and D/A
converter are not used
TA = −40 °C to +85 °C
⎯
⎯
3.5
3.0
5.5
5.5
Maintains state in stop
mode
⎯
V
V
VIH
P30 to P37, P60 to P67
0.7 VCC VCC + 0.3
CMOS input
P00 to P07, P10 to P17,
P20 to P27, P40 to P44,
P45*1, P46, P47, P50,
P51, P70, P71, P72*1,
P73 to P77, P80 to P87,
RST
“H” level
input voltage
VIHS
0.8 VCC VCC + 0.3
V
CMOS hysteresis input
VIHM
VIL
MD0, MD1, MD2
VCC − 0.3 VCC + 0.3
VSS − 0.3 0.3 VCC
V
V
MD input
VCC =5V
10%
P30 to P37, P60 to P67
CMOS input
P00 to P07, P10 to P17,
P20 to P27, P40 to P44,
P45*1, P46, P47, P50,
P51, P70, P71, P72*1,
P73 to P77, P80 to P87,
RST
“L” level
input voltage
VILS
VSS − 0.3 0.2 VCC
V
CMOS hysteresis input
VILM
CS
MD0, MD1, MD2
VSS − 0.3 VSS + 0.3
V
MD input
Smoothing
capacitor
⎯
⎯
⎯
⎯
0.1
2.7
−40
1.0
AVCC
+85
µF *2
Reference
input voltage
of A/D
AVR
TA
⎯
⎯
V
converter
Operating
temperature
°C
*1 : UART ch.0/ch.1 data input pins P45/SIN0, P72/SIN1/AN10 can be used as CMOS input by the communication
prescaler control register (CDRR).
*2 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. On the VCC pin, connect a
bypass capacitor that has a larger capacity than that of CS. Refer to the following figure for connection of
smoothing capacitor CS.
(Continued)
32
DS07-13751-2E
MB90820B Series
(Continued)
• C pin connection circuit
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13751-2E
33
MB90820B Series
3. DC Characteristics
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Typ
Max
“H” level output
VOH
VCC = 4.5 V,
IOH = −4.0 mA
All output pins
VCC − 0.5
⎯
⎯
V
voltage
All pins except
P00 to P07
P82 to P87
VCC = 4.5 V,
IOL1 = 4.0 mA
VOL1
⎯
⎯
0.4
V
“L” level output
voltage
P00 to P07
P82 to P87
VCC = 4.5 V,
IOL2 = 12.0 mA
VCC = 5.5 V,
VSS < VI< VCC
VOL2
⎯
⎯
⎯
0.4
V
Input leakage
IIL
At pull-up
disabled
All input pins
−5
+ 5
µA
current
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
Pull-up
RUP
MASK ROM
product
⎯
⎯
25
25
50
50
100
100
kΩ
kΩ
resistance
Pull-down
resistance
MASK ROM
product
RDOWN MD2
(Continued)
34
DS07-13751-2E
MB90820B Series
(Continued)
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Typ Max
VCC = 5.0 V,
⎯
35
50
mA MASK ROM product
Internal frequency:
24 MHz,
At normal operation
Flash memory prod-
⎯
⎯
45
60
mA
uct
VCC = 5.0 V,
Internal frequency:
24 MHz,
At writing in flash
memory
Flash memory prod-
ICC
60
75
mA
uct
VCC = 5.0 V,
Internal frequency:
24 MHz,
Flash memory prod-
⎯
65
15
80
25
mA
uct
At erasing memory
VCC = 5.0 V,
Internal frequency:
24 MHz,
⎯
⎯
⎯
⎯
⎯
mA MASK ROM product
Power supply
current*
VCC
ICCS
Flash memory prod-
mA
uct
At sleep mode
VCC = 5.0 V,
Internal frequency:
2 MHz,
mA MASK ROM product
ICTS
0.3
0.8
Flash memory prod-
mA
uct
At main timer mode
VCC = 5.0 V,
Internal frequency:
8 MHz,
At timer mode,
TA = +25 °C
mA MASK ROM product
ICCT
3
7
Flash memory prod-
⎯
mA
uct
⎯
⎯
µA MASK ROM product
In stop mode,
TA = +25 °C
ICCH
5
5
20
15
Flash memory prod-
mA
uct
Except AVCC,
AVSS, AVR, C,
VCC and VSS
Input
capacitance
CIN
⎯
⎯
pF
* : The power supply current is regulated with an external clock.
DS07-13751-2E
35
MB90820B Series
4. AC Characteristics
(1) Clock Timings
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol Pin name
Unit
Remarks
Min
Typ
Max
When using
oscillation circuit
3
⎯
16
When using external
clock
3
⎯
24
4
4
4
4
4
⎯
⎯
⎯
⎯
⎯
24
12
8
1 multiplied PLL
2 multiplied PLL
3 multiplied PLL
4 multiplied PLL
6 multiplied PLL
Clock frequency
FC
X0, X1
MHz
6
4
When using
oscillation circuit
62.5
⎯
⎯
333
333
ns
ns
Clock cycle time
tHCYL
X0, X1
When using external
clock
41.67
When using external
ns clock, duty ratio is
about 30% to 70%.
PWH,
PWL
Input clock pulse width
Input clock rise/fall time
X0
X0
10
⎯
⎯
⎯
tCR
tCF
When using external
clock
⎯
5
ns
Internal operating clock frequency
Internal operating clock cycle time
fCP
tCP
⎯
⎯
1.5
⎯
⎯
24
MHz
ns
41.67
666
t
HCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
t
CF
tCR
36
DS07-13751-2E
MB90820B Series
Relationship between internal operating clock frequency and power supply voltage
Guaranteed D/A Converter operating range
5.5
4.5
4.0
Operation guarantee range of PLL
Guaranteed A/D Converter
operating range
3.5
Normal operation guarantee range
1.5 4
24
Internal operating clock frequency fCp (MHz)
Relationship between clock frequency and internal operating clock frequency
X6
X2
X4
X3
X1
24
16
12
8
Not multiplied
4
1.5
3 4
12
Clock frequency FC (MHz)
16
8
24
The AC ratings are measured for the following measurement reference voltages
• Input signal waveform
Hysteresis input pin
• Output signal waveform
Output pin
0.8 VCC
0.2 VCC
2.4 V
0.8 V
Pins other than hysteresis input/MD input
0.7 VCC
0.3 VCC
DS07-13751-2E
37
MB90820B Series
(2) External Reset
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Unit
Remarks
Parameter
Min
Max
500
⎯
ns In normal operation
µs In stop mode
Oscillation time of
oscillator* + 100
Reset input time
tRSTL
RST
⎯
⎯
100
µs In time-base timer mode
* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal
oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation time is
between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
• In normal operation mode
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, at power on
tRSTL
RST
0.2 VCC
0.2 VCC
90% of the oscillation amplitude
X0
Internal
operation
clock
Oscillation time of
oscillator
100 µs
Oscillator stabilization time
Instruction
execution
Internal reset
38
DS07-13751-2E
MB90820B Series
(3) Power-on Reset
Parameter
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit
Remarks
Min
Max
Power supply rising time
Power supply cut-off time
tR
VCC
VCC
0.05
30
ms
ms
⎯
Waiting time for power
supply on
tOFF
1
⎯
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Note : Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, be sure to set the slope of rising within
50 mV/ms or less as shown below.
VCC
Be sure to set the slope of rising
within 50 mV/ms or less.
3.0 V
RAM data hold time
VSS
DS07-13751-2E
39
MB90820B Series
(4) UART
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit
Parameter
Min
Max
Serial clock cycle time
tSCYC
tSLOV
tIVSH
tSHIX
SCK0 to SCK1
8 tCP
⎯
ns
ns
SCK0 to SCK1
SOT0 to SOT1
SCK ↓ → SOT delay time
−80
100
60
+ 80
⎯
CL = 80 pF + 1 TTL
for an output pin of
internal shift clock
mode
SCK0 to SCK1
SIN0 to SIN1
Valid SIN → SCK ↑
ns
ns
SCK0 to SCK1
SIN0 to SIN1
SCK ↑ → valid SIN hold time
⎯
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK0 to SCK1
SCK0 to SCK1
4 tCP
⎯
⎯
ns
ns
4 tCP
SCK0 to SCK1
SOT0 to SOT1
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOV
tIVSH
tSHIX
CL = 80 pF + 1 TTL
for an output pin of ex-
ternal shift clock mode
⎯
60
60
150
⎯
ns
ns
ns
SCK0 to SCK1
SIN0 to SIN1
SCK0 to SCK1
SIN0 to SIN1
SCK ↑ → valid SIN hold time
⎯
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitance value connected to pins while testing.
• tCP is machine cycle time (unit : ns).
40
DS07-13751-2E
MB90820B Series
• Internal shift clock mode
SCK
tSCYC
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External shift clock mode
SCK
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
0.2 VCC
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
DS07-13751-2E
41
MB90820B Series
(5) Resources Input Timing
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit
Parameter
Min
Max
IN0 to IN3,
tTIWH
tTIWL
TIN0 to TIN1,
PWI0 to PWI1,
DTTI
Input pulse width
⎯
4 tCP
⎯
ns
IN0 to IN3,
0.8 VCC
0.8 VCC
0.2 VCC
TIN0 to TIN1,
PWI0 to PWI1,
DTTI
0.2 VCC
tTIWH
tTIWL
(6) Trigger Input Timing
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit
Parameter
Min
Max
tTRGH
tTRGL
Input pulse width
INT0 to INT7
⎯
5 tCP
⎯
ns
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
INT0 to INT7
tTRGH
tTRGL
42
DS07-13751-2E
MB90820B Series
5. A/D Converter Electrical Characteristics
(3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Typ
10
Pin
name
Condi-
tion
Symbol
Unit
Remarks
Parameter
Resolution
Min
⎯
⎯
Max
⎯
3.0
2.5
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
LSB
LSB
Non-linearity error
⎯
Differentiallinearity
error
⎯
⎯
⎯
⎯
1.9
LSB
V
Zero transition
voltage
AN0 to
AN15
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
VOT
VFST
Full-scale
transition voltage
AN0 to
AN15
AVR −
3.5 LSB
AVR −
1.5 LSB
AVR +
0.5 LSB
V
1.0
2.0
0.5
1.2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
µs 4.5 V < AVcc < 5.5 V
µs 4.0 V < AVcc < 4.5 V
µs 4.5 V < AVcc < 5.5 V
µs 4.0 V < AVcc < 4.5 V
Compare time
Sampling time
⎯
⎯
⎯
⎯
⎯
Analog port input
current
AN0 to
AN15
IAIN
− 0.3
⎯
⎯
+ 0.3
AVR
µA
Analog input
voltage
AN0 to
AN15
VAIN
AVSS
V
Reference voltage
⎯
IA
AVR
AVSS + 2.7
⎯
2.4
⎯
600
⎯
AVCC
4.7
5
V
⎯
⎯
⎯
⎯
mA
Power supply
current
AVCC
IAH
IR
µA
µA
µA
*
*
900
5
Reference voltage
supply current
AVR
IRH
Offset between
channels
AN0 to
AN15
—
⎯
⎯
4
LSB
* : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 5.0 V)
Note : The error increases proportionally as |AVR - AVSS| decreases.
DS07-13751-2E
43
MB90820B Series
6. A/D Converter Glossary
Resolution
: Analog variation that is recognized by an A/D converter.
Non linearity error
: Deviation between a line across zero-transition line (“00 0000 0000”↔
“00 0000 0001”) and full-scale transition line (“11 1111 1110”↔“11 1111 1111”) and
actual conversion characteristics.
Differential linearity error : Deviation of input voltage, which is required for changing output code by 1 LSB, from
an ideal value
Total error
: Difference between an actual value and an ideal value. A total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
1.5 LSB
3FEH
Actual conversion
characteristics
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Measurement value)
Actual
conversion
characteristics
Ideal
characteristics
0.5 LSB
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
Total error for digital output N =
[LSB]
1 LSB
AVR − AVss
1024
[V]
1 LSB = (Ideal value)
N : A/D converter digital output value
VOT(Ideal value) = AVss + 0.5 LSB [V]
VFST(Ideal value) = AVR − 1.5 LSB [V]
VNT : Voltage at which of digital output transitions from (N − 1)H to NH.
(Continued)
44
DS07-13751-2E
MB90820B Series
(Continued)
Linearity error
Actualconversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Differential linearity error
Ideal
characteristics
3FFH
3FEH
3FDH
Actualconversion
characteristics
(N + 1)H
VFST
(Measurement
value)
NH
VNT
(Measurement value)
004H
003H
002H
001H
V(N + 1)T
Actual
(Measurement value)
(N − 1)H
(N − 2)H
conversion
VNT
characteristics
(Measurement value)
Ideal
Actualconversion
characteristics
characteristics
VOT
(Measurement value)
AVss
AVR
AVss
AVR
Analog input
Analog input
Linearity error of
digital output N
VNT − {1 LSB × (N − 1) + VOT}
=
=
[LSB]
1 LSB
Differential linearity error
of digital output N
V (N + 1) T − VNT
− 1 [LSB]
1 LSB
VFST − VOT
[V]
1 LSB =
1022
N
: A/D converter digital output value
VOT : Voltage at which of digital output transmissions from “000H” to “001H”.
VFST : Voltage at which of digital output transmissions from “3FEH” to “3FFH”.
DS07-13751-2E
45
MB90820B Series
7. Notes on Using A/D Converter
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
And if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
R
C
MB90822B/823B
2.0 kΩ (Max)
14.4 pF (Max)
16.0 pF (Max)
MB90F822B/F823B 2.0 kΩ (Max)
Note : The values are reference values.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
20
18
16
14
12
10
8
100
90
80
70
60
50
40
30
20
10
0
MB90822B/
MB90822B/
823B
823B
MB90F822B/F823B
MB90F822B/F823B
6
4
2
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
Minimum sampling time [µs]
• About the error
The accuracy gets worse as | AVR−AVSS | becomes smaller.
46
DS07-13751-2E
MB90820B Series
8. Electrical Characteristics of D/A convertor
(VCC = AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Resolution
Symbol Pin name Condition
Unit Remarks
Min
⎯
Typ
8
Max
⎯
⎯
⎯
⎯
⎯
⎯
⎯
bit
Differential linearity error
Conversion time
⎯
⎯
0.5
⎯
LSB
⎯
⎯
0.45
2.9
160
0.1
µs
kΩ
µA
*
⎯
Analog output impedance
⎯
⎯
3.8
920
⎯
IDVR
IDVRS
⎯
Power supply current
AVCC
⎯
µA D/A stops
* : With load capacitance 20 pF.
DS07-13751-2E
47
MB90820B Series
9. Flash Memory Program/Erase Characteristics
Value
Parameter
Condition
Unit
Remarks
Min
Typ
Max
15
Excludes programming prior to
erasure
Sector erase time
Chip erase time
⎯
1
s
s
TA = +25 °C
VCC = 5.0 V
⎯
Excludes programming prior to
erasure
⎯
9
Word (16 bit width)
programing time
Except for the overhead time of
the system
⎯
10,000
20
16
⎯
⎯
3,600
⎯
µs
Program/Erase cycle
⎯
cycle
year
Flash data retention
time
Average
TA = +85 °C
⎯
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
■ ORDERING INFORMATION
Part number
MB90F823BPMC
Package
MB90F822BPMC
MB90822BPMC
MB90823BPMC
MB90F828BPMC
80-pin plastic LQFP
(FPT-80P-M21)
MB90F823BPMC1
MB90F822BPMC1
MB90822BPMC1
MB90823BPMC1
MB90F828BPMC1
80-pin plastic LQFP
(FPT-80P-M22)
MB90F823BPF
MB90F822BPF
MB90822BPF
MB90823BPF
MB90F828BPF
80-pin plastic QFP
(FPT-80P-M06)
48
DS07-13751-2E
MB90820B Series
■ PACKAGE DIMENSIONS
80-pin plastic LQFP
Lead pitch
0.50 mm
12 mm × 12 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.47 g
Code
(Reference)
P-LFQFP80-12×12-0.50
(FPT-80P-M21)
80-pin plastic LQFP
(FPT-80P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
*
0.145±0.055
(.006±.002)
60
41
61
40
0.08(.003)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 –+..000048
0.10±0.05
(.004±.002)
(Stand off)
INDEX
0˚~8˚
80
21
"A"
0.25(.010)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
1
20
LEAD No.
0.50(.020)
0.20±0.05
(.008±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2006-2008 FUJITSU MICROELECTRONICS LIMITED F80035S-c-2-3
2006 FUJITSU LIMITED F80035S-c-2-2
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07-13751-2E
49
MB90820B Series
80-pin plastic LQFP
Lead pitch
0.65 mm
14.00 mm × 14.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.62 g
Code
(Reference)
P-LFQFP80-14×14-0.65
(FPT-80P-M22)
80-pin plastic LQFP
(FPT-80P-M22)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
0.145±0.055
(.006±.002)
60
41
61
40
0.10(.004)
Details of "A" part
1.50 +–00..1200 .059 –+..000048
(Mounting height)
0.25(.010)
INDEX
0~8˚
80
21
0.10±0.10
(.004±.004)
(Stand off)
0.50±0.20
(.020±.008)
"A"
0.60±0.15
1
20
(.024±.006)
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2007-2008 FUJITSU MICROELECTRONICS LIMITED F80036S-c-1-2
2007 FUJITSU LIMITED F80036S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
50
DS07-13751-2E
MB90820B Series
(Continued)
80-pin plastic QFP
Lead pitch
0.80 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP80-14×20-0.80
Code
(Reference)
(FPT-80P-M06)
80-pin plastic QFP
(FPT-80P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
64
41
65
40
0.10(.004)
17.90±0.40
(.705±.016)
*
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
80
25
0.25(.010)
3.05 –+00..2300
.120 –+..000182
(Mounting height)
1
24
0~8
°
0.80(.031)
0.37±0.05
(.015±.002)
0.17±0.06
(.007±.002)
M
0.16(.006)
0.30 +–00..2150
0.80±0.20
(.031±.008)
"A"
.012 –+..001004
0.88±0.15
(Stand off)
(.035±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002-2008 FUJITSU MICROELECTRONICS LIMITED F80010S-c-6-6
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13751-2E
51
MB90820B Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
■ PACKAGE AND
CORRESPONDING PRODUCTS
■ ELECTRICAL CHARACTERISTICS Changed the unit of zero transition voltage and full-scale tran-
Change Results
Changed the MB90822B (FPT-80P-M21).
4
X : Not available →
: Available
43
48
5. A/D Converter Electrical
Characteristics
sition voltage.
mV → V
■ ORDERING INFORMATION
Added the part number.
MB90822BPMC
MB90823BPMC
The vertical lines marked in the left side of the page show the changes.
52
DS07-13751-2E
MB90820B Series
MEMO
DS07-13751-2E
53
MB90820B Series
MEMO
54
DS07-13751-2E
MB90820B Series
MEMO
DS07-13751-2E
55
MB90820B Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
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