MB90V880-102CR-ES_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13743-2E

16-Bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90880 Series

MB90F882(S)/F883(S)/F883A(S)/F884(S)/F884A(S)

MB90882(S)/883(S)/884(S)/V880(A)-101/-102

■ DESCRIPTION

The MB90880 series is a general-purpose 16-bit microcontroller, designed by Fujitsu, for process control of

devices such as consumer appliances, which require high-speed real-time processing capabilities.

The instruction set of the F²MC-16LX CPU core retains the same AT architecture as the F²MC*¹family, with further

refinements including high-level language instructions, an expanded addressing mode, enhanced multiplier-

divider instructions and bit processing. In addition, a 32-bit accumulator is built in to enable long word processing.

As its peripheral resources, the MB90880 series has a 16-bit PPG, multi-function serial interface (software switch

over enabled for SIO, UART and I²C*²) , 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up-down counter, base

timer (software switch over enabled for 16-bit reload timer, PWC timer, PPG timer and PWM timer) ,

DTP / external interrupt and chip select pins.

*1 : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

*2 : Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these

components in an I²C system provided that the system conforms to the I²C Standard Specification as defined

by Philips.

Be sure to refer to the “Check Sheet” for the latest cautions on development.

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system

development.

MB90880 Series

■ FEATURES

• Clock

Minimum instruction execution time : 30.3 ns / 4.125 MHz source oscillation × eight times

(in internal operation : 33 MHz/3.3 V 0.3 V)

PLL clock multiplication system

• Maximum memory space

16 Mbytes

• Instruction set optimized for control applications

Supported data types : bit, byte, word and long word

Standard addressing modes : 23 types

Enhanced high-precision calculation realized by 32-bit accumulator

Signed multiplication/division instructions and extended RETI instruction functions

• Instruction set supporting high-level language (C language) and multi-task operations

Introduction of system stack pointer

Symmetrical instruction set and barrel shift instructions

• Improved execution speed

4-byte queue

• Powerful interrupt functions

Eight priority levels programmable; External interrupts : 24

• Data transfer functions (µDMAC)

Up to 16 channels

• Built-in ROM

Flash ROM : 256, 384 and 512 Kbytes; MASK ROM : 256, 384 and 512 Kbytes

• Built-in RAM

Flash RAM : 16, 24 and 30 Kbytes; MASK RAM : 16, 24 and 30 Kbytes

• General-purpose ports

Dual clock product : up to 81 channels; Single clock product : up to 83 channels

• A/D converter

RC successive approximation conversion type : 20 channels (Resolution : 8 or 10 bits)

• Multi-function serial interface

7 channels (software switchable between for SIO, UART and I²C)

• 16-bit PPG

8 channels

• 8/16-bit up-down counter/timer

Event input pins : 6

8-bit up-down counters : 2

8-bit reload/compare registers : 2

• Base timer

4 channels (software switchable between 16-bit reload timer, PWC timer, PPG timer, and PWM timer)

• 16-bit I/O timer

Input capture × 2 channels, output compare × 6 channels, free run timer × 1 channel

• Built-in dual clock generator

• Low power consumption modes

Stop mode, sleep mode, CPU intermittent operation mode, watch timer, time base timer mode

• Package

QFP-100/LQFP-100

• Process

CMOS technology

• Power supply voltage

3V : Single power supply operation

2

MB90880 Series

■ PRODUCT LINEUP

Item

MB90F883 (S) / MB90F884 (S) /

MB90F883A(S) MB90F884A(S)

MB90882(S) MB90883(S) MB90884(S) MB90F882(S)

Name

Class

MASK ROM product

Flash memory product

ROM size

RAM size

256 Kbytes 384 Kbytes 512 Kbytes

256 Kbytes

16 Kbytes

384 Kbytes

24 Kbytes

512 Kbytes

30 Kbytes

16 Kbytes

24 Kbytes

30 Kbytes

Number of instructions

Instruction bit length

Instruction length

Data bit length

Minimum execution time

: 351

: 8 bits, 16 bits

: 1 to 7 bytes

: 1 bit, 8 bits, 16 bits

: 30.3 ns (machine clock : 33 MHz)

CPU functions

Ports

The maximum operating frequency of MB90F883(S) and MB90F884(S) is 25 MHz.

General-purpose I/O ports : up to 81 for dual clock model, up to 83 for single clock model

General-purpose I/O ports (CMOS output)

Multi-function

serial interface

7 channels (software switchable between SIO, UART & I²C)

16-bit PPG timer 8 channels

8/16-bit up-down Event input pins : 6, 8-bit up-down counters : 2

counter/timer

8-bit reload/compare registers : 2

16-bit

free run

timer

Number of channels : 1

Overflow interrupt

16-bit Output

Number of channels : 6

Pin input source : Match signal of compare register

I/O

compare

(OCU)

timer

Input

capture

(ICU)

Number of channels : 2

Rewriting register by pin input (rising, falling or both edges)

DTP/external

interrupt circuit

External interrupt pins : 24 channels (edge/level support)

4 channels

(software switchable between 16-bit reload timer, PWC timer, PPG timer, and PWM timer)

In MB90F883(S) and MB90F884(S), P24/TIO0, P25/TIO1, P26/TIO2, and P27/TIO3

cannot be used as input function.

Base timer

18-bit counter

Time base timer

Interrupt interval : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (source oscillation : 4 MHz)

Conversion accuracy : 8 or 10 bits can be switched

Single conversion mode (Selected channel converted only once)

Scan conversion mode (Multiple successive channels converted)

Successive conversion mode (Selected channel converted repeatedly)

Stop conversion mode (Selected channel converted and stopped repeatedly)

A/D converter

Reset generation interval : 3.58 ms, 14.33 ms, 57.23ms, 458.75 ms

(source oscillation : 4 MHz, minimum value)

Watchdog timer

(Continued)

3

MB90880 Series

(Continued)

Item

MB90F883 (S) / MB90F884 (S) /

MB90F883A(S) MB90F884A(S)

MB90882(S) MB90883(S) MB90884(S) MB90F882(S)

Name

Low power

consumption

(standby)

modes

Sleep, stop, CPU intermittent operation, watch timer, time base timer

Flash security/ write-protect feature

Flash memory

Process

⎯

(not available in MB90F883(S), MB90F884(S),

MB90F883A(S), and MB90F884A(S))

CMOS technology

4

MB90880 Series

■ PIN ASSIGNMENTS

(TOP VIEW)

P24/A20/TIO0

P25/A21/TIO1

1

2

3

4

5

6

7

8

9

80 P03/AD03/D03/IRQ3

79 P02/AD02/D02/IRQ2

78 P01/AD01/D01/IRQ1

77 P00/AD00/D00/IRQ0

76 P57/CLK/PPG7

75 P56/RDY/PPG6

74 P55/HAK/PPG5

73 P54/HRQ/PPG4

72 P53/WRH/IRQ23

71 P52/WRL

P26/A22/TIO2

P27/A23/TIO3

P30/A00/ZIN0/UI1

P31/A01/AIN0/UO1

P32/A02/BIN0/UCK1

P33/A03/UI2

P34/A04/UO2

P35/A05/ZIN1/UCK2 10

P36/A06/AIN1/IRQ8 11

P37/A07/BIN1/IRQ9 12

P40/A08/X0A* 13

P41/A09/X1A* 14

VCC 15

70 P51/RD

69 P50/ALE

68 PA3/(PPG7)/IRQ22

67 PA2/(PPG6)/IRQ21

66 DVSS

QFP-100

VSS 16

65 DVCC

C

17

64 PA1/(PPG5)/IRQ20

63 PA0/(PPG4)/IRQ19

62 P87/IRQ18/ADTG

61 P86/UCK0

P42/A10/UI3 18

P43/A11/UO3 19

P44/A12/UCK3 20

P45/A13/UI4 21

P46/A14/UO4 22

P47/A15/UCK4 23

P90/CS0/AN8 24

P91/CS1/AN9 25

P92/CS2/AN10 26

P93/CS3/AN11 27

P94/AN12 28

60 P85/UO0

59 P84/UI0

58 P83/IRQ17

57 P82/IRQ16/UCK6

56 P81/UO6

55 P80/IRQ15/UI6

54 RST

53 MD0

P95/(UI3)/AN13 29

P96/(UO3)/AN14 30

52 MD1

51 MD2

(FPT-100P-M06)

* : dual clock product is sub clock oscillation pin.

5

MB90880 Series

(TOP VIEW)

1

2

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P26/A22/TIO2

P27/A23/TIO3

P30/A00/ZIN0/UI1

P31/A01/AIN0/UO1

P32/A02/BIN0/UCK1

P33/A03/UI2

P00/AD00/D00/IRQ0

P57/CLK/PPG7

P56/RDY/PPG6

P55/HAK/PPG5

P54/HRQ/PPG4

P53/WRH/IRQ23

P52/WRL

3

4

5

6

7

P34/A04/UO2

P35/A05/ZIN1/UCK2

P36/A06/AIN1/IRQ8

P37/A07/BIN1/IRQ9

P40/A08/X0A*

P41/A09/X1A*

VCC

8

P51/RD

9

P50/ALE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PA3/(PPG7)/IRQ22

PA2/(PPG6)/IRQ21

DVSS

LQFP-100

DVCC

VSS

PA1/(PPG5)/IRQ20

PA0/(PPG4)/IRQ19

P87/IRQ18/ADTG

P86/UCK0

C

P42/A10/UI3

P43/A11/UO3

P44/A12/UCK3

P45/A13/UI4

P85/UO0

P84/UI0

P46/A14/UO4

P47/A15/UCK4

P90/CS0/AN8

P91/CS1/AN9

P92/CS2/AN10

P93/CS3/AN11

P83/IRQ17

P82/IRQ16/UCK6

P81/UO6

P80/IRQ15/UI6

RST

MD0

(FPT-100P-M20)

* : dual clock product is sub clock oscillation pin.

6

MB90880 Series

■ PIN DESCRIPTIONS

Pin no.

I/O

name

circuit

Function

LQFP *¹

QFP *²

type*³

P26

General-purpose I/O port

In multiplex mode, it serves as higher address output pin (A22) when

corresponding bit in external address output control register (HACR)

is set to "0".

1

3

A22

D

In non-multiplex mode, it serves as higher address output pin (A22)

when corresponding bit in external address output control register

(HACR) is set to "0".

TIO2

P27

Base timer I/O pin (ch.2)

General-purpose I/O port

In multiplex mode, it serves as higher address output pin (A23) when

corresponding bit in external address output control register (HACR)

is set to "0".

2

4

A23

D

In non-multiplex mode, it serves as higher address output pin (A23)

when corresponding bit in external address output control register

(HACR) is set to "0".

TIO3

P30

A00

ZIN0

UI1

Base timer I/O pin (ch.3)

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

8/16-bit up-down counter/timer input pin (ch.0)

Multi-function serial input pin

3

4

5

6

E

P31

A01

AIN0

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

8/16-bit up-down counter/timer input pin (ch.0)

UO1/

(SDA1)

Multi-function serial output pin

P32

A02

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

8/16-bit up-down counter/timer input pin (ch.0)

5

7

E

BIN0

UCK1/

(SCL1)

Multi-function serial clock I/O pin

P33

A03

UI2

General-purpose I/O port

6

7

8

9

E

Serves as an external address pin in non-multiplex mode.

Multi-function serial input pin

P34

A04

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

UO2/

(SDA2)

Multi-function serial output pin

(Continued)

7

MB90880 Series

Pin no.

I/O

circuit

Function

name

LQFP *¹

QFP *²

type*³

P35

A05

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

8/16-bit up-down counter/timer input pin (ch.1)

8

10

E

ZIN1

UCK2/

(SCL2)

Multi-function serial clock I/O pin

P36

A06

AIN1

IRQ8

P37

A07

BIN1

IRQ9

P40

A08

X0A

P41

A09

X1A

VCC

VSS

C

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

8/16-bit up-down counter/timer input pin (ch.1)

External interrupt input pin

9

11

12

D

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

8/16-bit up-down counter/timer input pin (ch.1)

External interrupt input pin

10

General-purpose I/O port

11

12

13

14

A/D Serves as an external address pin in non-multiplex mode.

32 kHz oscillator connecting pin

General-purpose I/O port

A/D Serves as an external address pin in non-multiplex mode.

32 kHz oscillator connecting pin

13

14

15

16

17

-

Power supply pin

Power supply pin (GND)

Regulator stabilization capacity connecting pin

General-purpose I/O port

P42

A10

UI3

16

17

18

19

E

Serves as an external address pin in non-multiplex mode.

Multi-function serial input pin

P43

A11

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

UO3/

(SDA3)

Multi-function serial output pin

P44

A12

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

18

19

20

21

E

UCK3/

(SCL3)

Multi-function serial clock I/O pin

P45

A13

UI4

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

Multi-function serial input pin

(Continued)

8

MB90880 Series

Pin no.

I/O

name

circuit

Function

LQFP *¹

QFP *²

type*³

P46

A14

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

Multi-function serial output pin

20

21

22

E

UO4/

(SDA4)

P47

A15

General-purpose I/O port

Serves as an external address pin in non-multiplex mode.

23

UCK4/

(SCL4)

Multi-function serial clock I/O pin

P90

CS0

AN8

P91

General-purpose I/O port

Chip select 0

22

23

24

25

26

H

Analog input pin

General-purpose I/O port

Chip select 1

CS1

AN9

P92

Analog input pin

General-purpose I/O port

Chip select 2

CS2

AN10

P93

Analog input pin

General-purpose I/O port

Chip select 3

25

26

27

28

29

CS3

AN11

P94

H

K

Analog input pin

General-purpose I/O port

Analog input pin

AN12

P95

General-purpose I/O port

Analog input pin

AN13

(UI3)

P96

Multi-function serial input pin (when set by P9FSR register)

General-purpose I/O port

Analog input pin

AN14

28

29

30

31

K

(UO3)/

(SDA3)

Multi-function serial output pin (when set by P9FSR register)

P97

General-purpose I/O port

Analog input pin

AN15

(UCK3)/

(SCL3)

Multi-function serial clock I/O pin (when set by P9FSR register)

30

31

32

33

AVCC

AVRH

P70

-

A/D converter power supply pin

A/D converter external reference power supply pin

General-purpose I/O port

32

34

H

AN16

Analog input pin

(Continued)

9

MB90880 Series

Pin no.

I/O

circuit

Function

A/D converter power supply pin

name

LQFP *¹

QFP *²

type*³

33

35

AVSS

P60

-

General-purpose I/O port

Analog input pin

34

35

36

37

38

39

40

36

37

38

39

40

41

42

H

AN0

P61

General-purpose I/O port

Analog input pin

H

AN1

P62

General-purpose I/O port

Analog input pin

AN2

P63

General-purpose I/O port

Analog input pin

AN3

P64

General-purpose I/O port

Analog input pin

AN4

P65

General-purpose I/O port

Analog input pin

AN5

P66

General-purpose I/O port

Analog input pin

AN6

P67

General-purpose I/O port

Analog input pin

41

42

43

44

H

-

AN7

VSS

P71

Power supply pin (GND)

General-purpose I/O port

External interrupt input pin

Analog input pin

IRQ10

AN17

(UI4)

P72

43

44

45

46

K

Multi-function serial input pin (when set by P7FSR register)

General-purpose I/O port

External interrupt input pin

Analog input pin

IRQ11

AN18

(UO4)/

(SDA4)

Multi-function serial output pin (when set by P7FSR register)

P73

General-purpose I/O port

External interrupt input pin

Analog input pin

IRQ12

AN19

45

46

47

48

K

(UCK4)/

(SCL4)

Multi-function serial clock I/O pin (when set by F7FSR register)

P74

IRQ13

UI5

General-purpose I/O port

External interrupt input pin

Multi-function serial input pin

G

(Continued)

10

MB90880 Series

Pin no.

I/O

name

circuit

Function

LQFP *¹

QFP *²

type*³

P75

General-purpose I/O port

47

48

49

G

UO5/

Multi-function serial output pin

(SDA5)

P76

General-purpose I/O port

External interrupt input pin

IRQ14

50

UCK5/

(SCL5)

Multi-function serial clock I/O pin

49

50

51

52

51

52

53

54

MD2

MD1

MD0

RST

P80

L

B

Operation mode specification input pin

Reset input pin

General-purpose I/O port

53

54

55

56

IRQ15

UI6

G

External interrupt input pin

Multi-function serial input pin

General-purpose I/O port

P81

UO6/

(SDA6)

Multi-function serial output pin

P82

General-purpose I/O port

External interrupt input pin

IRQ16

55

57

G

UCK6/

(SCL6)

Multi-function serial clock I/O pin

P83

IRQ17

P84

General-purpose I/O port

External interrupt input pin

General-purpose I/O port

Multi-function serial input pin

General-purpose I/O port

56

57

58

59

I

G

UI0

P85

58

59

60

61

G

UO0/

Multi-function serial output pin

General-purpose I/O port

(SDA0)

P86

UCK0/

(SCL0)

Multi-function serial clock I/O pin

P87

IRQ18

ADTG

PA0

General-purpose I/O port

60

61

62

63

I

External interrupt input pin

External trigger input pin, when A/D converter is used.

General-purpose I/O port

IRQ19

(PPG4)

J

External interrupt input pin

PPG timer output pin (when set by PAFSR register)

(Continued)

11

MB90880 Series

Pin no.

I/O

circuit

Function

name

LQFP *¹

QFP *²

type*³

PA1

IRQ20

(PPG5)

DVCC

DVSS

PA2

General-purpose I/O port

External interrupt input pin

62

64

J

PPG timer output pin (when set by PAFSR register)

PA port power supply pin

63

64

65

66

-

PA port power supply pin (GND)

General-purpose I/O port

65

66

67

68

IRQ21

(PPG6)

PA3

J

External interrupt input pin

PPG timer output pin (when set by PAFSR register)

General-purpose I/O port

IRQ22

(PPG7)

P50

External interrupt input pin

PPG timer output pin (when set by PAFSR register)

General-purpose I/O port

67

68

69

70

F

Serves as address latch enable signal (ALE) pin in external bus

mode.

ALE

P51

RD

General-purpose I/O port

Serves as read strobe output (RD) pin in external bus mode.

General-purpose I/O port

P52

Serves as lower data write strobe output (WRL) pin in external bus

mode, and serves as a general-purpose I/O port when WRE bit in

EPCR register is "0".

69

70

71

72

F

WRL

P53

General-purpose I/O port

Serves as higher data write strobe output (WRH) pin in external bus

mode with 16-bit bus width, and serves as a general-purpose I/O

port when WRE bit in EPCR register is "0".

WRH

IRQ23

P54

External interrupt input pin

General-purpose I/O port

Serves as hold request input (HRQ) pin in external bus mode, and

serves as a general-purpose I/O port when HDE bit in EPCR register

is "0".

71

72

73

74

HRQ

F

PPG4

P55

PPG timer output pin

General-purpose I/O port

Serves as hold acknowledge output (HAK) pin in external bus mode,

and serves as a general-purpose I/O port when HDE bit in EPCR

register is "0".

HAK

PPG5

PPG timer output pin

(Continued)

12

MB90880 Series

Pin no.

I/O

name

circuit

Function

LQFP *¹

QFP *²

type*³

P56

General-purpose I/O port

Serves as external ready input (RDY) pin in external bus mode, and

serves as a general-purpose I/O port when RYE bit in EPCR register

is "0".

73

74

75

RDY

F

C

PPG6

P57

PPG timer output pin

General-purpose I/O port

Serves as machine cycle clock output (CLK) pin in external bus

mode, and serves as a general-purpose I/O port when CKE bit in

EPCR register is "0".

76

77

CLK

PPG7

P00

PPG timer output pin

General-purpose I/O port

In multiplex mode, it serves as lower external address/data bus I/O

pin.

AD00/

D00

Serves as lower external data bus output pin in non-multiplex mode.

External interrupt input pin

IRQ0

P01

General-purpose I/O port

Serves as an external address/lower data bus I/O pin in multiplex

mode.

AD01/

D01

76

77

78

79

78

79

80

81

C

Serves as a lower external data bus output pin in non-multiplex

mode.

IRQ1

P02

External interrupt input pin

General-purpose I/O port

Serves as an external address/lower data bus I/O pin in multiplex

mode.

AD02/

D02

Serves as a lower external data bus output pin in non-multiplex

mode.

IRQ2

P03

External interrupt input pin

General-purpose I/O port

Serves as an external address/lower data bus I/O pin in multiplex

mode.

AD03/

D03

Serves as a lower external data bus output pin in non-multiplex

mode.

IRQ3

P04

External interrupt input pin

General-purpose I/O port

In multiplex mode, it serves as lower external address/data bus I/O

pin.

AD04/

D04

Serves as a lower external data bus output pin in non-multiplex

mode.

IRQ4

External interrupt input pin

(Continued)

13

MB90880 Series

Pin no.

I/O

circuit

Function

LQFP *¹

QFP *²

name

type*³

P05

General-purpose I/O port

In multiplex mode, it serves as lower external address/data bus I/O

pin.

AD05/

D05

80

82

C

Serves as a lower external data bus output pin in non-multiplex

mode.

IRQ5

P06

External interrupt input pin

General-purpose I/O port

In multiplex mode, it serves as lower external address/data bus I/O

pin.

AD06/

D06

81

82

83

84

Serves as a lower external data bus output pin in non-multiplex

mode.

IRQ6

P07

External interrupt input pin

General-purpose I/O port

In multiplex mode, it serves as lower external address/data bus I/O

pin.

AD07/

D07

Serves as a lower external data bus output pin in non-multiplex

mode.

IRQ7

P10

External interrupt input pin

General-purpose I/O port

In multiplex mode, it serves as higher external address/data bus I/O

pin.

AD08/

D08

83

84

85

86

85

86

87

88

C

In non-multiplex mode, it serves as higher external data output pin.

Output compare event output pin

OUT0

P11

General-purpose I/O port

In multiplex mode, it serves as higher external address/data bus I/O

pin.

AD09/

D09

In non-multiplex mode, it serves as higher external data output pin.

Output compare event output pin

OUT1

P12

General-purpose I/O port

In multiplex mode, it serves as higher external address/data bus I/O

pin.

AD10/

D10

In non-multiplex mode, it serves as higher external data output pin.

Output compare event output pin

OUT2

P13

General-purpose I/O port

In multiplex mode, it serves as higher external address/data bus I/O

pin.

AD11/

D11

In non-multiplex mode, it serves as higher external data output pin.

Output compare event output pin

OUT3

(Continued)

14

MB90880 Series

Pin no.

I/O

name

circuit

Function

LQFP *¹

QFP *²

type*³

P14

General-purpose I/O port

AD12/

D12

87

89

C

In non-multiplex mode, it serves as higher external data output pin.

OUT4

VCC

VSS

X1

Output compare event output pin

Power supply pin

88

89

90

91

90

91

92

93

-

Power supply pin (GND)

Main oscillator connecting pin

General-purpose I/O port

A

X0

P15

In multiplex mode, it serves as higher external address/data bus I/O

pin.

AD13/

D13

92

93

94

95

96

C

In non-multiplex mode, it serves as higher external data output pin.

Output compare event output pin

OUT5

P16

General-purpose I/O port

In multiplex mode, it serves as higher external address/data bus I/O

pin.

AD14/

D14

In non-multiplex mode, it serves as higher external data output pin.

Trigger input pin for input capture ch.0

IN0

P17

General-purpose I/O port

In multiplex mode, it serves as higher external address/data bus I/O

pin.

AD15/

D15

In non-multiplex mode, it serves as higher external data output pin.

Trigger input pin for input capture ch.1

IN1

P20

General-purpose I/O port

In multiplex mode, it serves as higher address output pin (A16) when

corresponding bit in external address output control register (HACR)

is set to "0".

95

97

A16

D

In non-multiplex mode, it serves as higher address output pin (A16)

when corresponding bit in external address output control register

(HACR) is set to "0".

PPG0

P21

PPG timer output pin

General-purpose I/O port

In multiplex mode, it serves as higher address output pin (A17) when

corresponding bit in external address output control register (HACR)

is set to "0".

96

98

A17

D

In non-multiplex mode, it serves as higher address output pin (A17)

when corresponding bit in external address output control register

(HACR) is set to "0".

PPG1

PPG timer output pin

(Continued)

15

MB90880 Series

(Continued)

Pin no.

I/O

name

circuit

Function

LQFP *¹

QFP *²

type*³

P22

General-purpose I/O port

In multiplex mode, it serves as higher address output pin (A18) when

corresponding bit in external address output control register (HACR)

is set to "0".

97

99

A18

D

In non-multiplex mode, it serves as higher address output pin (A18)

when corresponding bit in external address output control register

(HACR) is set to "0".

PPG2

P23

PPG timer output pin

General-purpose I/O port

In multiplex mode, it serves as higher address output pin (A19) when

corresponding bit in external address output control register (HACR)

is set to "0".

98

100

A19

In non-multiplex mode, it serves as higher address output pin (A19)

when corresponding bit in external address output control register

(HACR) is set to "0".

PPG3

P24

PPG timer output pin

General-purpose I/O port

In multiplex mode, it serves as higher address output pin (A20) when

corresponding bit in external address output control register (HACR)

is set to "0".

99

1

A20

In non-multiplex mode, it serves as higher address output pin (A20)

when corresponding bit in external address output control register

(HACR) is set to "0".

TIO0

P25

Base timer I/O pin (ch.0)

General-purpose I/O port

In multiplex mode, it serves as higher address output pin (A21) when

corresponding bit in external address output control register (HACR)

is set to "0".

100

2

A21

In non-multiplex mode, it serves as higher address output pin (A21)

when corresponding bit in external address output control register

(HACR) is set to "0".

TIO1

Base timer I/O pin (ch.1)

*1 : LQFP : FPT-100P-M20

*2 : QFP : FPT-100P-M06

*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.

16

MB90880 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation feedback resistance

X1, X0 : approx. 1 MΩ

X1A, X0A : approx. 10 MΩ

• Standby control provided

X1, X1A

P-ch

N-ch

Xout

A

B

X0, X0A

Standby control

signal

Hysteresis input with pull-up resistor

R

Hysteresis input

• Input pull-up resistor control provided

• CMOS level output

• Hysteresis input

Pull-up control signal

P-ch

N-ch

• CMOS input (in external bus mode)

C

D

E

R

CMOS input

Hysteresis input

Standby control for

input shutdown

• CMOS level output

• Hysteresis input

P-ch

N-ch

R

Hysteresis input

Standby control for

input shutdown

• CMOS level output

• Hysteresis input

• I²C level hysteresis input

P-ch

N-ch

R

Hysteresis input

I²C level

hysteresis input

Standby control for

input shutdown

(Continued)

17

MB90880 Series

Type

Circuit

Remarks

• CMOS level output

P-ch

N-ch

• Hysteresis input

• CMOS input (in external bus mode)

F

R

CMOS input

Hysteresis input

Standby control for

input shutdown

• CMOS level output

(Open-drain control provided)

• 5V tolerant

• Hysteresis input

• I²C level hysteresis input

P-ch

N-ch

Open-drain control

signal

G

R

Hysteresis input

I²C level

hysteresis input

Standby control for

input shutdown

• CMOS level output

• Hysteresis input

• Analog input

P-ch

N-ch

H

R

Hysteresis input

Standby control for

input shutdown

Analog input

• CMOS level output

(Open-drain control provided)

• 5V tolerant

P-ch

N-ch

Open-drain control

signal

• Hysteresis input

I

R

Hysteresis input

Standby control for

input shutdown

(Continued)

18

MB90880 Series

(Continued)

Type

Circuit

Remarks

• CMOS/level output

(high-current type)

• Hysteresis input

P-ch

N-ch

J

R

Hysteresis input

Standby control for

input shutdown

• CMOS level output

• Hysteresis input

• Analog input

• I²C level hysteresis input

P-ch

N-ch

R

K

Hysteresis input

I²C level

Hysteresis input

Standby control for

input shutdown

Analog input

Flash memory product

• CMOS level input

• High-voltagecontrolforflashtest

provided

Flash memory product

N-ch

Control signal

Mode input

N-ch

R

L

Diffused resistor

MASK ROM product

Hysteresis input

MASK ROM product

R

Hysteresis input

19

MB90880 Series

■ HANDLING DEVICES

1. Maximum rated voltages for the prevention of latch-up

Be cautious not to exceed the absolute maximum rating.

CMOS ICs may cause latch-up, when a voltage higher than V^CCor lower than VSS is applied to input or output

pins other than medium-to-high resistant pins, or when a voltage exceeding the rating is applied between VCC

and VSS pins.

If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the

device. Take the utmost care not to let it occur.

Likewise, care must be taken not to allow the analog power supply (AV^CC, AVRH) and analog input to exceed

the digital power supply (VCC) when turning on or off any analog system.

2. Handling unused pins

Leaving unused input pins open may cause a malfunction or latch-up which leads to fatal damage to the device.

Therefore, they must be pulled up or down through at least 2 kΩ resistance. Also, any unused I/O pin should be

left open in the output state, or set to the input state and handled in the same way as an unused input pin.

3. Notes on using external clock

Even when an external clock is being used, oscillation stabilization wait time is required for a power-on reset or

release from sub clock mode or stop mode. Note that 25 MHz is the upper limit on the external clock that can

be used. The following diagram shows an example of using an external clock.

X0

Open

X1

4. Handling power supply pins (VCC/VSS)

When multiple VCC and VSS pins supply pins are used, all the power supply pins must be connected to external

power and ground lines due to the device design, to reduce latch-up and unwanted radiation, prevent abnormal

operation of strobe signals caused by the rise in the ground level and to conform to the total output current rating.

MakesuretoconnecttheVCCandVSSpinsofthisdevicevialowestimpedancetopowerlines. Itisrecommended

that a bypass capacitor of around 0.1 µF be placed between the VCC and VSS pins near the device.

5. Crystal oscillator circuit

Noises around X0/X1 or X0A/X1A pins may cause abnormal operations. It is strongly recommended to provide

bypass capacitors via shortest distance from X0/X1, X0A/X1A pins, crystal oscillator (or ceramic oscillator) and

ground lines and also not to allow the lines of the oscillation circuit to cross the lines of other circuits. This will

ensure stable operations of the printed circuit boards. Please ask each crystal maker to evaluate the oscillational

characteristics of the crystal and this device.

6. Notes on PLL clock mode operation

If an oscillator comes off or clock input stops during PLL clock mode operation, this microcontroller may continue

its operation using a free-running frequency from a self-excited oscillation circuit within PLL. This is not a

guaranteed operation.

20

MB90880 Series

7. Power-on and power-off sequence of A/D converter and analog input

Turn on the A/D converters (AVCC, AVRH) and analog inputs (AN0 to AN19) after turning on the digital power

supply (VCC) .

During power-off, turn off the digital power supply (V^CC) after turning off the A/D converters and analog inputs

(AN0 to AN19) .

In this case, make sure that AVRH does not exceed AVCC during the power-on/power-off procedure.

Also make sure that the input voltage does not exceed AV^CCwhen a pin which is also used as an analog input

is used as an input port.

8. Handling power supply pins on A/D converter-mounted models

Make sure to achieve "AVCC = AVRH = VCC" and "AVSS = VSS" in connecting the circuits, even when not using the

A/D converter function.

9. Note on power-up

To prevent the internal regulator from malfunctioning, maintain the voltage rise time at 50 µs (between 0.2V and

2.7V) or more during power-up.

10. Stabilization of power supply

Even when the VCC power supply voltage is within the specified operating range, it may still cause the device to

malfunction, if the power supply changes rapidly. For stabilization reference, it is recommended to control the

supply voltage so that V^CCripple variations (P-P values) at commercial frequencies (50/60 Hz) fall below 10%

of the standard V^CCsupply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous

power switching.

11. Writing to Flash memory

For serial writing to Flash memory, always make sure that the operating voltage VCC is between 3.13V and 3.6V.

For normal writing to Flash memory, always make sure that the operating voltage VCC is between 3.0V and 3.6V.

12. P90/CS0 pins

P90/CS0 pins output “L” during writing Flash serial. Do not input from external.

13. Note of MB90F883 (S) , MB90F884 (S)

• Maximum operating frequency is 25 MHz.

• The base timer cannot use P24/TIO0, P25/TIO1, P26/TIO2, and P27/TIO3 as input function.

• MB90F883(S) and MB90F884(S) do not contain the flash security feature and write-protect feature.

21

MB90880 Series

■ BLOCK DIAGRAM

CPU

X0, X1, RST

F²MC-16LX

series core

Clock control

X0A, X1A

circuit

MD0 to MD2

RAM

Interrupt controller

ROM

µDMAC

16-bit PPG

PPG0 to PPG7

UI0 to UI6

UO0 to UO6

UCK0 to UCK6

Multifunction serial

SIO/UART/I²C

mode switching

enabled

8/16-bit

up-down

counter/timer

AIN0, AIN1

BIN0, BIN1

ZIN0, ZIN1

I/O timer

AVCC

AVRH

AVSS

ADTG

16-bit input capture ×

IN0, IN1

2 channels

10-bit

A/D converter

OUT0 to OUT5

16-bit output compare ×

6 channels

16-bit free-run timer

AN0 to AN19

24

TIO0 to TIO3

External interrupt

IRQ0 to IRQ23

16-bit base timer

Reload timer/PWM/PWC

mode switching enabled

I/O port

8

7

8

4

P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0

to to to to to to to to to to to

P07 P17 P27 P37 P47 P57 P67 P76 P87 P97 PA3

Note : The I/O ports shown in the diagram above are shared by other built-in function blocks. They cannot be used

as I/O ports when used as pins for a built-in module.

22

MB90880 Series

■ MEMORY MAP

Internal ROM

external bus

External ROM

external bus

Single chip mode

ROM area

FFFFFF

H

ROM area

Address #1

010000

H

ROM area

Image of FF bank

ROM area

Image of FF bank

Address #2

Peripheral area

007900

H

Address #3

Register

RAM

Register

RAM

Register

RAM

000100

0000F0

H

Peripheral area

: Internal

Peripheral area

: External

Peripheral area

000000

H

: Access prohibited

Parts No.

MB90882 (S)

MB90F882 (S)

MB90883 (S)

Address #1

Address #2

Address #3

FC0000^H

FC0000H

FA0000H

004100^H

004100H

006100H

MB90F883 (S) /

MB90F883A (S)

FA0000^H

F80000H

F80000^H

(F80000H)

006100H

007900H

008000H, fixed

MB90884 (S)

MB90F884 (S) /

MB90F884A (S)

MB90V880 (S)

Note : The image of the ROM data in the FF band appears at the top of the 00 bank in order to enable efficient use

of the C compiler small memory model. The lower 16-bit address for the FF bank will be assigned to the

same address, so that tables in ROM can be referenced without declaring a "far" indication with the pointer.

For example, when accessing the address 00C000^H, the actual access is to address FFC000H in ROM.

Here the FF bank ROM area exceeds 32 Kbytes, it is not possible to see the entire area in the 00 bank

image. Therefore, the ROM data in FF8000^Hto FFFFFFH can be seen in the 00 bank image, while the data

in FF0000^Hto FF7FFFH can only be seen in the FF bank.

23

MB90880 Series

■ F²MC-16L CPU PROGRAMMING MODEL

• Dedicated register

Accumulator

AH

AL

User stack pointer

System stack pointer

Processor status

Program counter

USP

SSP

PS

PC

Direct page register

DPR

Program bank register

Data bank register

PCB

DTB

USB

SSB

ADB

User stack bank register

System stack bank register

Additional data bank register

8 bits

16 bits

32 bits

• General-purpose register

MSB

LSB

16 bits

000180H + RP × 10H

RW0

RW1

RW2

RW3

RL0

RL1

RL2

RL3

R1

R3

R5

R7

R0

R2

R4

R6

RW4

RW5

RW6

RW7

• Processor status

bit 15

bit 13 bit 12

bit 8 bit 7

bit 0

PS

ILM

RP

CCR

24

MB90880 Series

■ I/O MAP

Register

Address

Register name

Port 0 data register

R/W

Resource

Initial value

abbreviation

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

00000AH

PDR0

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

XXXXXXXXB

PDR1

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

Up-down timer input

control

00000BH

UDER

Up-down timer input enable register

R/W

XX000000B

00000CH

00000DH

00000EH

00000FH

000010H

000011H

000012H

000013H

000014H

000015H

000016H

000017H

000018H

000019H

00001AH

00001BH

00001CH

00001DH

ILSR0

ILSR1

ILSR2

Serial input level selection register 0

Serial input level selection register 1

Serial input level selection register 2

R/W

00000000B

---00000B

Multi-function serial

control

Disabled

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

DDRA

ADER0

ADER1

ADER2

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

Port A direction register

Analog input enable register 0

Analog input enable register 1

Analog input enable register 2

R/W

Port 0

Port 1

00000000B

-0000000B

00000000B

----0000B

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port 6, A/D

Port 9, A/D

Port 7, A/D

11111111B

----1111B

Port 0 (pull-up

00001EH

00001FH

RDR0

RDR1

Port 0 input resistance register

Port 1 input resistance register

R/W

00000000B

resistance control)

Port 1 (pull-up

resistance control)

00000000B

(Continued)

25

MB90880 Series

Register

Address

Register name

R/W

Resource

Initial value

$$$$$$$$B

abbreviation

000020^H

SMR0

Serial bus mode register ch.0

SCR0/IBCR0 serial bus control

000021H SCR0/IBCR0

register/I²C bus control register ch.0

Extended communication control

register/I²C bus status register ch.0

ESCR0/

000022H

R/W

R,W

$$$$$$$$B

$$$$$$$$^B

IBSR0

000023H

000024H

SSR0

Serial status register ch.0

Transmission/reception data register 0

ch.0

RDR00/

TDR00

Multi-function serial

ch.0

Transmission/reception data register 1

ch.0

RDR10/

TDR10

000025H

R,W

$$$$$$$$B

000026H

000027H

000028H

000029H

00002AH

BGR00

BGR10

ISBA0

ISMK0

SMR1

Baud rate generator register 0 ch.0

Baud rate generator register 1 ch.0

7-bit slave address register ch.0

7-bit slave address mask register ch.0

Serial bus mode register ch.1

R/W

$$$$$$$$B

00000000B

01111111B

$$$$$$$$B

Serial bus control register / I²C bus

control register ch.1

00002BH SCR1/IBCR1

R/W

$$$$$$$$B

Extended communication control

ESCR1/

00002CH

R/W

R,W

$$$$$$$$^B

$$$$$$$$B

register / I²C bus status register ch.1

IBSR1

00002DH

00002EH

SSR1

Serial status register ch.1

Transmission/reception data register 0

ch.1

RDR01/

TDR01

Multi-function serial

ch.1

Transmission/reception data register 1

ch.1

RDR11/

TDR11

00002FH

R,W

$$$$$$$$^B

000030H

000031H

000032H

000033H

000034H

000035H

000036H

000037H

BGR01

BGR11

ISBA1

Baud rate generator register 0 ch.1

Baud rate generator register 1 ch.1

7-bit slave address register ch.1

7-bit slave address mask register ch.1

Lower A/D control status register

Higher A/D control status register

Lower A/D data register

R/W

R

$$$$$$$$B

00000000B

01111111B

00011110B

00000000B

XXXXXXXXB

111111XXB

ISMK1

ADCSL

ADCSH

ADCRL

ADCRH

Higher A/D data register

R

A/D Converter

Lower A/D conversion channel setting

register

000038H

ADSRL

ADSRH

R/W

00000000B

Higher A/D conversion channel setting

register

000039H

00003AH

Reserved

(Continued)

26

MB90880 Series

Register

Address

00003B^H

00003CH

Register name

R/W

Resource

Initial value

00000000^B

-000----^B

abbreviation

Address detection control status

register 1

Address match

detection function

PACSR1

OLSR0

Port 7 (N-ch

open-drain control)

Output level selection register 0

Port 8 (N-ch

open-drain control)

00003DH

00003EH

OLSR1

SMR2

Output level selection register 1

Serial bus mode register ch.2

Serial bus control register / I²C bus

control register ch.2

R/W

00000000^B

$$$$$$$$B

00003FH SCR2/IBCR2

Extended communication control

ESCR2/

000040H

R/W

R,W

$$$$$$$$B

register / I²C bus status register ch.2

IBSR2

000041H

000042H

SSR2

Serial status register ch.2

Transmission/reception data register 0

ch.2

RDR02/

TDR02

Multi-function serial

ch.2

Transmission/reception data register 1

ch.2

RDR12/

TDR12

000043H

R,W

$$$$$$$$B

000044H

000045H

000046H

000047H

000048H

BGR02

BGR12

ISBA2

ISMK2

SMR3

Baud rate generator register 0 ch.2

Baud rate generator register 1 ch.2

7-bit slave address register ch.2

7-bit slave address mask register ch.2

Serial bus mode register ch.3

R/W

$$$$$$$$B

00000000B

01111111B

$$$$$$$$B

Serial bus control register / I²C bus

control register ch.3

000049H SCR3/IBCR3

R/W

$$$$$$$$B

Extended communication control

ESCR3/

00004AH

R/W

R,W

$$$$$$$$B

register / I²C bus status register ch.3

IBSR3

00004BH

00004CH

SSR3

Serial status register ch.3

Transmission/reception data register 0

ch.3

RDR03/

TDR03

Multi-function serial

ch.3

Transmission/reception data register 1

ch.3

RDR13/

TDR13

00004DH

R,W

$$$$$$$$^B

00004EH

00004FH

000050H

000051H

000052H

BGR03

BGR13

ISBA3

ISMK3

SMR4

Baud rate generator register 0 ch.3

Baud rate generator register 1 ch.3

7-bit slave address register ch.3

7-bit slave address mask register ch.3

Serial bus mode register ch.4

R/W

$$$$$$$$B

00000000B

01111111B

$$$$$$$$B

Multi-function serial

ch.4

Serial bus control register / I²C bus

control register ch.4

000053H SCR4/IBCR4

R/W

$$$$$$$$B

(Continued)

27

MB90880 Series

Register

Address

Register name

R/W

Resource

Initial value

abbreviation

Extended communication control

ESCR4/

IBSR4

000054^H

000055H

000056H

R/W

R,W

$$$$$$$$B

register / I²C bus status register ch.4

SSR4

Serial status register ch.4

Transmission/reception data register 0

ch.4

RDR04/

TDR04

Multi-function serial

ch.4

Transmission/reception data register 1

ch.4

RDR14/

TDR14

000057H

R,W

$$$$$$$$B

000058H

000059H

00005AH

00005BH

00005CH

BGR04

BGR14

ISBA4

ISMK4

SMR5

Baud rate generator register 0 ch.4

Baud rate generator register 1 ch.4

7-bit slave address register ch.4

7-bit slave address mask register ch.4

Serial bus mode register ch.5

R/W

$$$$$$$$B

00000000B

01111111B

$$$$$$$$B

Serial bus control register / I²C bus

control register ch.5

00005DH SCR5/IBCR5

R/W

$$$$$$$$B

Extended communication control

ESCR5/

00005EH

R/W

R,W

$$$$$$$$B

register / I²C bus status register ch.5

IBSR5

00005FH

000060H

SSR5

Serial status register ch.5

Transmission/reception data register 0

ch.5

RDR05/

TDR05

Multi-function serial

ch.5

Transmission/reception data register 1

ch.5

RDR15/

TDR15

000061H

R,W

$$$$$$$$B

000062H

000063H

000064H

000065H

000066H

000067H

000068H

000069H

00006AH

00006BH

00006CH

00006DH

00006EH

00006FH

BGR05

BGR15

ISBA5

ISMK5

Baud rate generator register 0 ch.5

Baud rate generator register 1 ch.5

7-bit slave address register ch.5

7-bit slave address mask register ch.5

Lower output compare register (ch.0)

Higher output compare register (ch.0)

Lower output compare register (ch.1)

Higher output compare register (ch.1)

Lower output compare register (ch.2)

Higher output compare register (ch.2)

Lower output compare register (ch.3)

Higher output compare register (ch.3)

Reserved

R/W

$$$$$$$$B

00000000B

01111111B

00000000^B

00000000B

00000000^B

00000000B

00000000^B

00000000B

00000000^B

00000000B

OCCP0

OCCP1

OCCP2

OCCP3

R/W

16-bit I/O timer output

compare

(ch.0 to ch.5)

ROMM

ROM mirror function selection register

R/W

ROM mirror function

-------1B

(Continued)

28

MB90880 Series

Register

abbreviation

Address

Register name

R/W

Resource

Initial value

000070^H

000071H

000072H

000073H

Lower output compare register (ch.4)

Higher output compare register (ch.4)

Lower output compare register (ch.5)

Higher output compare register (ch.5)

00000000^B

00000000B

00000000^B

00000000B

OCCP4

OCCP5

R/W

Lower output compare control register

(ch.0, ch.1)

000074H

000075H

000076H

000077H

000078H

R/W

0000--00^B

---00000B

0000--00^B

---00000B

0000--00^B

OCS01

OCS23

OCS45

Higher output compare control register

(ch.0, ch.1)

16-bit I/O timer output

compare

(ch.0 to ch.5)

Lower output compare control register

(ch.2, ch.3)

Higher output compare control register

(ch.2, ch.3)

Lower output compare control register

(ch.4, ch.5)

Higher output compare control register

(ch.4, ch.5)

000079H

00007AH

00007BH

00007CH

00007DH

R/W

R

---00000B

Lower input capture data register (ch.0)

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

IPCP0

IPCP1

Higher input capture data register

(ch.0)

R

6-bit I/O timer

input capture

(ch.0, ch.1)

Lower input capture data register (ch.1)

R

Higher input capture data register

(ch.1)

R

00007EH

00007FH

000080H

000081H

000082H

000083H

000084H

000085H

ICS01

ICE01

TCDT

TCCS

Input capture control status register

Input capture edge register

R/W

R

00000000B

------XXB

Lower timer counter data register

Higher timer counter data register

Timer control status register

Lower compare clear register

Higher compare clear register

R/W

00000000B

XX-00000B

XXXXXXXX^B

XXXXXXXXB

16-bit I/O timer

free-run timer

CPCLR

R/W

000086H

to

00009AH

Reserved

DMAC descriptor channel specification

register

00009B^H

DCSR

R/W

DMAC

00000000B

00009CH

00009DH

DSRL

DSRH

DMAC lower status register

DMAC higher status register

R/W

DMAC

00000000B

(Continued)

29

MB90880 Series

Register

Address

Register name

R/W

Resource

Initial value

00000000^B

-------0^B

abbreviation

Address detection control status

register 0

Address match

detection function

00009E^H

00009FH

PACSR0

DIRR

Delayed interrupt source generation/

release register

Delayed interrupt

generation module

Low power consumption mode control

register

0000A0H

0000A1H

LPMCR

CKSCR

W, R/W

R, R/W

00011000B

11111100B

Low power

consumption

Clock selection register

Reserved

0000A2H,

0000A3^H

0000A4H

0000A5H

0000A6H

0000A7H

0000A8H

0000A9H

0000AAH

0000ABH

0000ACH

0000ADH

0000AEH

0000AFH

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

DSSR

ARSR

HACR

EPCR

WDTC

TBTC

WTC

DMAC stop status register

Auto ready function selection register

External address output control register

Bus control signal selection register

Watchdog timer control register

Time base timer control register

Watch timer control register

Reserved

R/W

W

DMAC

00000000B

0011--00B

********B

W

External pin

W

1000*10-B

XXXXX111B

1XX00100B

10001000B

R, W

W, R/W

R, R/W

Watchdog timer

Time base timer

Watch timer

DERL

DERH

FMCS

DMAC lower enable register

DMAC higher enable register

Flash memory control status register

Prohibited

R/W

00000000B

000X0000B

DMAC

W, R/W

Flash memory I/F

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

W, R/W

00000111B

Interrupt control

00000111B

(Continued)

30

MB90880 Series

Register

abbreviation

Address

Register name

R/W

Resource

Initial value

0000BE^H

0000BFH

0000C0H

0000C1H

0000C2H

0000C3H

0000C4H

0000C5H

0000C6H

0000C7H

0000C8H

0000C9H

ICR14

ICR15

CMR0

CAR0

CMR1

CAR1

CMR2

CAR2

CMR3

CAR3

CSCR

CALR

Interrupt control register 14

Interrupt control register 15

Chip select area MASK register 0

Chip select area register 0

W, R/W

R/W

00000111B

00001111B

11111111B

00001111B

11111111B

00001111B

11111111B

00001111B

11111111B

----000*B

Interrupt control

Chip select function

R/W

Chip select area MASK register 1

Chip select area register 1

R/W

Chip select area MASK register 2

Chip select area register 2

R/W

Interrupt control

Chip select area MASK register 3

Chip select area register 3

R/W

Chip select control register

Chip select active level register

R/W

----0000B

0000CAH

to

0000CE^H

Reserved

0000CF^H

0000D0H

0000D1H

0000D2H

0000D3H

0000D4H

0000D5H

0000D6H

0000D7H

PLLOS

BAPL

BAPM

BAPH

MACS

IOAL

PLL output selection register

DMA buffer address pointer (low)

DMA buffer address pointer (middle)

DMA buffer address pointer (high)

DMA control register

W

PLL

------X0B

R/W

XXXXXXXXB

DMAC

DMAI/O register address pointer (low)

DMAI/O register address pointer (high)

DMA data counter (low)

IOAH

DCTL

DCTH

DMA data counter (high)

0000D8H

to

0000DF^H

Reserved

0000E0H

0000E1H

0000E2H

0000E3H

0000E4H

0000E5H

0000E6H

0000E7H

ENIR0

EIRR0

Interrupt/DTP enable register 0

Interrupt/DTP source register 0

Request level setting register 0

Interrupt/DTP enable register 1

Interrupt/DTP source register 1

Request level setting register 1

R/W

00000000^B

XXXXXXXXB

00000000^B

00000000B

XXXXXXXXB

00000000^B

DTP / external

interrupt

ELVR0

ENIR1

EIRR1

DTP / external

interrupt

ELVR1

00000000B

(Continued)

31

MB90880 Series

Register

Address

Register name

R/W

Resource

Initial value

abbreviation

0000E8^H

0000E9H

0000EAH

0000EBH

ENIR2

EIRR2

Interrupt/DTP enable register 2

Interrupt/DTP source register 2

Request level setting register 2

R/W

XXXX0000B

XXXXXXXXB

00000000^B

00000000B

DTP / external

interrupt

ELVR2

0000ECH

to

0000EFH

Reserved

0000F0H

to

External area

RAM area

0000FFH

000100^H

to

#H*

007900^H

007901H

007902H

007903H

007904H

007905H

007906H

007907H

007908H

007909H

00790AH

00790BH

00790CH

00790DH

00790EH

00790FH

007910H

007911H

007912^H

007913H

007914H

007915H

PCNTL0

PCNTH0

PCNTL1

PCNTH1

PCNTL2

PCNTH2

PCNTL3

PCNTH3

PCNTL4

PCNTH4

PCNTL5

PCNTH5

PCNTL6

PCNTH6

PCNTL7

PCNTH7

PPGDIV

PPG0 lower control status register

R/W

00000000B

00000001B

00000000B

00000001B

00000000B

00000001B

00000000B

00000001B

00000000B

00000001B

00000000B

00000001B

00000000B

00000001B

00000000B

00000001B

11111100B

16-bit PPG0

16-bit PPG1

16-bit PPG2

16-bit PPG3

16-bit PPG4

16-bit PPG5

16-bit PPG6

PPG0 higher control status register

PPG1 lower control status register

PPG1 higher control status register

PPG2 lower control status register

PPG2 higher control status register

PPG3 lower control status register

PPG3 higher control status register

PPG4 lower control status register

PPG4 higher control status register

PPG5 lower control status register

PPG5 higher control status register

PPG6 lower control status register

PPG6 higher control status register

PPG7 lower control status register

PPG7 higher control status register

PPG0 output division setting register

16-bit PPG7

16-bit PPG0

Reserved

PDCRL0

PDCRH0

PCSRL0

PCSRH0

11111111B

PPG0 down counter register

PPG0 period setting register

R

16-bit PPG0

W

11111111B

(Continued)

32

MB90880 Series

Register

abbreviation

Address

Register name

R/W

Resource

Initial value

007916^H

PUDUTL0

00000000B

PPG0 duty setting register

W

16-bit PPG0

007917H PUDUTH0

007918H

Disabled

007919^H

00791AH

00791BH

00791CH

00791DH

PDCRL1

PDCRH1

PCSRL1

PCSRH1

11111111B

00000000B

PPG1 down counter register

PPG1 period setting register

PPG1 duty setting register

R

W

16-bit PPG1

16-bit PPG2

16-bit PPG3

16-bit PPG4

00791EH PUDUTL1

00791FH PUDUTH1

007920H

Disabled

007921H

007922H

007923H

007924H

007925H

007926H

PDCRL2

PDCRH2

PCSRL2

PCSRH2

PUDUTL2

11111111^B

11111111B

00000000B

PPG2 down counter register

PPG2 period setting register

PPG2 duty setting register

R

W

007927H PUDUTH2

007928H

Disabled

007929H

00792AH

00792BH

00792CH

00792DH

PDCRL3

PDCRH3

PCSRL3

PCSRH3

11111111^B

11111111B

00000000B

PPG3 down counter register

PPG3 period setting register

PPG3 duty setting register

R

W

00792EH PUDUTL3

00792FH PUDUTH3

007930H

Disabled

007931H

007932^H

007933H

007934H

007935H

007936H

PDCRL4

PDCRH4

PCSRL4

PCSRH4

PUDUTL4

11111111^B

11111111B

00000000B

PPG4 down counter register

PPG4 period setting register

PPG4 duty setting register

R

W

007937H PUDUTH4

00000000B

(Continued)

33

MB90880 Series

Register

Address

Register name

R/W

Resource

Initial value

abbreviation

007938^H

007939H

Disabled

00793A^H

00793BH

00793CH

00793DH

PDCRL5

PDCRH5

PCSRL5

PCSRH5

11111111^B

11111111B

00000000B

PPG5 down counter register

PPG5 period setting register

PPG5 duty setting register

R

W

16-bit PPG5

00793EH PUDUTL5

00793FH PUDUTH5

007940H

Disabled

007941H

007942^H

007943H

007944H

007945H

007946H

PDCRL6

PDCRH6

PCSRL6

PCSRH6

PUDUTL6

11111111^B

11111111B

00000000B

PPG6 down counter register

PPG6 period setting register

PPG6 duty setting register

R

W

16-bit PPG6

007947H PUDUTH6

007948H

Disabled

007949H

00794A^H

00794BH

00794CH

00794DH

PDCRL7

PDCRH7

PCSRL7

PCSRH7

11111111^B

11111111B

00000000B

PPG7 down counter register

PPG7 period setting register

PPG7 duty setting register

R

W

16-bit PPG7

00794EH PUDUTL7

00794FH PUDUTH7

007950H

Disabled

007951^H

007952H

TMCR0

007953H

00000000^B

00000000B

Timer control register ch.0

Status control register ch.0

R/W

Base timer ch.0

007954H

007955H

STC0

Disabled

00000000^B/

XXXXXXXXB

007956H

007957H

TMR0

Timer register ch.0

R/W

00000000B/

XXXXXXXXB

(Continued)

34

MB90880 Series

Register

abbreviation

Address

Register name

R/W

Resource

Initial value

007958^H

007959H

XXXXXXXX^B

XXXXXXXXB

PCSR0/

PRLL0

Period/L-width setting register ch.0

R/W

XXXXXXXX^B/

00000000B

Base timer ch.0

00795AH

00795BH

PDUT0/

PRLH0/

DTBF0

Duty/H-width/data buffer register ch.0

R/W

XXXXXXXXB/

00000000B

00795CH

00795DH

00795EH

00795FH

00000000^B

00000000B

TMCR1

STC1

Timer control register ch.1

Status control register ch.1

R/W

Base timer ch.1

Disabled

00000000^B/

007960^H

007961H

XXXXXXXX^B

TMR1

Timer register ch.1

R/W

00000000B/

XXXXXXXX^B

007962H

007963H

XXXXXXXX^B

XXXXXXXXB

PCSR1/

PRLL1

Period/L-width setting register ch.1

Duty/H-width/data buffer register ch.1

Base timer ch.1

XXXXXXXX^B/

00000000^B

007964H

007965H

PDUT1/

PRLH1/

DTBF1

XXXXXXXXB/

00000000^B

007966H

007967H

007968H

007969H

00000000^B

00000000B

TMCR2

STC2

Timer control register ch.2

Status control register ch.2

R/W

Base timer ch.2

Disabled

00000000^B/

00796A^H

00796BH

XXXXXXXXB

TMR2

Timer register ch.2

R/W

00000000B/

XXXXXXXXB

00796CH

00796DH

XXXXXXXX^B

XXXXXXXXB

PCSR2/

PRLL2

Period/L-width setting register ch.2

Duty/H-width/data buffer register ch.2

Base timer ch.2

XXXXXXXX^B/

00000000^B

00796EH

00796FH

PDUT2/

PRLH2/

DTBF2

XXXXXXXXB/

00000000^B

007970H

007971H

007972H

00000000^B

00000000B

TMCR3

STC3

Timer control register ch.3

Status control register ch.3

R/W

Base timer ch.3

00000000B

(Continued)

35

MB90880 Series

Register

Address

Register name

R/W

Resource

Initial value

abbreviation

007973^H

007974H

Disabled

00000000^B/

XXXXXXXX^B

TMR3

Timer register ch.3

R/W

00000000B/

XXXXXXXX^B

007975H

007976H

007977H

XXXXXXXX^B

XXXXXXXXB

PCSR3/

PRLL3

Period/L-width setting register ch.3

Duty/H-width/data buffer register ch.3

Base timer ch.3

XXXXXXXX^B/

00000000B

007978H

007979H

PDUT3/

PRLH3/

DTBF3

XXXXXXXXB/

00000000B

00797AH

00797BH

00797CH

00797DH

00797EH

00797FH

007980H

007981H

007982H

007983H

UDCR0

UDCR1

RCR0

Up-down count register (ch.0)

R

00000000B

XX00X000B

00000000B

XX00X000B

-0000000B

00000000B

Up-down count register (ch.1)

Reload/compare register (ch.0)

Reload/compare register (ch.1)

Lower counter control register (ch.0)

Higher counter control register (ch.0)

Lower counter control register (ch.1)

Higher counter control register (ch.1)

Counter status register (ch.0)

W

RCR1

W

8/16-bit up-down

counter/timer

CCRL0

CCRH0

CCRL1

CCRH1

CSR0

W, R/W

R/W

W, R/W

R/W

R, R/W

Reserved

8/16-bit up-down

counter/timer

007984H

CSR1

SMR6

Counter status register (ch.1)

Serial bus mode register ch.6

R, R/W

00000000B

007985H

to

00798FH

Reserved

007990^H

R/W

$$$$$$$$B

Serial bus control register / I²C bus

control register ch.6

007991H SCR6/IBCR6

Extended communication control

ESCR6/

007992H

R/W

R,W

$$$$$$$$B

$$$$$$$$^B

register / I²C bus status register ch.6

IBSR6

007993H

007994H

SSR6

Serial status register ch.6

Multi-function serial

ch.6

Transmission/reception data register 0

ch.6

RDR06/

TDR06

Transmission/reception data register 1

ch.6

RDR16/

TDR16

007995H

R,W

$$$$$$$$B

007996H

007997H

BGR06

BGR16

Baud rate generator register 0 ch.6

Baud rate generator register 1 ch.6

R/W

$$$$$$$$B

(Continued)

36

MB90880 Series

Register

abbreviation

Address

Register name

R/W

Resource

Initial value

007998^H

007999H

ISBA6

ISMK6

7-bit slave address register ch.6

R/W

00000000^B

01111111B

Multi-function serial

ch.6

7-bit slave address mask register ch.6

PPG pin switching

control

00799AH

PAFSR

PMSSR

PPG pin assignment switching register

R/W

----0000^B

PPG multi-start

control

00799BH

00799CH

00799DH

PPG multi-channel start register

Reserved

00000000^B

Multi-function serial

pin control

P9FSR

Serial pin switching register 1

R/W

-----000^B

00799CH

to

0079A1^H

Reserved

Multi-function serial

pin control

0079A2^H

0079A3H

P7FSR

LSYNS

Serial pin switching register 0

LIN SYNCH FIELD switching register

Reserved

R/W

----000XB

Input capture input

control

10001000B

0079A4H,

0079A5^H

0079A6^H

0079A7H

FWR0

FWR1

Flash memory write control register 0

Flash memory write control register 1

R/W

00000000B

Flash memory I/F

0079A8H

to

0079DFH

Reserved

0079E0^H

0079E1H

0079E2H

0079E3H

0079E4H

0079E5H

0079E6H

0079E7H

0079E8H

Detection address register 0 (low)

Detection address register 0 (middle)

Detection address register 0 (high)

Detection address register 1 (low)

Detection address register 1 (middle)

Detection address register 1 (high)

Detection address register 2 (low)

Detection address register 2 (middle)

Detection address register 2 (high)

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

Address match

PADR0

PADR1

PADR2

R/W

detection function

Address match

detection function

Address match

detection function

0079E9H

to

0079EF^H

Reserved

0079F0H

0079F1H

0079F2H

Detection address register 3 (low)

Detection address register 3 (middle)

Detection address register 3 (high)

XXXXXXXX^B

XXXXXXXXB

Address match

detection function

PADR3

R/W

XXXXXXXXB

(Continued)

37

MB90880 Series

(Continued)

Register

Address

Register name

R/W

Resource

Initial value

abbreviation

0079F3^H

0079F4H

0079F5H

0079F6H

0079F7H

0079F8H

Detection address register 4 (low)

Detection address register 4 (middle)

Detection address register 4 (high)

Detection address register 5 (low)

Detection address register 5 (middle)

Detection address register 5 (high)

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

Address match

PADR4

PADR5

R/W

detection function

Address match

detection function

R/W

0079F9H

to

007FFFH

Reserved

Explanation on R/W

R/W : Readable/Writable

R

W

: Read only

: Write only

Explanation on initial value

0

1

X

-

: The initial value of this bit is “0”.

: The initial value of this bit is “1”.

: The initial value of this bit is undefined.

: This bit is not used.

*

: The initial value of this bit is “1” or “0”.

It varies depending on the mode pin (MD2, MD1 or MD0 pin) .

: The initial value of this bit is “1” or “0”.

: The initial value of this bit varies depending on the operation mode of the resource.

+

$

#H* : Varies depending on the RAM area of the device.

38

MB90880 Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL

REGISTERS

Interrupt control

register

µDMAC

channel

no.

Interrupt vector

Clearing

of EI²OS

Interrupt source

No.

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

Address

FFFFDC^H

FFFFD8H

FFFFD4H

FFFFD0^H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

No.

⎯

Address

Reset

×

⎯

0

⎯

INT9 instruction

⎯

Exception

⎯

INT0 (IRQ0/1)

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

INT0 (IRQ2 to IRQ7)

×

INT0 (IRQ8 to IRQ15)

INT0 (IRQ16 to IRQ23)

Base timer ch.0 (source 0,1)

Base timer ch.1 (source 0,1)

Base timer ch.2 (source 0,1)

Base timer ch.3 (source 0,1)

PPG0/PPG4 counter borrow

PPG1/PPG5 counter borrow

PPG2/PPG6 counter borrow

PPG3/PPG7 counter borrow

×

1

2

3

4

5

6

7

×

8

8/16-bit up-down counter/timer (ch.0/1)

compare / underflow / overflow / up-down

inversion

×

#23

FFFFA0H

ICR06

0000B6H

Input capture retrieval (ch.0/1)

Output compare (ch.0/1/2) match

Output compare (ch.3/4/5) match

A/D converter

×

#24

#25

#26

#27

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

ICR07

ICR08

ICR09

0000B7H

0000B8H

0000B9H

Overflow in 16-bit free-run timer / compare

clear / multi-function serial ch.4/5/6 status

9

#28

FFFF8CH

Multi-function serial ch.4 reception

Multi-function serial ch.4 transition

Multi-function serial ch.5 reception

Multi-function serial ch.5 transition

Multi-function serial ch.6 reception

Multi-function serial ch.6 transition

Multi-function serial ch.0/1 reception / status

Multi-function serial ch.0/1 transmission

Multi-function serial ch.2 reception / status

Multi-function serial ch.2 transmission

10

11

12

13

14

15

×

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF70H

FFFF6CH

FFFF68H

FFFF64H

ICR10 0000BAH

ICR11 0000BBH

ICR12 0000BCH

×

ICR13 0000BDH

×

(Continued)

39

MB90880 Series

(Continued)

Interrupt control

register

µDMAC

channel

no.

Interrupt vector

Clearing

of EI²OS

Interrupt source

No.

#39

#40

Address

FFFF60^H

FFFF5CH

No.

Address

Multi-function serial ch.3 reception / status

Multi-function serial ch.3 transmission

×

ICR14 0000BEH

Flash writing/deletion, time base timer, watch

timer*

×

#41

#42

FFFF58H

FFFF54H

ICR15 0000BFH

Delayed interrupt generation module

×

: The interrupt request flag is not cleared by the interrupt clear signal.

: The interrupt request flag is cleared by the interrupt clear signal.

: Theinterruptrequestflagisclearedbytheinterruptclearsignal. Stoprequestfunctionprovidedatreceiving

only.

* : Flash writing/deletion, the time base timer and watch timer cannot be used simultaneously.

Note : If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are

cleared by the EI²OS/µDMAC interrupt clear signal. Therefore, when either of the two sources for the EI²OS/

µDMAC function is used, the other interrupt function can not be used. In this case, set the interrupt request

enable bit to “0” in the appropriate resource and take measures by software polling.

40

MB90880 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute maximum ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

VSS + 4.0

VSS + 7.0

VSS + 4.0

VSS + 7.0

+2.0

VCC

DV^CC

AVCC

AVRH

VSS − 0.3

V

VSS − 0.3

DVcc = Vcc*²

Power supply voltage^*1

VSS − 0.3

V

*2

V^SS− 0.3

V

*2

VSS − 0.3

V

*3

Input voltage^*1

VI

V^SS− 0.3

V

*3, *8

VSS − 0.3

V^SS− 0.3

− 2.0

⎯

V

*3

Output voltage^*1

VO

V

*3, *8

Maximum clamp current

I^CLAMP

Σ⏐I^CLAMP⏐

I^OL1

mA

mW

°C

*7

Total maximum clamp current

20

*7

⎯

10

*4

“L” level maximum output cur-

rent

I^OL2

⎯

20

PA0 to PA3*⁴

I^OLAV1

I^OLAV2

ΣI^OL1

ΣI^OL2

ΣI^OLAV1

ΣI^OLAV2

I^OH1

⎯

3

*5

“L” level average output current

⎯

10

PA0 to PA3*⁵

⎯

60

“L” level maximum total output

current

⎯

80

PA0 to PA3

*6

PA0 to PA3*⁶

⎯

30

“L” level average total output

current

⎯

40

⎯

−10

*4

“H” level maximum output

current

I^OH2

⎯

−20

PA0 to PA3*⁴

*5

PA0 to PA3*⁵

I^OHAV1

I^OHAV2

ΣI^OH1

ΣI^OH2

ΣI^OHAV1

ΣI^OHAV2

PD

⎯

−3

“H” level average output current

⎯

−10

⎯

−60

“H” level maximum total output

current

⎯

−80

PA0 to PA3

*6

PA0 to PA3*⁶

⎯

−30

“H” level average total output

current

⎯

−40

Power consumption

Operating temperature

Storage temperature

⎯

320

T^A

−40

−55

+85

Tstg

+150

°C

*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.

*2 : Set AVCC, DVCC and AVRH to the same voltage. AVCC and DVCC must not exceed VCC. Also, AVRH must not

exceed AVCC.

*3 : VI and VO must not exceed 0.3V. When the maximum current to/from an input is limited by using an external

component, the ICLAMP rating supersedes the VI rating.

*4 : The maximum output current is defined as the peak value of the current of any one of the corresponding pins.

(Continued)

41

MB90880 Series

(Continued)

*5 : The average output current is defined as the value of the average current flowing over 100 ms at any one of

the corresponding pins.

*6 : The average total output current is defined as the value of the average current flowing over 100 ms at all of the

corresponding pins.

*7 : • Relevant pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,

P70 to P76, P80 to P87, P90 to P97, PA0 to PA3

• Use within recommended operating conditions.

• Use with DC voltage (current) .

• The + B signal should always be applied with a limiting resistance placed between the + B signal and the

microcontroller.

• Set the limiting resistor value, whether instantaneous or stationary, so that the current to be input to the

microcontroller pin does not exceed the rating during the input of the + B signal.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the + B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this may

affect other devices.

• Note that if a + B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply

is provided from the pins, so that incomplete operation may result.

• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the + B input pin open.

• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept + B

signal input.

• Sample recommended circuit :

• Input/Output equivalent circuit

Protective diode

V^CC

Limiting

P-ch

resistance

+ B input (0V to 16V)

N-ch

R

*8 : P74 to P76 and P80 to P87 can be used as 5V I/F pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed any of these ratings.

42

MB90880 Series

2. Recommended operating conditions

(VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

2.7

1.8

Max

3.6

V

In normal operation

Hold stop status

V^CC

DVcc

Power supply voltage

3.6

All pins other than VIH2, VIHS,

VIHM and VIHX

V^IH

0.7 VCC

VCC + 0.3

V

VIH2

0.7 VCC

0.8 VCC

VSS + 5.8

VCC + 0.3

V

P74 to P76, P80 to P87

Hysteresis input pins

V^IHS

Hysteresis input pins

(multi-function serial pins)

“H” level input voltage

VIHS2

0.7 VCC

VCC + 0.3

V

CMOS input pins (external

bus mode input pins)

V^IHS3

VIHM

VCC − 0.3

VCC + 0.3

V

MD pin input

V^IHX

0.8 VCC

X0A and X1A pins

All pins other than VILS, VILM

and VIHX

VIL

VILS

V^ILS2

VSS − 0.3

0.3 VCC

0.2 VCC

0.3 VCC

V

Hysteresis input pins

(multi-function serial pins)

“L” level input voltage

CMOS input pins (external

bus mode pins)

VILS3

VSS − 0.3

0.3 VCC

V

V^ILM

VSS − 0.3

VSS + 0.3

V

MD pin input

VILX

0.1

X0A and X1A pins

Use a ceramic capacitor or

comparable capacitor of the

AC characteristics. Bypass

capacitor at the VCC pin

should be greater than this

capacitor.

Smoothing capacitor

C^S

T^A

0.1

1.0

µF

°C

Operating temperature

−40

+85

• C Pin Connection Diagram

C

CS

43

MB90880 Series

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is

operated within these ranges. Always use semiconductor devices within their recommended operating

condition ranges. Operation outside these ranges may adversely affect reliability and could result in

device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

44

MB90880 Series

3. DC characteristics

(VCC = 2.7V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter Symbol Pin name

Conditions

Unit Remarks

Min

Typ

Max

All pins

except

P74 to P76, V^CC= 3.0 V,

P80 to P87

and

V^CC− 0.5

⎯

V

I^OH= −4.0 mA

“H” level

output

V^OH

PA0 to PA3

voltage

P74 to P76, V^CC= 3.0 V,

V^CC− 0.5

⎯

V

P80 to P87

I^OH= −2.0 mA

DV^CC= 3.0 V,

I^OH= −10.0 mA

PA0 to PA3

DV^CC− 0.6

All pins

except

P74 to P76, V^CC= 3.0 V,

P80 to P87

and

⎯

0.4

V

I^OL= 4.0 mA

“L” level

output

V^OL

PA0 to PA3

voltage

P74 to P76, V^CC= 3.0 V,

⎯

50

0.4

0.5

V

P80 to P87

I^OH= −2.0 mA

DV^CC= 3.0 V,

I^OL= 10.0 mA

PA0 to PA3

Input leak

current

V^CC= 3.3 V,

V^SS< VI < VCC

I^IL

All input pins

−10

25

+10

100

µA

kΩ

Evaluation

version

Flash

memory

kΩ version /

Pull-up

resistance

R^PULL

⎯

15

33

66

10

MASKROM

version

P31, P32,

P34, P35,

P43, P44,

P46, P47,

P72 to P76,

P80 to P87,

P96, P97

Open-drain

output

current

I^leak

⎯

0.1

µA

(Continued)

45

MB90880 Series

(Continued)

(V^CC= 2.7V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Min

Typ

Max

V^CC= 3.3V;

Normal internal 25 MHz

operation

⎯

20

28

mA

VCC = 3.3V;

Normal internal 33 MHz

operation

⎯

28

30

38

40

52

12

20

0.9

mA

I^CC

⎯

V^CC= 3.3V;

Internal 25 MHz

operation; flash write

V^CC= 3.3V;

Internal 33 MHz

operation; flash write

40

V^CC= 3.3V;

Internal 25 MHz

operation; sleep mode

6

I^CCS

⎯

V^CC= 3.3V;

Internal 33 MHz

operation; sleep mode

10

Supply current

V^CC= 3.3 V;

Internal 2 MHz,

operation; Time-base timer

ICTS

⎯

0.25

V^CC= 3.3V;

External 32 kHz & internal

8 kHz operation;

sub-operation

I^CCL

⎯

80

50

20

200

160

110

µA

(TA = + 25 °C)

V^CC= 3.3 V;

External 32 MHz,

Internal 8 MHz operation;

sub sleep mode (T^A= +25 °C)

ICCLS

⎯

V^CC= 3.3V;

External 32 kHz & internal

8 kHz operation; watch

operation

I^CCT

⎯

(T^A= + 25 °C)

TA = + 25 °C;

Stop mode; VCC = 3.3V

ICCH

⎯

15

5

100

15

µA

All pins except

AVCC, AVSS,

VCC, DVCC,

VSS, DVSS

Input

capacitance

C^IN

AVCC, AVSS, VCC, DVCC, VSS, DVSS

pF

Note : P74 to P76 and P80 to P87 are N-ch open-drain pins with controls and normally used at the CMOS level.

46

MB90880 Series

4. AC characteristics

(1) Clock timing ratings

(VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Typ

Condi-

tions

Parameter

Clock frequency

Clock cycle time

Symbol Pin name

Unit

Remarks

Min

Max

External crystal

oscillation

⎯

3

⎯

25

⎯

3

4

⎯

50

25

External clock input

PLL1 multiplication

PLL2 multiplication

PLL3 multiplication

PLL4 multiplication

PLL6 multiplication

PLL8 multiplication

3

⎯

12.5

6.66

6.25

5.5

F^CH

X0, X1

MHz

kHz

3

⎯

3

⎯

3

⎯

3

⎯

4.125

⎯

F^CL

t^C

X0A, X1A

X0, X1

⎯

15.15

⎯

32.768

⎯

333

⎯

ns *1

tCL

X0A, X1A

30.5

µs

PWH

PWL

X0

X0A

X0

⎯

5

⎯

15.2

⎯

5

ns

Input clock pulse width

Input clock rise/fall time

PWLH

PWLL

⎯

µs *2

External clock in

use

tcr

tcf

ns

fCP

fCPL

t^CP

⎯

1.5

⎯

33

⎯

MHz *1

kHz

Internal operating clock

frequency

8.192

⎯

30.3

⎯

666

⎯

ns *1

µs

Internal operating clock

cycle time

tCPL

122.1

*1 : Observe the operating voltage with care.

The maximum operating frequency is 25 MHz in MB90F883(S) and MB90F884(S).

*2 : Input it at a duty ratio of 50% 3%.

• X0, X1 clock timing

t

C

0.8 VCC

0.2 VCC

X0

P

WH

PWL

t

cf

tcr

47

MB90880 Series

• X0A, X1A clock timing

X0A

tCL

0.8 VCC

0.1 VCC

PWLH

PWLL

tcf

tcr

48

MB90880 Series

• PLL warranted operating range

Internal operating clock frequency vs. Supply voltage

3.6

PLL warranted operating range

3.0

2.7

Normal operating range

16

1.5

4

33

Internal clock fCP (MHz) *⁴

Notes: • Use the f^CPat 4 MHz or higher only for PLL1 multiplication.

• For A/D operating frequencies, refer to “5. A/D Converter electrical characteristics”.

Source oscillator frequency vs. Internal operating clock frequency

33

8 Multi-

plication*³

3 Multi-

plication*¹

25

24

No multiplication

6 Multi-

plica-

tion*³

20

18

16

1 Multiplication*¹

2 Multi-

2

plication*^1,

*

4 Multi-

plica-

tion

1,

2

*

12

9

8

6

4

1.5

3 4 5 6 8 10 12.5 16

20

25

32

40

50

Source oscillator clock F^CH(MHz)

*1 :

When using the internal clock at “20 MHz < fCP ≤ 25 MHz” in PLL1, 2, 3 or 4 multiplication setting, set both of

the DIV2 and PLL2 bits to “1” in the PLLOS register.

Example : When the source oscillator frequency is 24 MHz in PLL1 multiplication :

CKSCR register : CS1 = “0”, CS0 = “0”

PLLOS register : DIV2 = “1”, PLL2 = “1”

Example : When the source oscillator frequency is 6 MHz in PLL3 multiplication :

CKSCR register : CS1 = “1”, CS0 = “0”

PLLOS register : DIV2 = “1”, PLL2 = “1”

*2 :

*3 :

When using the internal clock at “20 MHz < fCP ≤ 25 MHz” in PLL 2 or 4 multiplication setting, the following

settings can also be used.

PLL2 multiplication : CKSCR register : CS1 = “0”, CS0 = “0”

PLLOS register : DIV2 = “0”, PLL2 = “1”

PLL4 multiplication CKSCR register : CS1 = “0”, CS0 = “1”

PLLOS register : DIV2 = “0”, PLL2 = “1”

When using the PLL6 or 8 multiplication setting, set DIV2 to “0” and PLL2 to “1” in the PLLOS register.

Example : When the source oscillator frequency is 4 MHz in PLL6 multiplication :

CKSCR register : CS1 = “1”, CS0 = “0”

PLLOS register : DIV2 = “0”, PLL2 = “1”

Example : When the source oscillator frequency is 3 MHz in PLL8 multiplication :

CKSCR register : CS1 = “1”, CS0 = “1”

PLLOS register : DIV2 = “0”, PLL2 = “1”

*4 :

The maximum operating frequency of MB90F883(S) and MB90F884(S) is 25 MHz.

49

MB90880 Series

AC characteristics are determined using the following measurement reference voltage values.

• Input signal waveform

Hysteresis input pins

• Output signal waveform

Output pins

0.8 VCC

0.2 VCC

2.4 V

0.8 V

Pins other than hysteresis input/MD input pins

0.7 VCC

0.3 VCC

50

MB90880 Series

(2) Clock output timing

(V^SS= 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Cycle time

Symbol Pin name

Conditions

Unit

Remarks

Min

Max

t^CYC

CLK

⎯

tCP*

⎯

ns

V^CC= 3.0 V to 3.6 V tCP* / 2 − 15 tCP* / 2 + 15

V^CC= 2.7 V to 3.3 V tCP* / 2 − 20 tCP* / 2 + 20

VCC = 2.7 V to 3.3 V tCP* / 2 − 64 tCP* / 2 + 64

fCP = 25 MHz

fCP = 16 MHz

fCP = 5 MHz

CLK↑ → CLK↓

t^CHCL

* : t^CPis the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

tCYC

t

CHCL

2.4 V

0.8 V

CLK

51

MB90880 Series

(3) Reset input ratings

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Condi-

tions

Parameter

Symbol

Unit

Remarks

name

Min

Max

In normal

operation

16 t^CP*¹

⎯

ns

In sub clock,

sub-sleep,

watch and stop

modes

Oscillator oscillation time *²

Reset input time

t^RSTL

RST

⎯

ms

+ 100 µs + 16 t^CP*¹

In time base

timer mode

100

µs

*1 : t^CPis the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

*2 : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several

tens of ms; for a ceramic oscillator, this is several hundred ms to a few ms, and for an external clock this is 0 ms.

• In sub clock, sub-sleep, watch and stop modes

t

RSTL

RST

0.2 VCC

90% of amplitude

X0

Internal operation

clock

100 µs +

16 t^CP

Oscillator

oscillation

time

Oscillation stabilization

wait time

Execution of instruction

Internal reset

• Measurement conditions for AC ratings

CL : Load capacitance applied to pin during testing

CLK, ALE : CL = 30 pF

AD15 to AD00 (Address, data bus) , RD, WR,

A23 to A00/D15 to D00 : C^L= 30 pF

CL

52

MB90880 Series

(4) Power-on ratings (Power-on reset)

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name

Conditions

Unit

Remarks

Min

Max

Power rise time

t^R

VCC

0.05

30

ms

*

⎯

For continuous

operation

Power cutoff time

t^OFF

1

⎯

* : During the power rise time, V^CCmust be less than 0.2V.

Notes : • The above ratings are values used for power-on reset.

• A power-on reset should be applied by restarting the power supply inside the device.

tR

2.7 V

VCC

0.2 V

tOFF

A sudden change in the supply voltage may activate a power-on reset.

As shown in the following figure, it is recommended to apply a smooth voltage rise with

suppressed fluctuation when changing the supply voltage during operation.

Main power

voltage

VCC

A rise slope of 50mV/ms or less

is recommended.

Sub supply voltage

RAM data held

VSS

53

MB90880 Series

(5) Bus read timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)

Value

Condi-

tions

Parameter

Symbol Pin name

Unit

Remarks

Min

Max

16 MHz < fCP ≤

t^CP* / 2 − 15

⎯

ns

25 MHz

ALE pulse width

t^LHLL

ALE

⎯

8 MHz < fCP ≤

16 MHz

t^CP* / 2 − 20

⎯

t^CP* / 2 − 35

t^CP* / 2 − 17

t^CP* / 2 − 40

⎯

ns fCP ≤ 8 MHz

ns

Valid address →

ALE↓ time

Address,

ALE

t^AVLL

⎯

ns fCP ≤ 8 MHz

ALE ↓ →

ALE,

tLLAX

tAVRL

⎯

tCP* / 2 − 15

t^CP* − 25

⎯

ns

address

valid address time

valid address →

RD↓ Time

RD,

address

⎯

5 t^CP* / 2 − 55 ns

Valid address →

Address /

data

t^AVDV

tRLRH

tRLDV

⎯

valid data input

5 tCP* / 2 − 80 ns fCP ≤ 8 MHz

16 MHz < fCP ≤

3 t^CP* / 2 − 25

3 tCP* / 2 − 20

⎯

ns

25 MHz

RD pulse width

RD

8 MHz < fCP ≤

16 MHz

⎯

3 t^CP* / 2 − 55 ns

3 tCP* / 2 − 80 ns fCP ≤ 8 MHz

RD↓ →

valid data input

RD, data

RD↑→

tRHDX

tRHLH

tRHAX

RD, data

RD, ALE

⎯

0

⎯

ns

data hold time

RD↑ → ALE↑ time

tCP* / 2 − 15

tCP* / 2 − 10

RD↑ →

valid address time

Address,

RD

Valid address →

CLK↑ time

Address,

CLK

t^AVCH

⎯

tCP* / 2 − 17

⎯

ns

RD↓ → CLK↑ time

ALE↓ → RD↓ time

tRLCH

tLLRL

RD, CLK

RD, ALE

⎯

tCP* / 2 − 17

tCP* / 2 − 15

⎯

ns

* : t^CPis the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

54

MB90880 Series

t

AVCH

t

RLCH

2.4 V

CLK

ALE

RD

t

RHLH

2.4 V

0.8 V

2.4 V

t

LHLL

t

RLRH

2.4 V

t

AVLL

tLLAX

0.8 V

t

LLRL

Multiplex mode

t

AVRL

t

RLDV

tRHAX

2.4 V

A23 to A16

0.8 V

t

AVDV

t

RHDX

2.4 V

0.8 V

0.7 VCC

Read data

Address

AD15 to AD00

0.8 V

0.3 VCC

t

RHAX

Non-multiplex mode

2.4 V

0.8 V

A23 to A00

0.8 V

t

RLDV

t

RHDX

t

AVDV

0.7 VCC

Read data

D15 to D00

0.3 VCC

55

MB90880 Series

(6) Bus write timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)

Value

Condi-

tions

Parameter

Symbol Pin name

Unit

Remarks

Min

Max

Valid address → WR ↓

Address,

WR

tAVWL

tWLWH

tDVWH

⎯

tCP* − 15

⎯

ns

time

16 MHz < fCP ≤

3 tCP* / 2 − 25

3 t^CP* / 2 − 20

3 tCP* / 2 − 15

10

⎯

25 MHz

WR pulse width

WRL, WRH

8 MHz < fCP ≤ 16

MHz

Valid data output → WR↑

time

Data,

WR

16 MHz < fCP ≤

25 MHz

WR↑ → data hold time

tWHDX

tWHAX

WR, data

8 MHz < f^CP≤ 16

MHz

⎯

20

30

⎯

ns f^CP≤ 8 MHz

WR,

address

WR↑ → valid address time

tCP* / 2 − 10

ns

WR↑ → ALE↑ time

WR↓ → CLK↑ time

tWHLH

tWLCH

WR, ALE

WR, CLK

⎯

tCP* / 2 − 15

tCP* / 2 − 17

⎯

ns

* : t^CPis the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

56

MB90880 Series

t

WLCH

2.4 V

CLK

ALE

t

WHLH

2.4 V

t

WLWH

2.4 V

WR

(WRL, WRH)

0.8 V

Multiplex mode

t

AVWL

tWHAX

2.4 V

A23 to A16

0.8 V

t

DVWH

t

WHDX

2.4 V

Write data

Address

AD15 to AD00

0.8 V

t

WHAX

Non-multiplex mode

2.4 V

0.8 V

A23 to A00

0.8 V

t

DVWH

t

WHDX

2.4 V

Write data

D15 to D00

0.8 V

57

MB90880 Series

(7) Ready input timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)

Value

Parameter

Symbol Pin name

Conditions

Unit

Remarks

Min

35

70

0

Max

⎯

ns

RDY setup time

RDY hold time

t^RYHS

t^RYHH

RDY

⎯

fCP = 8 MHz

⎯

2.4 V

CLK

ALE

RD/WR

tRYHS

tRYHH

When

RDY wait is

not applied

0.8 VCC

When

RDY wait is

applied

(1 cycle)

0.2 VCC

0.2 V^CC

tRYHS

58

MB90880 Series

(8) Hold timing

Parameter

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)

Value

Symbol

Pin name

Conditions

Unit

Min

30

Max

t^CP*

Pin floating → HAK↓

time

tXHAL

tHAHV

HAK

ns

⎯

HAK↓ → valid pin time

tCP*

2 tCP*

* : t^CPis the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

Note : It takes one or more cycles from when the HRQ pin is read to when HAK changes.

HAK

2.4 V

0.8 V

tXHAL

tHAHV

High-Z

2.4 V

0.8 V

2.4 V

0.8 V

Pins

59

MB90880 Series

(9) Multi-function serial timing (UART, SIO)

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name

Conditions

Unit

Min

8 t^CP*²

−50

50

Max

⎯

Serial clock cycle time

UCK↓ → UO delay time

Valid UI → UCK↑

t^SCYC

t^SLOV

t^IVSH

tSHIX

t^SHSL

t^SLSH

tSLOV

t^IVSH

tSHIX

⎯

ns

Internal shift clock mode

output pin :

+50

⎯

C^L*¹= 80 pF + 1 TTL

UCK↑ → valid UI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

UCK↓ → UO delay time

Valid UI → UCK↑

0

⎯

4 t^CP*²

4 tCP*²

⎯

External shift clock mode

output pin :

50

⎯

C^L*¹= 80 pF + 1 TTL

50

UCK↑ → valid UI hold time

50

⎯

*1 : C^Lis the load capacitance applied to pins during testing.

*2 : t^CPis the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

Note : The above AC characteristics are for CLK synchronous mode operation.

• Internal shift clock mode

tSCYC

UCK

2.4 V

0.8 V

t

0.8 V

SLOV

2.4 V

0.8 V

UO

UI

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

• External shift clock mode

UCK

tSLSH

tSHSL

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

UO

UI

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

60

MB90880 Series

(10) Multi-function serial timing (I²C)

a. Master mode operation

(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

High-speed

Standard mode

mode*³

Condi-

tions

Parameter

SCL clock frequency

Symbol

Unit

Min

0

Max

100

⎯

Min

0

Max

400

⎯

f^SCL

t^LOW

tHIGH

kHz

µs

SCL clock “L” width

SCL clock “H” width

4.7

4.0

4.7

4.0

⎯

µs

Bus-free time between “stop”

condition and “start” condition

t^BUS

4.7

⎯

1.3

0.6

⎯

µs

ns

Repeat “start” condition setup time

SCL↑ → SDA↓

t^SUSTA

t^HDSTA

tSUSTO

tHDDAT

t^SUDAT

R=1kΩ

C=50pF*⁴

(Repeat) “start” condition hold time

SDA↓ → SCL↓

4.0

0.6

“Stop” condition setup time

SCL↑ → SDA↑

4.0

0.6

Data hold time

SCL↓ → SDA↓↑

2tcp*¹

250

2tcp*¹

100*²

Data setup time

SDA↓↑ → SCL↑

61

MB90880 Series

b. Slave mode operation

Parameter

(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

High-speed mode

Standard mode

3

Condi-

tions

*

Symbol

Unit

Min

0

Max

100

⎯

Min

0

Max

400

⎯

SCL clock frequency

SCL clock “L” width

SCL clock “H” width

f^SCL

t^LOW

t^HIGH

kHz

µs

4.7

4.0

1.3

0.6

⎯

µs

Bus-free time between “stop”

condition and “start” condition

tBUS

4.7

⎯

1.3

0.6

⎯

µs

ns

Repeat “start” condition setup time

SCL↑ → SDA↓

t^SUSTA

t^HDSTA

t^SUSTO

tHDDAT

t^SUDAT

R=1kΩ

C=50pF*⁴

(Repeat) “start” condition hold time

SDA↓ → SCL↓

4.0

0.6

“Stop” condition setup time

SCL↑ → SDA↑

4.0

0.6

Data hold time

SCL↓ → SDA↓↑

2tcp*¹

250

2tcp*¹

100*²

Data setup time

SDA↓↑ → SCL↑

*1 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

*2 : The high-speed mode I²C bus device can be used in a standard mode I²C bus system. However, the device

must satisfy the required condition “tSUDAT ≥ 250 ns”. If the device does not extend the “L” period of the SCL

signal, the succeeding data must be output to the SDA line before a period of 1250 ns (the maximum time of

SDA/SCL rise + tSUDAT) in which the SCL line is open.

*3 : Set the internal operation clock to 6MHz or higher when using this over 100kHz.

*4 : “R” and “C” are the pull-up resistance and load capacitance of the SCL/SDA lines.

62

MB90880 Series

• Note on SDA/SCL setup time

SDA

Input data setup time

SCL

6 tcp

Note: Thespecificationfortheinputdatasetuptimeofthe devicewhichisconnectedtothebusmaynotbesatisfied,

depending on the load capacitance and pull-up resistance.

If the specification of the input data setup time can not be satisfied, adjust the pull-up resistance of SDA and

SCL.

• Timing definition

SDA

tBUS

tHDSTA

tSUDAT

tLOW

SCL

tHDSTA

tSUSTA

tHIGH

tSUSTO

tHDDAT

fSCL

63

MB90880 Series

(11) Timer input timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

t^TIWH

tTIWL

IN0, IN1,

TIO0 to TIO3

Input pulse width

⎯

4 t^CP*

⎯

ns

*: t^CPis the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

0.8 VCC

IN0, IN1

TIO0 to TIO3

0.2 VCC

t

TIWH

tTIWL

(12) Timer output timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

CLK↑ → change time

PPG0 to PPG5 change

time

OUT0 to OUT5 change

time

PPG0 to PPG7,

OUT0 to OUT5,

TIO0 to TIO3

Load

condition :

80 pF

t^TO

30

⎯

ns

0.7 VCC

CLK

PPG0 to PPG7

OUT0 to OUT5

TIO0 to TIO3

0.7 VCC

0.3 VCC

tTO

64

MB90880 Series

(13) Trigger input timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min

5 t^CP*

1

Max

⎯

ns In normal operation

tTRGH

tTRGL

ADTG,

IRQ0 to IRQ7

Input pulse width

⎯

µs In stop mode

*: t^CPis the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

0.8 VCC

IRQ0 to IRQ7

ADTG

0.2 VCC

tTRGH

tTRGL

65

MB90880 Series

(14) Chip select output timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

Chip select output valid time

→ RD↓

CS0 to CS3,

RD

tSVRL

tSVWL

tRHSV

tWHSV

⎯

tCP* / 2 − 7

⎯

ns

Chip select output valid time

→ WR↓

CS0 to CS3,

WRH, WRL

tCP* / 2 − 7

t^CP* / 2 − 17

tCP* / 2 − 17

⎯

RD↑ →

Chip select output valid time

RD,

CS0 to CS3

WR↑ →

Chip select output valid time

WRH, WRL,

CS0 to CS3

*: t^CPis the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.

t

SVRL

2.4 V

RD

0.8 V

t

RHSV

2.4 V

A23 to A16

CS0 to CS3

0.8 V

2.4 V

D15 to D00

Read data

0.8 V

t

SVWL

tWHSV

2.4 V

WRH, WRL

D15 to D00

0.8 V

Un-

defined

Write data

Note : The chip select output signal changes simultaneously due to the internal bus configuration; therefore, this

may generate a bus wait. AC cannot be warranted between the ALE output signal and the chip select output

signal.

66

MB90880 Series

5. A/D converter electrical characteristics

(VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH, TA = −40 °C to +85 °C)

Value

Parameter

Resolution

Symbol

Unit Remarks

name

Min

Standard

Max

10

⎯

bit

Total error

⎯

3.0

2.5

LSB

Linear error

⎯

Differential linear

error

⎯

1.9

LSB

V

Zero transition

voltage

AN0 to

AN7

V^OT

V^FST

AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB

AVRH − 3.5 LSB AVRH − 1.5 LSB AVRH + 0.5 LSB

Full-scale transition

voltage

AN0 to

AN7

V

Sampling time

Compare time

Conversion time

t^SMP

t^CMP

tCNV

⎯

1.2

1.8

3.0

⎯

µs *1

Analog port input

current

AN0 to

AN7

IAIN

− 3.0

⎯

+ 3.0

µA

AN0 to

AN7

Analog input voltage

Reference voltage

V^AIN

AVSS

AVRH

V

⎯

I^A

AVRH

AVCC

AVRH

AV^SS+ 2.2

⎯

1.9

⎯

AVCC

3.7

5^*2

V

⎯

mA

µA

Supply current

I^AH

IR

520

⎯

720

5^*2

Reference voltage

supply current

IRH

Inter-channel

variation

AN0 to

AN7

⎯

4

LSB

*1 : Time per channel

*2 : Current when the A/D converter is not in operation and the CPU is stopped (V^CC= AVCC = AVRH = 3.0 V )

67

MB90880 Series

• External impedance and sampling time for analog input

This is an A/D converter with a sample hold function. If high external impedance is preventing it from securing

sufficient sampling time, a sufficient analog voltage will not be charged in the internal sample hold capacitor,

affecting the accuracy of the A/D conversion. In order to satisfy the A/D conversion accuracy specifications,

adjust the register values and operating frequency or decrease the external impedance so that the sampling

time becomes longer than the minimum value, based on the relationship between the external impedance and

the minimum sampling time. If a sufficient sampling time cannot be secured, connect a capacitor with a ca-

pacitance of approximately 0.1 µF to the analog input pin.

Model diagram of analog input circuit

R

Analog input

Comparator

C

Turned on during sampling ON

R

C

12.2kΩ (Max)

8.5pF (Max)

Note : These are reference values.

• Relation between external impedance and minimum sampling time

[External impedance = 0 kΩ to 100 kΩ]

[External impedance = 0 kΩ to 20 kΩ]

Flash memory device

MASK ROM device

Flash memory device

MASK ROM device

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

6

4

2

0

1

2

3

4

5

6

7

8

0

5

10

15

20

25

30

35

Minimum sampling time [µs]

• Errors :

As | AVRH⎯AV^SS| decreases, the absolute error increases.

68

MB90880 Series

6. Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

Non linearity

error

: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )

and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion

characteristics.

Differential

linearity error

: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

value.

Total error

: Difference between an actual value and a theoretical value. A total error includes zero tran-

sition error, full-scale transition error, and linear error.

Total error

3FFH

1.5 LSB

3FEH

Actual conversion

characteristics

3FDH

{1 LSB × (N − 1) + 0.5 LSB}

004H

003H

002H

001H

V^NT

(Actual measurement value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

[LSB]

Total error of digital output “N” =

1 LSB

AVRH − AV^SS

1 LSB (Ideal value) =

[V]

1024

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVRH − 1.5 LSB [V]

V^NT: A voltage at which digital output transits from (N − 1) H, NH.

(Continued)

69

MB90880 Series

(Continued)

Linearity error

Differential linearity error

Ideal

characteristics

3FFH

Actual conversion

characteristics

3FEH

(N + 1)^H

Actual conversion

characteristics

{1 LSB × (N − 1)

+ V^OT

}

3FDH

VFST (actual

measurement

value)

NH

V

NT (actual

measurement value)

004H

003H

002H

001H

V

(N + 1) T

Actual conversion

characteristics

(actual measurement

value)

(N − 1)H

(N − 2)H

V

NT

(actual measurement value)

Actual conversion

characteristics

Ideal characteristics

V

OT (actual measurement value)

AVSS

AVRH

AVSS

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + VOT}

[LSB]

Non linearity error of digital output N =

1 LSB

V (^N+1) T − VNT

−1 LSB [LSB]

1 LSB

Differential linearity error of digital output N =

1 LSB =

VFST − VOT

[V]

1022

V^OT: Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

• Flash memory write/erase characteristics

Value

Parameter

Conditions

Unit

Remarks

Min

Standard

Max

Excludes internal write time before

erase operation.

Sector erase time

Chip erase time

⎯

0.9

6.2

23

⎯

3.6

s

Excludes internal write time before

erase operation.

T^A= +25 °C,

VCC = 3.0 V

⎯

Byte (16-bit width)

write time

Excludes overhead time at system

level.

µs

cycle

h

Number of write/erase

cycles

⎯

10000

100000

Flash memory data

hold time

Average

T^A= +85 °C

⎯

*

* : Value converted from the evaluation result of technology reliability (The Arrhenius equation is used to convert

the high-temperature high-speed test result into the average temperature + 85 °C.)

70

MB90880 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90F882PF

MB90F883PF

MB90F883APF

MB90F884PF

MB90F884APF

MB90882PF

MB90883PF

MB90884PF

100-pin plastic QFP

(FPT-100P-M06)

MB90F882SPF

MB90F883SPF

MB90F883ASPF

MB90F884SPF

MB90F884ASPF

MB90882SPF

MB90883SPF

MB90884SPF

With S :

Single clock product (without sub clock)

Without S :

Dual clock product (with sub clock)

MB90F882PMC

MB90F883PMC

MB90F883APMC

MB90F884PMC

MB90F884APMC

MB90882PMC

MB90883PMC

MB90884PMC

100-pin plastic LQFP

(FPT-100P-M20)

MB90F882SPMC

MB90F883SPMC

MB90F883ASPMC

MB90F884SPMC

MB90F884ASPMC

MB90882SPMC

MB90883SPMC

MB90884SPMC

Evaluation product

101 :

Single clock product (without sub clock)

102 :

Dual clock product (with sub clock)

MB90V880-101CR-ES

MB90V880-102CR-ES

MB90V880A-101CR-ES

MB90V880A-102CR-ES

299-pin ceramic PGA

(PGA-299C-A01)

71

MB90880 Series

■ PACKAGE DIMENSIONS

100-pin plastic LQFP

Lead pitch

0.50 mm

14.0 mm × 14.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm Max

0.65 g

Code

(Reference)

P-LFQFP100-14×14-0.50

(FPT-100P-M20)

100-pin plastic LQFP

(FPT-100P-M20)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

16.00 0.20(.630 .008)SQ

*

14.00 0.10(.551 .004)SQ

75

51

76

50

0.08(.003)

Details of "A" part

1.50 ^+0.20

–

^0.10.059 ^+.008

–.004

INDEX

(Mounting height)

0.10 0.10

(.004 .004)

(Stand off)

100

26

0˚~8˚

"A"

(0.50(.020))

0.25(.010)

0.60 0.15

(.024 .006)

1

25

0.50(.020)

0.20 0.05

(.008 .002)

0.145 0.055

(.0057 .0022)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2005 FUJITSU LIMITED F100031S-c-2-1

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

(Continued)

72

MB90880 Series

(Continued)

100-pin plastic QFP

Lead pitch

0.65 mm

14.00 × 20.00 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Plastic mold

3.35 mm MAX

P-QFP100-14×20-0.65

Code

(Reference)

(FPT-100P-M06)

100-pin plastic QFP

(FPT-100P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

23.90 0.40(.941 .016)

*

20.00 0.20(.787 .008)

80

51

81

50

0.10(.004)

17.90 0.40

(.705 .016)

*

14.00 0.20

(.551 .008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ⁺^–0⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8

˚

1

30

0.65(.026)

0.32 0.05

(.013 .002)

0.17 0.06

(.007 .002)

M

0.13(.005)

0.25 0.20

(.010 .008)

(Stand off)

0.80 0.20

(.031 .008)

"A"

0.88 0.15

(.035 .006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2002 FUJITSU LIMITED F100008S-c-5-5

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

73

MB90880 Series

■ MAIN CHANGES IN THIS EDITION

Page

⎯

Section

⎯

Change Results

Added the following part numbers:

MB90F883A (S), MB90F884A (S)

3

■ PRODUCT LINEUP

Added the following details to the CPU functions:

“Maximum operating frequency is 25 MHz in MB90F883 (S) ,

MB90F884 (S)”

Added the following details to the base timer:

“In MB90F883(S) and MB90F884(S), P24/TIO0, P25/TIO1,

P26/TIO2, and P27/TIO3 cannot be used as input function.”

4

Added the "Flash memory" item

21

■ HANDLING DEVICES

Added "13. Note of MB90F883 (S), MB90F884 (S)"

■ ELECTRICAL CHARACTERISTICS Added the "Smoothing capacitor" item

43

46

2. Recommended operating conditions

Added the "• C Pin Connection Diagram"

■ ELECTRICAL CHARACTERISTICS Added the "I^CTS" and "ICCLS" items to the supply current

3. DC characteristics

Changed supply current ratings:

I^CCSInternal 25 MHz operation;

Typ 9 → 6, Max 16 → 12

I^CCSInternal 33 MHz operation;

Typ 12 → 10, Max 22 → 20

I^CCLTyp 70 → 80

I^CCTTyp 15 → 20

I^CCHTyp 10 → 15

47

71

■ELECTRICAL CHARACTERISTICS Added the following details to footnote 1 of the table:

4. AC characteristics

(1) Clock timing ratings

“The maximum operating frequency is 25 MHz in

MB90F883(S) and MB90F884(S).”

■ ORDERING INFORMATION

Added the following part numbers:

MB90F883APF, MB90F884APF, MB90F883ASPF,

MB90F884ASPF, MB90F883APMC, MB90F884APMC,

MB90F883ASPMC, MB90F884ASPMC

Added the following details to the remarks:

With S :

Single clock product (without sub clock)

Without S :

Dual clock product (with sub clock)

Added the MB90V880 item

The vertical lines marked in the left side of the page show the changes.

74

MB90880 Series

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

The company names and brand names herein are the trademarks or

registered trademarks of their respective owners.

Edited

Business Promotion Dept.

F0702


型号：	MB90V880-102CR-ES
厂家：	FUJITSU
描述：	16-Bit Proprietary Microcontroller 16位微控制器专有微控制器
文件：	总75页 (文件大小：1096K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90V880-102CR-ES [FUJITSU]

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