MB90V925-101_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13745-1E

16-bit Microcontroller

CMOS

F²MC-16LX MB90925 Series

MB90F927/F927S/V925-101/V925-102

■ DESCRIPTION

MB90925 series is a 16-bit general-purpose high-capacity microcontroller designed for vehicle meter control

applications etc.

The instruction set retains the same AT architecture as F²MC-8L and F²MC-16L series, with further refinements

including high-level language instructions, expanded addressing mode, enhanced signed multiplication and

division computation and bit processing.

In addition, a 32-bit accumulator is built in to enable long word processing.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURES

• Clock

Built-in PLL clock frequency multiplication circuit.

Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and

multiplication of 1 to 4 times of oscillation clock(for 4 MHz oscillation clock, 4 MHz to 16 MHz).

Operation by sub clock(up to 50 kHz : 100 kHz oscillation clock divided by 2).

(Continued)

Be sure to refer to the “Check Sheet” for the latest cautions on development.

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system

development.

MB90925 Series

• 16-bit input capture (4 channels)

Detects rising, falling, or both edges.

16-bit capture register × 4

Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.

• 16-bit reload timer (2 channels)

16-bit reload timer operation (select toggle output or one-shot output)

Event count function selection provided

• Real Time watch timer (main clock)

Operates directly from oscillator clock.

Interrupt can be generated by second/minute/hour/date counter overflow.

• 16-bit PPG (3 channels)

Output pins (3 channels) , external trigger input pin (1 channel)

Output clock frequencies : f^CP, fCP/2², fCP/2⁴, fCP/2⁶

• Delay interrupt

Generates interrupt for task switching.

Interrupts to CPU can be generated/deleted by software setting.

• External interrupts (8 channels)

8-channel independent operation

Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.

• A/D converter

10-bit or 8-bit resolution × 8 channels (input multiplexed)

Conversion time : 2.6µs (at f^CP= 16 MHz)

External trigger startup available (P50/INT0/ADTG)

Internal timer startup available (16-bit reload timer 1)

• UART(LIN/SCI) (2 channels)

Equipped with full duplex double buffer

Clock-asynchronous or clock-synchronous serial transfer is available

• SIO (1 channel)

Clock synchronized data transmission.

LSB-first or MSB-first data transfer selection is available.

• CAN interface

Conforms to CAN specifications version 2.0 Part A and B.

Automatic resend in case of error.

Automatic transfer in response to remote frame.

16 prioritized message buffers for data and ID

Multiple message support

Receiving filter has flexible configuration : Full bit compare/full bit mask/two partial bit masks

Supports up to 1 Mbps

CAN WAKEUP function (connects RX internally to INT0)

• LCD controller/driver (32 segment x 4 common)

Segment driver and command driver with direct LCD panel (display) drive capability

• Low voltage/Program looping detect reset

Automatic reset when low voltage is detected

Program looping detection function

(Continued)

2

MB90925 Series

(Continued)

• Stepping motor controller (4 channels)

High current output for each channel × 4

Synchronized 8/10-bit PWM for each channel × 2

• Sound generator

8-bit PWM signal mixed with tone frequency from 8-bit reload counter.

PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at f^CP= 16 MHz)

Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)

• Input/output ports

General-purpose input/output port (CMOS output)

- 70 ports (dual clock system)

- 72 ports (single clock system)

• Input level select function for port

Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode)

• Flash memory security function

Protect the content of Flash memory (Flash memory product only)

3

MB90925 Series

■ PRODUCT LINEUP

Part number

Parameter

MB90F927

MB90F927S

MB90V925-101

MB90V925-102

Type

CPU

Flash memory product

Evaluation product

F²MC-16LX CPU

PLL clock multiplier circuit ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)

Minimum instruction execution time 62.5 ns (with 4 MHz oscillation clock × 4)

System clock

Sub clock pin

(X0A, X1A)

Yes

No

Yes

ROM

Flash memory 64 Kbytes

4 Kbytes

External

RAM

13.5 Kbytes

I/O port

70 ports

72 ports

1 channel

32

70 ports

SIO

LCD segment

UART

UART(LIN/SCI) 2 channels

1 channel

CAN interface

16-bit input capture

16-bit reload timer

16-bit free-run timer

Real time watch timer

16-bit PPG

4 channels

2 channels

1 channel

3 channels

External interrupt

8/10-bit A/D converter

LVD/CPU loop reset

Stepping motor controller

Sound generator

Flash memory security

Operation voltage

Packages

8 channels

Yes

No

4 channels

1 channel

Yes

3.7 V to 5.5 V

4.5 V to 5.5 V

PGA-299

QFP-100, LQFP-100

4

MB90925 Series

■ PIN ASSIGNMENTS

(TOP VIEW)

COM2

COM3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P92/X0A

P93/X1A

P57/SGA

RST

P56/SGO/FRCK

P55/RX0

P54/TX0

P22/SEG0

P23/SEG1

P24/SEG2

P25/SEG3

P26/SEG4

P27/SEG5

P30/SEG6

P31/SEG7

DV^SS

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

DV^CC

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

DV^SS

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

DV^CC

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

DV^SS

V

SS

P32/SEG8

P33/SEG9

P34/SEG10

P35/SEG11

P36/SEG12

P37/SEG13

P40/SEG14

P41/SEG15

P42/SEG16

P43/SEG17

P44/SEG18

VCC

P45/SEG19

P46/SEG20

P47/SEG21

C

P90/SEG22

P91/SEG23

V0

P53/INT3/SCK

MD2

(FPT-100P-M06)

5

MB90925 Series

(TOP VIEW)

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

RST

P56/SGO/FRCK

P55/RX0

P54/TX0

DVSS

P22/SEG0

P23/SEG1

P24/SEG2

P25/SEG3

P26/SEG4

P27/SEG5

P30/SEG6

P31/SEG7

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

DVCC

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

DVSS

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

DVCC

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

DVSS

V

SS

P32/SEG8

P33/SEG9

P34/SEG10

P35/SEG11

P36/SEG12

P37/SEG13

P40/SEG14

P41/SEG15

P42/SEG16

P43/SEG17

P44/SEG18

VCC

P45/SEG19

P46/SEG20

P47/SEG21

C

(FPT-100P-M05)

6

MB90925 Series

■ PIN DESCRIPTIONS

Pin no.

I/O

circuit

Pin name

Function

LQFP*¹

QFP*²

type*³

80

81

82

83

X0

X1

High speed oscillator input pin

A

High speed oscillator output pin

General-purpose I/O port

P92

G

A

G

A

B

78

80

Low speed oscillator input pin. If no oscillator is connected,

apply pull-down processing.

X0A

P93

X1A

General-purpose I/O port

77

75

79

77

Low speed oscillator output pin. If no oscillator is connected,

leave open.

RST

P00

Reset input pin

General-purpose input/output port

UART ch.0 serial data input pin

INT4 external interrupt input pin

LCD controller/driver segment output

General-purpose input/output port

UART ch.0 serial data output pin

INT5 external interrupt input pin

LCD controller/driver segment output

General-purpose input/output port

UART ch.0 serial clock input/output pin

INT6 external interrupt input pin

LCD controller/driver segment output

General-purpose input/output port

UART ch.1 serial data input pin

INT7 external interrupt input pin

LCD controller/driver segment output

General-purpose input/output port

UART ch.1 serial data output pin

LCD controller/driver segment output

General-purpose input/output port

UART ch.1 serial clock input/output pin

16-bit PPG ch.0 to ch.2 external trigger input pin

LCD controller/driver segment output

SIN0

INT4

83

84

85

86

87

J

E

SEG24

P01

SOT0

INT5

SEG25

P02

SCK0

INT6

SEG26

P03

SIN1

INT7

86

87

88

89

90

J

E

SEG27

P04

SOT1

SEG28

P05

SCK1

TRG

SEG29

(Continued)

7

MB90925 Series

Pin no.

I/O

circuit

Pin name

Function

General-purpose input/output port

LQFP*¹

QFP*²

type*³

P06

PPG0

TOT1

SEG30

P07

16-bit PPG ch.0 output pin

89

91

E

16-bit reload timer ch.1 TOT output pin

LCD controller/driver segment output

General-purpose input/output port

16-bit PPG ch.1 output pin

PPG1

TIN1

90

92

16-bit reload timer ch.1 TIN output pin

LCD controller/driver segment output

General-purpose input/output port

16-bit PPG ch.2 output pin

SEG31

P10

91

92

93

94

G

PPG2

P11

General-purpose input/output port

16-bit reload timer ch.0 TOT output pin

General-purpose input/output port

16-bit reload timer ch.0 TIN output pin

Input capture ch.3 trigger input pin

General-purpose input/output port

Input capture ch.2 to ch.0 trigger input pins

TOT0

P12

93

95

TIN0

G

IN3

P13 to P15

IN2 to IN0

94 to 96 96 to 98

G

I

99, 100,

97 to 100

COM0 to

COM3

LCD controller/driver common output pins

General-purpose input/output ports

LCD controller/driver segment output pins

General-purpose input/output port

1, 2

P22 to P27

1 to 6

3 to 8

E

SEG0 to

SEG5

P30 to P37

7, 8,

9, 10,

SEG6 to

SEG13

10 to 15 12 to 17

LCD controller/driver segment output pins

General-purpose input/output port

P40 to P47

16 to 20, 18 to 22,

22 to 24 24 to 26

SEG14 to

SEG21

LCD controller/driver segment output pins

General-purpose input/output port

P90, P91

26, 27

34

28, 29

36

SEG22,

SEG23

LCD controller/driver segment output pins

P50

INT0

General-purpose input/output port

INT0 external interrupt input pin

A/D converter external trigger input pin

G

ADTG

(Continued)

8

MB90925 Series

Pin no.

LQFP*¹QFP*²

I/O

Pin name circuit

type*³

Function

General-purpose input/output port

P60 to P67

36 to 39, 38 to 41,

41 to 44 43 to 46

F

K

AN0 to

AN7

A/D converter input pins

P51

INT1

SI

General-purpose input/output port

INT1 external interrupt input pin

SIO data input pin

45

46

50

47

48

52

P52

General-purpose input/output port

INT2 external interrupt input pin

SIO data output pin

INT2

SO

G

P53

General-purpose input/output port

INT3 external interrupt input pin

SIO clock input/output pin

INT3

SCK

P70 to P73

General-purpose input/output port

PWM1P0,

PWM1M0,

PWM2P0,

PWM2M0

52 to 55 54 to 57

57 to 60 59 to 62

62 to 65 64 to 67

67 to 70 69 to 72

H

Stepping motor controller ch.0 output pins

General-purpose input/output port

P74 to P77

PWM1P1,

PWM1M1,

PWM2P1,

PWM2M1

Stepping motor controller ch.1 output pins

General-purpose input/output port

P80 to P83

PWM1P2,

PWM1M2,

PWM2P2,

PWM2M2

Stepping motor controller ch.2 output pins

General-purpose input/output port

P84 to P87

PWM1P3,

PWM1M3,

PWM2P3,

PWM2M3

Stepping motor controller ch.3 output pins

P54

TX0

P55

RX0

General-purpose input/output port

CAN interface 0 TX output pin

General-purpose output port

CAN interface 0 RX input pin

72

73

74

75

G

(Continued)

9

MB90925 Series

(Continued)

Pin no.

I/O

Pin name circuit

Function

General-purpose input/output port

LQFP*¹

QFP*²

type*³

P56

74

76

SGO

FRCK

P57

G

Sound generator SGO output pin

Free-run timer clock input pin

General-purpose input/output port

Sound generator SGA output pin

LCD controller /driver reference power supply pins

76

78

SGA

28 to 31 30 to 33

56, 66 58, 68

51, 61, 71 53, 63, 73

V0 to V3

⎯

Power supply input pins dedicated for high current output buffer

(pin numbers 54 to 57, 59 to 62, 64 to 67, 69 to 72) .

DV^CC

DV^SS

Power supply GND pins dedicated for high current output buffer (pin

numbers 54 to 57, 59 to 62, 64 to 67, 69 to 72) .

⎯

32

35

33

34

37

35

AV^CC

AV^SS

⎯

A/D converter dedicated power supply input pin

A/D converter dedicated power supply GND pin

A/D converter Vref + input pin

AVRH

47,

48

49,

50

MD0,

MD1

C

Test mode input pins. Connect to V^CC.

49

51

MD2

C/D^*4Test mode input pin. Connect to VSS.

External capacitor pin. Connect an 0.1 µF capacitor between this

pin and VSS.

25

27

C

⎯

21, 82

23, 84

V^CC

V^SS

⎯

Power supply input pins

Power supply GND pins

9, 40, 79 11, 42, 81

*1: FPT-100P-M05

*2: FPT-100P-M06

*3: For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”

*4: Type C in MB90F927 and MB90F927S, type D in MB90V925-101 and MB90V925-102.

10

MB90925 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• High-speed oscillation pin

X1

Oscillation feedback resistance :

approx. 1 MΩ (X0, X1 : MAIN)

• Low-speed oscillation pin

Xout

Oscillation feedback resistance :

approx. 10 MΩ (X0A, X1A : SUB)

A

X0

Standby control signal

Input dedicated pin (with pull-up resis-

tance)

• Pull-up resistance attached :

approx. 50 kΩ

• Hysteresis input

B

C

Hysteresis input

(V^IH/VIL = 0.8VCC/0.2VCC)

Input dedicated pin

Hysteresis input

(VIH/VIL = 0.8VCC/0.2VCC)

Input dedicated pin (with pull-down re-

sistance)

Hysteresis input

• Pull-down resistance attached :

D

approx. 50 kΩ

• Hysteresis input

(V^IH/VIL = 0.8VCC/0.2VCC)

LCDC output common general-

purpose port

• CMOS output

Pout

Nout

P-ch

N-ch

(I^OH/IOL =

4 mA)

• Hysteresis input

(V^IH/VIL = 0.8VCC/0.2VCC)

• Automotive input

(VIH/VIL = 0.8VCC/0.5VCC)

LCDC output

E

Hysteresis input

Standby control signal or

LCDC output switching signal

Automotive input

Standby control signal or

LCDC output switching signal

(Continued)

11

MB90925 Series

Type

Circuit

Remarks

A/D converter input common general-

purpose port

• CMOS output

P-ch

N-ch

Pout

Nout

(I^OH/IOL =

4 mA)

• Hysteresis input

(V^IH/VIL = 0.8VCC/0.2VCC)

• Automotive input

(V^IH/VIL = 0.8VCC/0.5VCC)

Analog input

F

Hysteresis input

Standby control signal or

Analog input enable signal

Automotive input

Standby control signal or

Analog input enable signal

General-purpose port

• CMOS output

(I^OH/IOL =

• Hysteresis input

(V^IH/VIL = 0.8VCC/0.2VCC)

• Automotive input

4 mA)

Pout

Nout

P-ch

N-ch

G

(VIH/VIL = 0.8VCC/0.5VCC)

Hysteresis input

Standby control signal

Automotive input

Standby control signal

High current output common general-

purpose port

• CMOS output

Pout high current output

Nout high current output

P-ch

N-ch

(I^OH/IOL =

30 mA)

• Hysteresis input

(VIH/VIL = 0.8VCC/0.2VCC)

• Automotive input

H

(V^IH/VIL = 0.8VCC/0.5VCC)

Hysteresis input

Standby control signal

Automotive input

Standby control signal

(Continued)

12

MB90925 Series

(Continued)

Type

Circuit

Remarks

LCDC output pin (COM pin)

P-ch

N-ch

I

LCDC output

LCDC output common general-

purpose port (serial input)

• CMOS output

P-ch

Pout

(I^OH/IOL =

4 mA)

• Hysteresis input

Nout

N-ch

(V^IH/VIL = 0.8VCC/0.2VCC)

• CMOS input (SIN)

(V^IH/VIL = 0.7VCC/0.3VCC)

• Automotive input

LCDC output

(V^IH/VIL = 0.8VCC/0.5VCC)

J

Hysteresis input

Standby control signal or

LCDC output enable signal

Automotive input

Standby control signal or

LCDC output enable signal

CMOS input (SIN)

Standby control signal or

LCDC output enable signal

General-purpose port (serial input)

• CMOS output

(I^OH/IOL =

• Hysteresis input

(V^IH/VIL = 0.8VCC/0.2VCC)

• CMOS input (SIN)

(VIH/VIL = 0.7VCC/0.3VCC)

• Automotive input

4 mA)

Pout

Nout

P-ch

N-ch

Hysteresis input

K

(V^IH/VIL = 0.8VCC/0.5VCC)

Standby control signal

Automotive input

Standby control signal

CMOS input (SIN)

Standby control signal

13

MB90925 Series

■ HANDLING DEVICES

• Strictly observe maximum rated voltages (preventing latch-up)

In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are

applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and

VSS exceeds the rated voltage level. In a latch-up condition, the power supply current can increase dramatically

and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid

exceeding maximum ratings.

Also care must be taken when the analog system power supply is switched on or off to ensure that the analog

power supply (AV^CC, AVRH) , the analog input voltages and the power supply voltage for the high current output

buffer pins (DVCC) do not exceed the digital power supply voltage (VCC) .

Once the digital power supply voltage (V^CC) has been disconnected, the analog power supply (AVCC, AVRH) and

the power supply voltage for the high current output buffer pins (DVCC) may be turned on in any sequence.

• Stable supply voltage

Even within the warranted operating range of V^CCpower supply voltage, rapid fluctuations in the power supply

voltage can cause malfunctions. The recommended stability for ripple fluctuations (P-P value) at commercial

frequencies (50 Hz/60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur

during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.

• Notes on energization Power-on procedures

In order to prevent the built-in step-down circuits from malfunctioning, the voltage rising time (0.2 V to 2.7 V)

during power-on should be attained within 50 µs.

• Treatment of unused pins

If unused input pins are left open, they may cause malfunctions or latch-up which may lead to permanent damage

to the semiconductor. Unused input pins should therefore be pulled up or pulled down through a resistor of at

least 2 kΩ.

Any unused input/output pins should be left open in output status, or if found set to input status, they should be

treated in the same way as input pins.

• Treatment of A/D converter power supply pins

Even if the A/D converter is not used, pins should be connected so that AV^CC= VCC, and AVSS = AVRH = VSS.

• Notes on Using an external clock

Even when an external clock is used, an oscillation stabilization wait time is required following power-on reset

or release from sub clock mode or stop mode. Also, when an external clock is used, it should drive only the X0

pin and the X1 pin should be left open, as shown below.

X0

OPEN

X1

MB90925 Series

Sample external clock connection

14

MB90925 Series

• Power supply pins

Devices are designed to prevent problems such as latch-up when multiple V^CCand VSS pins are used, by providing

internal connections between pins having the same potential. However, in order to reduce unwanted radiation,

to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current

ratings, all VCC and VSS pins should always be connected externally to power supplies and ground respectively.

As shown in the figure below, all V^CCpins must have the same potential and all VSS pins must be at the same

potential. If there are multiple VCC or VSS systems, the device will not operate properly even within the warranted

operating range.

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Power supply input pins (VCC/VSS)

In addition, care must be given to connecting the V^CCand VSS pins of this device to the current supply source

with as low impedance as possible. It is recommended that a 1.0 µF bypass capacitor be connected between

the VCC and VSS pins as close to the pins as possible.

• Turning-on sequence of power supply to A/D converter and analog inputs

The A/D converter power supply (AV^CC, AVRH) and analog inputs (AN0 to AN7) must be applied after the digital

power supply (VCC) is switched on. When power is shut off, the A/D converter power supply and analog inputs

must be cut off before the digital power supply is switched off (VCC) . In both power-on and power-off, care should

be taken that AVRH does not exceed AV^CC. Even when pins which double as analog input pins are used as input

ports, be sure that the input voltage does not exceed AVCC.

• Handling the power supply for high-current output buffer pins (DV^CC, DVSS)

Always apply power supply to high-current output buffer pins (DVCC, DVSS) after the digital power supply (VCC) is

turned on. Also when switching the power off, always shut off the power supply to the high-current output buffer

pins (DV^CC, DVSS) before switching off the digital power supply (VCC) . There is no problem if the high-current

output buffer pins and digital power supplies are turned off and on at the same time.

Even when the high-current output buffer pins are used as general-purpose ports, the power supply for high

current output buffer pins (DV^CC, DVSS) should be applied to these pins.

• Pull-up/pull-down resistor

MB90925 series does not support internal pull-up/pull-down resistor. If necessary, use external components.

15

MB90925 Series

• Precautions for when not using a sub clock signal

If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave

the X1A pin open.

• Notes on operation when external clock is stopped

When there is no external oscillator or external clock input is stopped, performance of the operation by MB90925

series the internal oscillation circuit cannot be guaranteed.

16

MB90925 Series

■ BLOCK DIAGRAM

X0, X1

P92/X0A

P93/X1A

RST

Clock control

circuit

CPU

F MC-16LX core

2

RAM 4 Kbytes*

ROM 64 Kbytes*

Interrupt

controller

Low voltage/

CPU operation

detection reset

Sound generator

CAN controller

SIO

P87/PWM2M3

P57/SGA

P56/SGO/FRCK

P55/RX0

Port 8

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

P83/PWM2M2

P82/PWM2P2

P54/TX0

Prescaler (SIO)

Port 5

P53/INT3/SCK

P52/INT2/SO

P51/INT1/SI

P50/INT0/ADTG

P81/PWM1M2

P80/PWM1P2

Stepping

motor

controller

0/1/2/3

External interrupt

(8 channels)

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

P00/SIN0/INT4/SEG24

P01/SOT0/INT5/SEG25

P02/SCK0/INT6/SEG26

P03/SIN1/INT7/SEG27

P04/SOT1/SEG28

UART0/1

Prescaler

0/1

P05/SCK1/TRG/SEG29

P06/PPG0/TOT1/SEG30

P07/PPG1/TIN1/SEG31

Port 7

Port 6

Port 0

P67 to P60/

AN7 to AN0

AVCC/AVSS

AVRH

A/D converter

(8 channels)

PPG0/1/2

P10/PPG2

P11/TOT0

P12/TIN0/IN3

P13/IN2

Port F

P91, P90/

Port 9

Port 4

Port 3

SEG23, SEG22

Reload timer

0/1

P14/IN1

P47 to P40/

P15/IN0

SEG21 to SEG14

Real-time

watch timer

P37 to P30/

SEG13 to SEG6

ICU0/1/2/3

P27 to P22/

Port 2

SEG5 to SEG0

Free-run timer

* : Evaluation device (MB90V925-101/102)

LCD controller/

driver

COM3 to COM0

V3 to V0

No built-in ROM

Built-in RAM is 6 Kbytes.

17

MB90925 Series

■ MEMORY MAP

Single chip mode

(with ROM mirror function)

000000H

Peripheral area

0000D0H

000100H

Register

RAM area

Address #2

003900^H

004000H

Peripheral area

ROM area

(FF bank image)

010000H

Address #1

FFFFFFH

: Internal access memory

: Access prohibited

ROM area

Part number

Address #1

FF0000H

Address #2

001100H

MB90F927/MB90F927S

MB90V925-101/MB90V925-102

F80000H

003700H

Note : To select models without the ROM mirror function, refer to the “ROM Mirror Function Selection Module” in

Hardware Manual. The image of the ROM data in the FF bank appears at the top of the 00 bank, in order

to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned

to the same address, so that tables in ROM can be referenced without declaring a “far” indication with the

pointer. For example when accessing the address 00C000H, the actual access is to address FFC000H in

ROM. Here the FF bank ROM area exceeds 48 Kbytes, so that it is not possible to see the entire area in the

00 bank image. Therefore because the ROM data from FF4000H to FFFFFFH will appear in the image from

004000H to 00FFFFH, it is recommended that the ROM data table be stored in the area from FF4000H to

FFFFFFH.

18

MB90925 Series

■ I/O MAP

• Other than CAN Interface

Address

Register name

Symbol Read/write Resource name

Initial value

XXXXXXXXB

- - XXXXXXB

XXXXXX - -B

XXXXXXXXB

- - - -XXXXB

000000^HPort 0 data register

000001H Port 1 data register

000002H Port 2 data register

000003H Port 3 data register

000004H Port 4 data register

000005H Port 5 data register

000006H Port 6 data register

000007H Port 7 data register

000008H Port 8 data register

000009H Port 9 data register

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

00000AH

to

(Disabled)

00000FH

000010^HPort 0 direction register

000011H Port 1 direction register

000012H Port 2 direction register

000013^HPort 3 direction register

000014^HPort 4 direction register

000015H Port 5 direction register

000016H Port 6 direction register

000017H Port 7 direction register

000018H Port 8 direction register

000019H Port 9 direction register

00001AH Analog input enable

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

ADER

R/W

Port 0

Port 1

0 0 0 0 0 0 0 0B

- - 0 0 0 0 0 0B

0 0 0 0 0 0 - -B*

0 0 0 0 0 0 0 0B*

0 0 0 0 0 0 0 0B

- - - - 0 0 0 0B

1 1 1 1 1 1 1 1B

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port 6, A/D

00001BH

to

(Disabled)

00001FH

000020H A/D control status register lower

000021H A/D control status register higher

000022H A/D data register lower

ADCS0

ADCS1

ADCR0

ADCR1

R/W

R

0 0 0 - - - - 0B

0 0 0 0 0 0 0 -B

0 0 0 0 0 0 0 0B

- - - - - - 0 0B

8/10-bit

A/D converter

000023H A/D data register higher

R

000024H

R/W

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 1 - 0 0 0 0 0B

Compare clear register

000025H

CPCLR

000026H

Timer data register

000027H

TCDT

16-bit free-run timer

000028H Timer control status register lower

TCCSL

000029H Timer control status register higher TCCSH

(Continued)

19

MB90925 Series

Address

00002A^HPPG0 control status register lower

00002BH PPG0 control status register higher PCNTH0

00002CH PPG1 control status register lower PCNTL1

00002DH PPG1 control status register higher PCNTH1

00002EH PPG2 control status register lower PCNTL2

00002FH PPG2 control status register higher PCNTH2

Register name

Symbol Read/write Resource name

Initial value

PCNTL0

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

16-bit PPG0

16-bit PPG1

16-bit PPG2

000030H External interrupt enable

000031H External interrupt request

000032H External interrupt level lower

000033H External interrupt level higher

000034H Serial mode register 0

ENIR

EIRR

External interrupt

ELVRL

ELVRH

SMR0

SCR0

000035H Serial control register 0

Reception/transmission data

register 0

RDR0/

TDR0

000036H

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 1 0 0 0B

0 0 0 0 0 0 XXB

000037H Serial status register 0

SSR0

UART(LIN/SCI) 0

Extended communication control

register 0

000038H

ECCR0

000039H Extended status control register

00003AH Baud rate generator register 00

00003BH Baud rate generator register 01

ESCR0

BGR00

BGR01

R/W

0 0 0 0 0 1 0 0B

0 0 0 0 0 0 0 0B

00003CH,

00003DH

(Disabled)

00003E^HCAN wake-up control register

00003FH

CWUCR

R/W

CAN

- - - - - - - 0B

(Disabled)

000040^H

to

Area reserved for CAN interface 0

00004FH

Timer control status register 0

000050^H

lower

TMCSR0L

TMCSR0H

R/W

0 0 0 0 0 0 0 0B

- - 1 0 0 0 0 0B

Timer control status register 0

000051H

higher

16-bit reload timer 0

16-bit reload timer 1

000052H

XXXXXXXX^B

XXXXXXXXB

TMR0/

TMRLR0

Timer register 0/reload register 0

000053H

R/W

Timer control status register 1

000054H

lower

TMCSR1L

TMCSR1H

R/W

0 0 0 0 0 0 0 0B

- - 1 0 0 0 0 0B

Timer control status register 1

000055H

higher

000056H

XXXXXXXXB

(Continued)

TMR1/

TMRLR1

Timer register 1/reload register 1

000057H

R/W

20

MB90925 Series

Address

Register name

Symbol Read/write

Resource name

Initial value

000058^HLCD output control register 1

000059H LCD output control register 2

00005AH Sound control register lower

00005BH Sound control register higher

00005CH Frequency data register

00005DH Amplitude data register

00005EH Decrement grade register

00005FH Tone count register

LOCR1

LOCR2

SGCRL

SGCRH

SGFR

R/W

1 1 1 1 1 1 1 1B

0 0 0 0 0 0 0 0B

0 - - - - 1 0 0B

XXXXXXXXB

0 0 0 0 0 0 0 0B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0B

XXX0X0XXB

0 0 0 0 0 0 0 0B

XXXXXXXXB

0 0 0 1 0 0 0 0B

0 0 0 0 0 0 0 0B

LCD

Sound generator

SGAR

SGDR

SGTR

000060H

Input capture register 0

000061H

IPCP0

IPCP1

IPCP2

IPCP3

R

Input capture 0/1

Input capture 2/3

000062H

Input capture register 1

000063H

000064H

Input capture register 2

000065H

000066H

Input capture register 3

000067H

000068H Input capture control status 0/1 ICS01

000069H Input capture edge register 0/1 ICE01

00006AH Input capture control status 2/3 ICS23

R/W

Input capture 0/1

Input capture 2/3

00006BH Input capture edge register 2/3

00006CH LCD control register lower

00006DH LCD control register higher

ICE23

LCRL

LCRH

LCD controller/

driver

Low voltage/CPU operation

00006EH

Low voltage/CPU opera-

tion detection reset

LVRC

R/W

W

0 0 1 1 1 0 0 0B

X X X X X X X 1B

detection reset control register

00006FH ROM mirror

ROMM

ROM mirror

000070H

to

(Disabled)

00007FH

Stepping motor

controller 0

000080^HPWM control register 0

000081H

PWC0

PWC1

PWC2

PWC3

R/W

0 0 0 0 0 - - 0B

(Disabled)

R/W

Stepping motor

controller 1

000082H PWM control register 1

000083H

(Disabled)

R/W

Stepping motor

controller 2

000084H PWM control register 2

000085H

(Disabled)

R/W

Stepping motor

controller 3

000086H PWM control register 3

0 0 0 0 0 - - 0B

(Continued)

21

MB90925 Series

Address

Register name

Symbol Read/write

Resource name

Initial value

000087^H

to

(Disabled)

000089H

00008AH A/D setting register 0

00008BH A/D setting register 1

00008CH Port input level select 0

00008DH Port input level select 1

ADSR0

ADSR1

PIL0

R/W

0 0 0 0 0 0 0 0B

- - - 0 0 0 0 0B

A/D

Port Input Level Select

PIL1

00008EH

to

(Disabled)

00009DH

Address match

detection function

00009EH ROM correction control register PACSR

R/W

- - - - - 0 - 0B

00009FH Delay interrupt/release

0000A0H Power saving mode

0000A1H Clock select

DIRR

R/W

Delay interrupt

- - - - - - - 0B

0 0 0 1 1 0 0 0B

1 1 1 1 1 1 0 0B

LPMCR

CKSCR

Power saving

control circuit

0000A2H

to

(Disabled)

0000A7H

0000A8H Watchdog control

WDTC

TBTC

R/W

Watchdog timer

Time-base timer

XXXXX 1 1 1B

1 - - 0 0 1 0 0B

Time-base timer control regis-

0000A9H

ter

Watch timer

(sub clock)

0000AAH Watch timer control register

WTC

R/W

1 X 0 0 0 0 0 0B

0000ABH

to

(Disabled)

0000ADH

0000AEH Flash control register

FMCS

R/W

(Disabled)

R/W

Flash memory interface 0 0 0 X 0 XX 0B

0000AFH

0000B0^HInterrupt control register 00

0000B1H Interrupt control register 01

0000B2H Interrupt control register 02

0000B3H Interrupt control register 03

0000B4H Interrupt control register 04

0000B5H Interrupt control register 05

0000B6H Interrupt control register 06

0000B7H Interrupt control register 07

0000B8H Interrupt control register 08

0000B9H Interrupt control register 09

0000BAH Interrupt control register 10

0000BBH Interrupt control register 11

0000BCH Interrupt control register 12

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

0 0 0 0 0 1 1 1B

R/W

Interrupt controller

0 0 0 0 0 1 1 1B

(Continued)

R/W

Interrupt controller

R/W

22

MB90925 Series

Address

Register name

Symbol Read/write Resource name

Initial value

0 0 0 0 0 1 1 1B

0000BD^HInterrupt control register 13

0000BEH Interrupt control register 14

0000BFH Interrupt control register 15

0000C0H Serial mode control register (lower)

ICR13

ICR14

ICR15

SMCSL

R/W

Interrupt controller 0 0 0 0 0 1 1 1B

0 0 0 0 0 1 1 1B

- - - - 0 0 0 0B

0000C1H Serial mode control register (higher) SMCSH

SIO

0 0 0 0 0 0 1 0B

XXXXXXXXB

0000C2H Serial data register

SDR

Communication prescaler

control register

Communication

prescaler (SIO)

0000C3H

SDCR

R/W

0 - - - 0 0 0 0B

0000C4H Serial mode register 1

0000C5H Serial control register 1

SMR1

SCR1

R/W

0 0 0 0 0 0 0 0B

Reception/transmission

0000C6H

RDR1/

TDR1

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 1 0 0 0B

0 0 0 0 0 0 XXB

data register 1

0000C7H Serial status register 1

SSR1

UART(LIN/SCI) 1

Extended communication

0000C8H

ECCR1

control register 1

0000C9H Extended status control register 1

0000CAH Baud rate generator register 10

0000CBH Baud rate generator register 11

0000CCH Watch timer control register lower

ESCR1

BGR10

BGR11

WTCRL

R/W

W

0 0 0 0 0 1 0 0B

0 0 0 0 0 0 0 0B

0 0 0 - - 0 0 0B

0 0 0 0 0 0 0 0B

- - - - 0 0 0 0B

Real-time

watch timer

0000CDH Watch timer control register middle WTCRM

0000CEH Watch timer control register higher

0000CFH Sub clock control register

WTCRH

SCCR

Sub clock

- - - - 0 0 0 0B

0000D0H

to

(Disabled)

0000FFH

001FF0^HROM correction address 0

001FF1H ROM correction address 1

001FF2H ROM correction address 2

001FF3H ROM correction address 3

001FF4H ROM correction address 4

001FF5H ROM correction address 5

PADR0

PADR1

R/W

XXXXXXXXB

Address match

detection function

Address match

detection function

003900H

to

(Disabled)

00391FH

003920H

1 1 1 1 1 1 1 1^B

1 1 1 1 1 1 1 1B

XXXXXXXXB

(Continued)

PPG0 down counter register

003921H

PDCR0

PCSR0

PDUT0

R

W

003922H

PPG0 cycle setting register

003923H

16-bit PPG 0

003924H

PPG0 duty setting register

003925H

23

MB90925 Series

Address

Register name

Symbol Read/write Resource name

Initial value

003926^H,

003927H

(Disabled)

003928^H

003929H

00392AH

00392BH

00392CH

00392DH

1 1 1 1 1 1 1 1^B

1 1 1 1 1 1 1 1B

XXXXXXXXB

PPG1 down counter register

PPG1 cycle setting register

PPG1 duty setting register

PDCR1

PCSR1

PDUT1

R

W

16-bit PPG 1

00392EH,

00392FH

(Disabled)

003930H

003931H

003932H

003933H

003934H

003935H

1 1 1 1 1 1 1 1B

XXXXXXXX^B

XXXXXXXXB

PPG2 down counter register

PPG2 cycle setting register

PPG2 duty setting register

PDCR2

PCSR2

PDUT2

R

W

16-bit PPG 2

003936H

to

(Disabled)

003957H

003958^H

XXXXXXXX^B

XXXXXXXXB

- - - XXXXXB

- - 0 0 0 0 0 0B

- - - 0 0 0 0 0B

0 0 - 0 0 0 0 1B

003959H Sub second data register

00395AH

WTBR

R/W

Real time

watch timer

00395BH Second data register

00395CH Minute data register

00395DH Hour data register

00395EH Day data register

00395FH

WTSR

WTMR

WTHR

WTDR

R/W

(Disabled)

003960H

LCD controller/

driver

to

LCD display RAM

VRAM

R/W

XXXXXXXXB

00396FH

003970H

to

(Disabled)

00397FH

003980^H

003981H

003982H

003983H

XXXXXXXXB

- - - - - - XXB

XXXXXXXX^B

- - - - - - XXB

- - 0 0 0 0 0 0B

- 0 0 0 0 0 0 0B

(Continued)

PWM1 compare register 0

PWM2 compare register 0

PWC10

PWC20

R/W

Stepping motor

controller 0

003984H PWM1 select register 0

003985H PWM2 select register 0

PWS10

PWS20

R/W

24

MB90925 Series

Address

Register name

Symbol Read/write Resource name

(Disabled)

Initial value

003986^H,

003987H

003988^H

003989H

00398AH

00398BH

XXXXXXXX^B

- - - - - - XXB

XXXXXXXXB

- - - - - - XXB

- - 0 0 0 0 0 0B

- 0 0 0 0 0 0 0B

PWM1 compare register 1

PWM2 compare register 1

PWC11

R/W

Stepping motor

controller 1

PWC21

00398CH PWM1 select register 1

00398DH PWM2 select register 1

PWS11

PWS21

R/W

00398EH,

00398FH

(Disabled)

003990H

XXXXXXXX^B

- - - - - - XXB

XXXXXXXX^B

- - - - - - XXB

- - 0 0 0 0 0 0B

- 0 0 0 0 0 0 0B

PWM1 compare register 2

003991H

PWC12

PWC22

R/W

003992H

Stepping motor

controller 2

PWM2 compare register 2

003993H

003994H PWM1 select register 2

003995H PWM2 select register 2

PWS12

PWS22

R/W

003996H,

003997H

(Disabled)

003998^H

XXXXXXXXB

- - - - - - XXB

XXXXXXXX^B

- - - - - - XXB

- - 0 0 0 0 0 0B

- 0 0 0 0 0 0 0B

PWM1 compare register 3

003999H

PWC13

PWC23

R/W

00399AH

Stepping motor

controller 3

PWM2 compare register 3

00399BH

00399CH PWM1 select register 3

00399DH PWM2 select register 3

PWS13

PWS23

R/W

00399EH

to

(Disabled)

0039FFH

003A00^H

to

003AFFH

Area reserved for CAN interface 0

(Disabled)

003B00H

to

003BFFH

003C00H

to

003CFFH

Area reserved for CAN interface 0

(Disabled)

003D00^H

to

003EFFH

(Continued)

25

MB90925 Series

(Continued)

• Initial value symbols :

“0” : initial value 0

“1” : initial value 1

“X” : initial value undetermined

“-” : initial value undetermined (none)

• Write/read symbols :

“R/W” : read/write enabled

“R”

“W”

: read only

: write only

• Addresses in the area 0000^Hto 00FFH are reserved for the principal functions of the MCU. Read access

attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited.

* : P22/SEG0 to P27/SEG5 and P30/SEG6 to P35/SEG11 initially will be LCD segment output as LCD output

control register LOCR1 (58H) is “11111111B” initially. To use port 2 and port 3 as the general-purpose input/

output ports, set LOCR1 to “00000000^B” to disable the LCD segment output first.

26

MB90925 Series

• CAN Interface

Read/

write

Address

Register name

Symbol

Initial value

000040^H

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 - - - 0 0 0^B

0 - - - - 0 - 1B

Message buffer valid area

BVALR

R/W

000041H

000042H

000043H

000044H

000045H

000046H

000047H

000048H

000049H

00004AH

00004BH

00004CH

00004DH

00004EH

00004FH

003C00H

003C01H

003C02H

003C03H

003C04H

003C05H

003C06H

003C07H

003C08H

003C09H

003C0AH

003C0BH

003C0CH

003C0DH

003C0EH

003C0FH

Transmission request register

Transmission cancel register

Transmission completed register

Receiving completed register

Remote request receiving register

Receiving overrun register

Receiving interrupt enable register

Control status register

TREQR

TCANR

TCR

R/W

W

R/W

R/W, R

R/W

R

RCR

RRTRR

ROVRR

RIER

CSR

- - - - - - - -^B

Last event indicator register

RX/TX error counter

LEIR

0 0 0 - 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

- 1 1 1 1 1 1 1^B

1 1 1 1 1 1 1 1B

XXXXXXXX^B

RTEC

BTR

Bit timing register

R/W

IDE register

IDER

XXXXXXXXB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

XXXXXXXX^B

Transmission RTR register

Remote frame receiving wait register

Transmission interrupt enable register

TRTRR

RFWTR

TIER

XXXXXXXXB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

(Continued)

27

MB90925 Series

Read/

write

Address

Register name

Symbol

Initial value

003C10^H

003C11H

003C12H

003C13H

003C14H

003C15H

003C16H

003C17H

003C18H

003C19H

003C1AH

003C1BH

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

Acceptance mask select register

Acceptance mask register 0

AMSR

R/W

AMR0

Acceptance mask register 1

General-purpose RAM

ID register 0

AMR1

⎯

R/W

003A00H

to

003A1FH

XXXXXXXXB

to

XXXXXXXXB

003A20H

003A21H

003A22H

003A23H

003A24H

003A25H

003A26H

003A27H

003A28H

003A29H

003A2AH

003A2BH

003A2CH

003A2DH

003A2EH

003A2FH

003A30H

003A31H

003A32H

003A33H

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

IDR0

ID register 1

ID register 2

ID register 3

ID register 4

IDR1

IDR2

IDR3

IDR4

R/W

(Continued)

28

MB90925 Series

Read/

write

Address

Register name

Symbol

Initial value

003A34^H

003A35H

003A36H

003A37H

003A38H

003A39H

003A3AH

003A3BH

003A3CH

003A3DH

003A3EH

003A3FH

003A40H

003A41H

003A42H

003A43H

003A44H

003A45H

003A46H

003A47H

003A48H

003A49H

003A4AH

003A4BH

003A4CH

003A4DH

003A4EH

003A4FH

003A50H

003A51H

003A52H

003A53H

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

ID register 5

ID register 6

ID register 7

ID register 8

ID register 9

ID register 10

ID register 11

ID register 12

IDR5

R/W

IDR6

IDR7

R/W

IDR8

IDR9

IDR10

IDR11

IDR12

(Continued)

29

MB90925 Series

Read/

write

Address

Register name

Symbol

Initial value

003A54^H

003A55H

003A56H

003A57H

003A58H

003A59H

003A5AH

003A5BH

003A5CH

003A5DH

003A5EH

003A5FH

003A60H

003A61H

003A62H

003A63H

003A64H

003A65H

003A66H

003A67H

003A68H

003A69H

003A6AH

003A6BH

003A6CH

003A6DH

003A6EH

003A6FH

003A70H

003A71H

003A72H

003A73H

003A74H

003A75H

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXX- - -B

XXXXXXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

ID register 13

ID register 14

ID register 15

IDR13

R/W

IDR14

IDR15

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLCR0

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

DLCR10

R/W

(Continued)

30

MB90925 Series

Read/

write

Address

Register name

Symbol

Initial value

003A76^H

003A77H

003A78H

003A79H

003A7AH

003A7BH

003A7CH

003A7DH

003A7EH

003A7FH

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

- - - -XXXX^B

- - - -XXXXB

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR11

R/W

DLCR12

DLCR13

DLCR14

DLCR15

R/W

003A80H

to

003A87H

XXXXXXXXB

to

XXXXXXXXB

Data register 0 (8 bytes)

Data register 1 (8 bytes)

Data register 2 (8 bytes)

Data register 3 (8 bytes)

Data register 4 (8 bytes)

Data register 5 (8 bytes)

Data register 6 (8 bytes)

Data register 7 (8 bytes)

Data register 8 (8 bytes)

Data register 9 (8 bytes)

DTR0

DTR1

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

R/W

003A88H

to

003A8FH

XXXXXXXXB

to

XXXXXXXXB

003A90H

to

003A97H

XXXXXXXXB

to

XXXXXXXXB

003A98H

to

003A9FH

XXXXXXXXB

to

XXXXXXXXB

003AA0H

to

003AA7H

XXXXXXXXB

to

XXXXXXXXB

003AA8H

to

003AAFH

XXXXXXXXB

to

XXXXXXXXB

003AB0H

to

003AB7^H

XXXXXXXXB

to

XXXXXXXXB

003AB8H

to

003ABFH

XXXXXXXX^B

to

XXXXXXXXB

003AC0H

to

003AC7H

XXXXXXXX^B

to

XXXXXXXXB

003AC8H

to

XXXXXXXXB

to

003ACF^H

XXXXXXXXB

(Continued)

31

MB90925 Series

(Continued)

Read/

write

Address

Register name

Symbol

Initial value

003AD0^H

to

003AD7H

XXXXXXXXB

to

XXXXXXXXB

Data register 10 (8 bytes)

Data register 11 (8 bytes)

Data register 12 (8 bytes)

Data register 13 (8 bytes)

Data register 14 (8 bytes)

Data register 15 (8 bytes)

DTR10

R/W

003AD8H

to

003ADFH

XXXXXXXXB

to

XXXXXXXXB

DTR11

DTR12

DTR13

DTR14

DTR15

003AE0H

to

003AE7H

XXXXXXXXB

to

XXXXXXXXB

003AE8H

to

003AEFH

XXXXXXXXB

to

XXXXXXXXB

003AF0H

to

003AF7H

XXXXXXXXB

to

XXXXXXXXB

003AF8H

to

XXXXXXXXB

to

003AFFH

XXXXXXXXB

32

MB90925 Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

EI²OS

corre-

sponding

Interrupt control register

Interrupt vector

Priority

Interrupt source

2

*

Number Address

ICR

Address

Reset

×

#08 08^HFFFFDCH

#09 09H FFFFD8H

#10 0A^HFFFFD4H

#11 0BH FFFFD0H

#12 0CH FFFFCCH

#13 0DH FFFFC8H

#14 0EH FFFFC4H

#15 0FH FFFFC0H

#16 10H FFFFBCH

#17 11H FFFFB8H

#18 12H FFFFB4H

#19 13H FFFFB0H

#20 14H FFFFACH

#21 15H FFFFA8H

#22 16H FFFFA4H

#23 17H FFFFA0H

⎯

High

INT9 instruction

Exception processing

CAN0 RX

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

0000B0H *¹

0000B1H *¹

0000B2H *¹

0000B3H *¹

0000B4H *¹

0000B5H *¹

CAN0 TX/NS

( Reserved) ^*3

SIO ^*3

Input capture 0

DTP/external interrupt - ch.0 detected

Reload timer 0

DTP/external interrupt - ch.1 detected

Input capture 1

DTP/external interrupt - ch.2 detected

Input capture 2

DTP/external interrupt - ch.3 detected

Input capture 3

ICR06

ICR07

0000B6H *¹

0000B7H *¹

DTP/external interrupt - ch.4/ch.5

detected

#24 18H FFFF9CH

#25 19H FFFF98H

#26 1AH FFFF94H

PPG timer 0

DTP/external interrupt - ch.6/ch.7

detected

PPG timer 1

#27 1BH FFFF90H

#28 1CH FFFF8CH

#29 1DH FFFF88H

#30 1EH FFFF84H

#31 1FH FFFF80H

#32 20H FFFF7CH

#33 21H FFFF78H

#34 22H FFFF74H

#35 23H FFFF70H

#36 24H FFFF6CH

#37 25H FFFF68H

#38 26H FFFF64H

#39 27H FFFF60H

#40 28H FFFF5CH

#41 29H FFFF58H

#42 2AH FFFF54H

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

0000B8H *¹

0000B9H *¹

0000BAH *¹

0000BBH *¹

0000BCH *¹

0000BDH *¹

0000BEH *¹

0000BFH *¹

Reload timer 1

PPG timer 2

Real time watch timer

Free-run timer overflow

A/D converter conversion end

Free-run timer clear

Sound generator

Time-base timer

×

Watchdog (sub clock)

UART 1 RX

UART 1 TX

UART 0 RX

UART 0 TX

Flash memory status

Delay interrupt generator module

×

Low

(Continued)

33

MB90925 Series

(Continued)

: Usable, with EI²OS stop function

: Usable

: Usable when interrupt sources sharing ICR are not in use

× : Unusable

*1 : • Peripheral functions sharing the ICR register have the same interrupt level.

• If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other

cannot be used.

• When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services,

the interrupt from the other function cannot be used.

*2 : Priority applies when interrupts of the same level are generated.

*3 : SIO and CAN1 TX/NX will share IRQ3 in evaluation chip (MB90V925-101/102) .

34

MB90925 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

VCC

AV^CC

AVRH

DVCC

VI

VSS − 0.3 VSS + 6.0

VSS − 0.3 VCC + 0.3

V

AVCC = VCC*²

Power supply voltage*¹

AVCC ≥ AVRH*²

DVCC = VCC*²

*3

Input voltage*¹

Output voltage*¹

VO

Maximum clamp current

I^CLAMP

− 400

⎯

+ 400

4

µA *7

Total maximum clamp current Σ| I^CLAMP|

mA *7

IOL1

I^OL2

⎯

15

mA Other than P70 to P77 and P80 to P87

mA P70 to 77 and P80 to87

mA Other than P70 to P77 and P80 to P87

mA P70 to 77 and P80 to 87

mA Other than P70 to P77 and P80 to P87

mA P70 to 77 and P80 to 87

mA Other than P70 to P77 and P80 to P87

mA P70 to 77 and P80 to 87

mA Other than P70 to P77 and P80 to P87

mA P70 to 77 and P80 to 87

mA Other than P70 to P77 and P80 to P87

mA P70 to 77 and P80 to 87

mA Other than P70 to P77 and P80 to P87

mA P70 to 77 and P80 to 87

mA Other than P70 to P77 and P80 to P87

mA P70 to 77 and P80 to 87

mW

“L” level maximum

output current*⁴

⎯

40

IOLAV1

I^OLAV2

ΣI^OL1

⎯

4

“L” level average output

current*⁵

⎯

30

⎯

100

330

50

“L” level maximum

total output current

ΣI^OL2

⎯

ΣI^OLAV1

ΣI^OLAV2

I^OH1*⁴

I^OH2*⁴

I^OHAV1*⁵

I^OHAV2*⁵

ΣI^OH1

ΣI^OH2

ΣI^OHAV1*⁶

ΣI^OHAV2*⁶

P^D

⎯

“L” level average total

output current

⎯

250

−15

−40

−4

⎯

“H” level maximum

output current

⎯

“H” level average

output current

⎯

−30

−100

−330

−50

−250

500

+105

+150

⎯

“H” level maximum

total output current

⎯

“H” level average total

output current

⎯

Power consumption

Operating temperature

Storage temperature

⎯

T^A

−40

−55

°C

T^STG

°C

*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.

*2 : AV^CC, AVRH and DVCC shall never exceed VCC.

Also, AVRH shall never exceed AV^CC.

*3 : The maximum current to/from and input are limited by some means with external components, the I^CLAMPrating

supersedes the VI rating.

*4 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins.

*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the

corresponding pins. The “average value” can be calculated from the formula of “operating current” times

“operating factor”.

(Continued)

35

MB90925 Series

(Continued)

*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the

corresponding pins. The “average value” can be calculated from the formula of “operating current” times

“ operating factor”.

*7 : • Applicable to pins : P10 to P15, P50 to P57, P70 to P77, P80 to P87

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied with a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting power supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept +B

signal input.

• Sample recommended circuits :

• Input/Output equivalent circuits

Protective diode

V^CC

P-ch

Limiting

resistance

+B input (0 V to 16 V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

36

MB90925 Series

2. Recommended Operating Conditions

Value

(VSS = DVSS = AVSS = 0.0 V)

Parameter Symbol

Unit

Remarks

Min

Max

(MB90F927/MB90F927S)

3.7

5.5

V

Low voltage detection reset starts to work when power

supply voltage is 4.0 V 0.3 V.

V^CC

Power supply

AVCC

voltage

DVCC

Holding stop operation status

(MB90F927/MB90F927S)

4.3

0.1

5.5

1.0

Use a ceramic capacitor or other capacitor of equivalent

Smoothing

C^S

µF frequency characteristics. A bypass capacitor on the VCC pin

capacitor*

should have a capacitance greater than Cs.

Operating

T^A

− 40

+ 105

°C

temperature

* : For smoothing capacitor Cs connections, refer to the illustration below.

• C pin connection diagram

C

AVSS

VSS

DVSS

C^S

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

37

MB90925 Series

3. DC Characteristics

(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Symbol

Parameter

Conditions

Unit

Remarks

name

Min

Typ

Max

Pin inputs if

⎯

VCC + 0.3

V^IHA

⎯

0.8 VCC

⎯

V

Automotive input

levels are selected*¹

Pin inputs if CMOS

hysteresis input

levels are selected*¹

(0.8Vcc/0.2Vcc

CMOS hysteresis is

selected for P00,

P03 and P51)

⎯

VCC + 0.3

VIHS2

⎯

0.8 VCC

0.7 VCC

⎯

V

“H” level

input voltage

Pin inputs if 0.7Vcc/

0.3Vcc CMOS hys-

teresis input levels is

selected for P00,

P03 and P51.

VCC + 0.3

V^IHS1

RST input pin

(CMOS hysteresis)

MD pin*²

⎯

0.8 VCC

⎯

VCC + 0.3

V

V^IHR

V^IHM

VCC − 0.3

⎯

Pin inputs if

⎯

VSS − 0.3

⎯

0.5 VCC

V

Automotive input

V^ILA

levels are selected*¹

Pin inputs if CMOS

hysteresis input

levels are selected*¹

(0.8Vcc/0.2Vcc

VILS2

⎯

VSS − 0.3

⎯

0.2 VCC

V

CMOS hysteresis is

selected for P00,

P03 and P51)

“L” level

input voltage

Pin inputs if 0.7Vcc/

0.3Vcc CMOS hys-

teresis input levels is

selected for P00,

P03 and P51.

⎯

VSS − 0.3

V^ILS1

⎯

0.3 VCC

V

RST input pin

(CMOS hysteresis)

MD pin*²

⎯

VSS − 0.3

V^ILR

V^ILM

⎯

0.2 VCC

V

VSS + 0.3

(Continued)

38

MB90925 Series

(V^CC= 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Parameter Symbol

Pin name

Conditions

Unit Remarks

Min

Typ

Max

Operating frequency

FCP = 16 MHz,

normal operation

⎯

35

45

mA

Operating frequency

F^CP= 16 MHz,

ICC

⎯

50

12

0.4

60

20

1.0

mA

writing Flash memory

Operating frequency

F^CP= 16 MHz,

erasing Flash memory

Flash

mA memory

product

Operating frequency

F^CP= 16 MHz,

sleep mode

I^CCS

mA

Operating frequency

FCP = 2 MHz,

time-base timer mode

I^CTS

Power supply

current*³

VCC

Operating frequency

FCP = 16 MHz,

PLL timer mode,

I^CTSPLL

⎯

4

7

mA

µA

External frequency = 4MHz

Operating frequency

FCP = 8 kHz, TA = + 25 °C,

sub clock operation

I^CCL

90

60

200

150

130

Operating frequency

FCP = 8 kHz, TA = + 25 °C,

sub sleep operation

I^CCLS

Operating frequency

FCP = 8 kHz, TA = + 25 °C,

watch mode

I^CCT

TA = + 25 °C,

I^CCH

⎯

50

130

µA

stop mode

Input leakage

I^IL

VCC = DVCC = AVCC = 5.5 V

VSS < VI < VCC

All input pins

−5

⎯

+5

current

Other than

VCC, VSS,

Input

capacitance 1

DVCC, DVSS,

AVCC,AVSS,C,

P70 to P77,

P80 to P87

C^IN1

⎯

5

15

pF

(Continued)

39

MB90925 Series

(Continued)

(V^CC= 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Parameter

Symbol Pin name

Conditions

Unit

Remarks

Min

⎯

Typ

Max

45

P70 to P77,

P80 to P87

Input capacitance 2

Pull-up resistance

C^IN2

R^UP

⎯

15

pF

kΩ

RST

25

50

100

Except Flash

memory product

Pull-down resistance R^DOWNMD2

25

50

Other than

P70 to P77,

P80 to P87

Output “H”

voltage 1

VCC = 4.5 V

VCC −

VOH1

V^OH2

V^OL1

V^OL2

⎯

V

IOH = −4.0 mA

0.5

Output “H”

voltage 2

P70 to P77, VCC = 4.5 V

P80 to P87 IOH = −30.0 mA

VCC −

0.5

Other than

V^CC= 4.5 V

P70 to P77,

IOL = 4.0 mA

P80 to P87

Output “L”

voltage 1

⎯

0.4

0.55

Output “L”

voltage 2

P70 to P77, VCC = 4.5 V

P80 to P87 IOL = 30.0 mA

PWM1Pn,

V^CC= 4.5 V

PWM1Mn,

IOH = 30.0 mA

Large current

output drive

capacity variation 1

∆V^OH2PWM2Pn,

PWM2Mn,

0

⎯

90

mV *4

VOH2 maximum

variation

(n = 0 to 3)

PWM1Pn,

PWM1Mn,

∆V^OL2PWM2Pn,

V^CC= 4.5 V

IOH = 30.0 mA

VOL2 maximum

variation

Large current

output drive

capacity variation 2

PWM2Mn,

(n = 0 to 3)

LCD internal divider

resistance

RLCD

R^VCOM

R^VSEG

V0 to V3

⎯

50

⎯

100

⎯

200

2.5

15

kΩ

COM0 to COM3

output impedance

COMn

(n = 0 to 3)

SEG0 to SEG31

output impedance

SEGn

(n = 0 to 31)

⎯

V0 to V3

COMm

(m = 0 to 3)

SEGn

LCD leakage

current

I^LCDC

⎯

−5.0

⎯

+5.0

µA

(n = 0 to 31)

*1 : All input pins except X0, X0A, MD0, MD1, and MD2.

*2 : MD0, MD1, and MD2 pins.

*3 : Power supply current values assume external clock feed from the X1 pin and X1A pin. Users must be aware

that power supply current levels differ depending on whether an external clock or oscillator is used.

*4:DefinedasmaximumvariationinV^OH2/VOL2 withallch.0PWM1P0/PWM1M0/PWM2P0/PWM2M0simultaneously

ON. Similarly for other channels.

40

MB90925 Series

4. AC Characteristics

(1) Clock timing

(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Condi-

tions

Parameter

Symbol Pinname

Unit

Remarks

Min

4

Typ

⎯

Max

12

8

MHz 1/2 (when PLL stops)

MHz PLL x 1

4

⎯

F^C

X0, X1

4

⎯

MHz PLL x 2

Base oscillation

clock frequency

4

⎯

5.33 MHz PLL x 3

4

⎯

4

MHz PLL x 4

F^LC

tCYL

X0A, X1A

X0, X1

⎯

32.768

250

30.5

⎯

kHz

ns

Base oscillation

clock cycle time

tLCYL

X0A, X1A

µs

Use duty ratio of

40 to 60% as a guideline

PWH, PWL

P^WLH, PWLL

tcr, tcf

X0

X0A

10

⎯

15.2

⎯

5

ns

µs

ns

⎯

Input clock pulse

width

Input clock

rise and fall time

external

clock signal

X0, X0A

Using main clock

(PLL clock)

FCP

F^LCP

t^CP

⎯

2

⎯

16

⎯

MHz

Internal operating

clock frequency

8.192

—

kHz Using sub clock

Using main clock

(PLL clock)

62.5

⎯

500

⎯

ns

Internal operating

clock cycle time

t^LCP

122.1

µs Using sub clock

• X0 clock timing

tCYL

0.8 VCC

0.2 VCC

X0

PWH

PWL

tcf

tcr

• X0A clock timing

tLCYL

0.8 VCC

0.2 VCC

X0A

PWLL

PWLH

tcf

tcr

41

MB90925 Series

• Range of guaranteed operation

Relation between internal operating clock frequency and power supply voltage

guaranteed operation range

5.5

Guaranteed A/D converter

operation range

4.0

3.7

Guaranteed PLL

operation range

4

16

2

Internal operating clock frequency FCP (MHz)

Note : The MB90F927/ MB90F927S enters reset mode at power supply voltage below 4 V 0.3 V.

Guaranteed oscillation

frequency range

x 4

x 2

x3

16

12

x 1

8

x 1/2

(PLL off)

4

2

16

8

12

4

External clock Fc (MHz)

42

MB90925 Series

(2) Reset input

Parameter

(V^CC= 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Symbol Pin name

Unit

Remarks

Min

Max

500

⎯

ns At normal operation

At stop mode,

ms sub clock mode,

Oscillator oscillation

Reset input time

t^RSTL

RST

⎯

time* + 100 µs

sub sleep mode, and watch mode

100

µs At time-base timer mode

*: Oscillator’s oscillation time is the time that the amplitude reaches 90%. The oscillation time of a crystal oscillator

is between several ms and tens of ms. The oscillation time of a ceramic oscillator is between hundreds of µs

and several ms. The oscillation time of an external clock is 0 ms.

• At normal operation

tRSTL

RST

0.2 VCC

• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on

t

RSTL

RST

0.2 Vcc

90 % of

amplitude

X0

Internal

operation

clock

Oscillator

oscillation time

100 µs

Oscillation stabilization wait time

Execution of the instruction

Internal

reset

43

MB90925 Series

(3) Power-on reset

(V^SS= 0.0 V, TA = −40 °C to +105 °C)

Value

Symbol

Parameter

Conditions

Unit

Remarks

name

Min

0.05

⎯

Max

30

Power supply rise time

t^R

ms

V

Power supply start voltage

Power supply attained voltage

V^OFF

V^ON

0.2

⎯

VCC

⎯

2.7

V

Waiting time until

power-on

Power supply cutoff time

tOFF

50

⎯

ms

tR

2.7 V

VCC

0.2 V

tOFF

Note : Extreme variations in power supply voltage may activate a power-on reset. As the illustration below shows,

when varying power supply voltage during operation, the use of a smooth voltage rise with suppressed

fluctuation is recommended. Also in this situation, the PLL clock on the device should not be used, however

it is permissible to use the PLL clock during a voltage drop of 1V/s or less.

VCC

5.0 V

A rise slope of 50 mV/ms or

3.0 V

less is recommended

RAM data hold

VSS

0 V

44

MB90925 Series

(4) SIO timing

(V^CC= 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Symbol

Conditions

Parameter

Pin name

Unit

Min

8 t^CP

−80

100

60

Max

⎯

Serial clock cycle time

SCK ↓ → SO delay time

Valid SI → SCK ↑

t^SCYC

t^SLOV

t^IVSH

t^SHIX

t^SHSL

t^SLSH

tSLOV

t^IVSH

t^SHIX

SCK

ns

Internal shift clock mode

output pin C^L= 80 pF +

1TTL

SCK, SO

+ 80

⎯

SCK, SI

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO delay time

Valid SI → SCK ↑

⎯

4 tCP

⎯

SCK

⎯

External shift clock mode

output pin C^L= 80 pF +

1TTL

SCK, SO

SCK, SI

150

⎯

60

SCK ↑ → valid SI hold time

60

⎯

Notes : • AC ratings are for CLK synchronous mode.

• C^Lis load capacitance connected to pin during testing.

• tCP is internal operating clock cycle time. Refer to “ (1) Clock timing”.

• Internal shift clock mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.8 V^CC

0.5 VCC

0.8 VCC

0.5 VCC

SI

• External shift clock mode

SCK

tSLSH

tSHSL

0.8 VCC

0.5 VCC

tSLOV

0.5 VCC

2.4 V

0.8 V

SO

SI

tIVSH

tSHIX

0.8 V^CC

0.5 VCC

0.8 VCC

0.5 VCC

45

MB90925 Series

(5) UART0/1 (LIN/SCI)

• Bit setting: ESCR0/1:SCES=0, ECCR0/1:SCDE=0

(V^CC= 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Conditions

Parameter

Symbol

Pin name

Unit

Min

Max

Serial clock cycle time

t^SCYC

t^SLOVI

SCK0, SCK1

5 t^CP

⎯

ns

SCK0, SCK1,

SOT0, SOT1

Internal shift clock

mode output pins are

C^L= 80 pF + 1TTL

SCK ↓ → SOT delay time

− 50

+ 50

Valid SIN → SCK ↑

tIVSHI

t^SHIXI

t^SLSH

tSHSL

t^CP+ 80

0

⎯

ns

SCK0, SCK1,

SIN0, SIN1

SCK ↑ → valid SIN hold time

Serial clock “L” pulse width

Serial clock “H” pulse width

t^CP+ 10

3 tCP − tR

SCK0, SCK1

SCK0, SCK1,

SOT0, SOT1

SCK ↓ → SOT delay time

tSLOVE

⎯

2 tCP + 60

ns

External shift clock

mode output pins are

C^L= 80 pF + 1TTL

Valid SIN → SCK ↑

SCK ↑ → valid SIN hold time

SCK fall time

t^IVSHE

t^SHIXE

tF

30

tCP + 30

⎯

10

ns

SCK0, SCK1,

SIN0, SIN1

SCK0, SCK1

SCK rise time

t^R

⎯

Notes : • AC characteristic in CLK synchronized mode.

• C^Lis load capacity value of pins when testing.

• tCP is internal operating clock cycle time (machine clock). Refer to “ (1) Clock timing”.

46

MB90925 Series

• Internal shift clock mode

tSLSH

tSHSL

SCK

VIH

tF

VIH

tR

VIH

VIL

tSLOVE

VIL

2.4 V

0.8 V

SOT

SIN

tIVSHE

tSHIXE

V^IH

VIL

VIH

VIL

• External shift clock mode

tSLSH

tSHSL

SCK

VIH

tF

VIH

VIL

tSLOVE

VIL

tR

2.4 V

SOT

SIN

0.8 V

tIVSHE

tSHIXE

V^IH

VIL

VIH

VIL

47

MB90925 Series

• Bit setting: ESCR0/1:SCES=1, ECCR0/1:SCDE=0

(V^CC= 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Conditions

Parameter

Symbol

Pin name

Unit

Min

Max

Serial clock cycle time

t^SCYC

t^SLOVI

SCK0, SCK1

5 t^CP

⎯

ns

SCK0, SCK1,

SOT0, SOT1

Internal shift clock

mode output pins are

C^L= 80 pF + 1TTL

SCK ↑ → SOT delay time

− 50

+ 50

Valid SIN → SCK ↓

t^IVSHI

tSHIXI

t^SHSL

t^SLSH

t^CP+ 80

0

⎯

ns

SCK0, SCK1,

SIN0, SIN1

SCK ↓ → valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

3 t^CP− tR

tCP + 10

SCK0, SCK1

SCK0, SCK1,

SOT0, SOT1

SCK ↑ → SOT delay time

tSLOVE

⎯

2 tCP + 60 ns

External shift clock

mode output pins are

C^L= 80 pF + 1TTL

Valid SIN → SCK ↓

SCK ↓ → valid SIN hold time

SCK fall time

tIVSHE

t^SHIX

t^F

30

tCP + 30

⎯

10

ns

SCK0, SCK1,

SIN0, SIN1

SCK0, SCK1

SCK rise time

t^R

⎯

48

MB90925 Series

• Internal shift clock mode

tSCYC

SCK

2.4 V

0.8 V

tSHOVI

2.4 V

SOT

SIN

0.8 V

tIVSLI

tSLIXI

VIH

VIL

VIH

VIL

• External shift clock mode

tSHSL

tSLSH

SCK

VIH

VIL

tR

VIL

tF

tSHOVE

2.4 V

0.8 V

SOT

SIN

tIVSLE

tSLIXE

V^IH

VIH

VIL

49

MB90925 Series

• Bit setting: ESCR0/1:SCES=0, ECCR0/1:SCDE=1

(V^CC= 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Conditions

Parameter

Symbol

Pin name

Unit

Min

Max

Serial clock cycle time

t^SCYC

SCK0, SCK1

5 t^CP

⎯

ns

SCK0, SCK1,

SOT0, SOT1

SCK ↑ → SOT delay time

t^SHOVI

− 50

+ 50

Internal clock operation

output pins are

C^L= 80 pF + 1TTL

Valid SIN → SCK ↓

t^IVSLI

t^CP+ 80

⎯

ns

SCK0, SCK1,

SIN0, SIN1

SCK ↓ → valid SIN hold time

tSLIXI

0

SCK0, SCK1,

SOT0, SOT1

SOT → SCK ↓ delay time

t^SOVLI

3 tCP − 70

⎯

ns

Notes : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing”rating for tCP.

tSCYC

2.4 V

SCK

0.8 V

tSHOVI

tSOVLI

2.4 V

0.8 V

SOT

SIN

0.8 V

tIVSLI

tSLIXI

V^IH

VIH

VIL

50

MB90925 Series

• Bit setting: ESCR0/1:SCES=1, ECCR0/1:SCDE=1

(V^CC= 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Conditions

Parameter

Symbol

Pin name

Unit

Min

Max

Serial clock cycle time

t^SCYC

t^SLOVI

SCK0, SCK1

5 t^CP

⎯

ns

SCK0, SCK1,

SOT0, SOT1

SCK ↓ → SOT delay time

− 50

+ 50

Internal clock operation

output pins are

C^L= 80 pF + 1TTL

Valid SIN → SCK ↑

t^IVSHI

t^CP+ 80

⎯

ns

SCK0, SCK1,

SIN0, SIN1

SCK ↑ → valid SIN hold time

tSHIXI

0

SCK0, SCK1,

SOT0, SOT1

SOT → SCK ↑ delay time

t^SOVHI

3 tCP − 70

⎯

ns

Notes : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing”rating for tCP.

tSCYC

SCK

2.4 V

0.8 V

tSLOVI

tSOVHI

2.4 V

0.8 V

2.4 V

0.8 V

SOT

SIN

tIVSHI

tSHIXI

V^IH

VIL

VIH

VIL

51

MB90925 Series

(6) Timer input timing

(V^CC= 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

t^TIWH

tTIWL

TIN0, TIN1,

IN0 to IN3

Input pulse width

⎯

4 tCP

⎯

ns

Note : t^CPis internal operating clock cycle time. Refer to “ (1) Clock timing”.

• Timer input timing

tTIWH

tTIWL

VIH

TIN0 , TIN1

IN0 to IN3

VIL

52

MB90925 Series

(7) Trigger input timing

(V^CC= 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

200

Max

⎯

INT0 to INT7

ADTG

⎯

ns

t^TRGH,

tTRGL

Input pulse width

t^CP+ 200

⎯

Note : t^CPis internal operating clock cycle time (machine clock) . Refer to “ (1) Clock timing”.

• Trigger input timing

VIH

INT0 to INT7

VIL

tTRGH

tTRGL

53

MB90925 Series

(8) Low voltage detection

(V^SS= AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Symbol

Conditions

Parameter

Pin name

Unit

Remarks

Min

Typ

Max

Duringvoltage

drop

Detection voltage

Hysteresis width

V^DL

VCC

⎯

3.7

4.0

4.3

V

Duringvoltage

rise

V^HYS

0.1

⎯

Powersupplyvoltage

fluctuation ratio

dV/dt

td

V^CC

⎯

−0.1

⎯

+0.02

V/µs

µs

Detection delay time

⎯

35

Internal reset

VCC

dV

dt

Vⁿⁱ

VHYS

td

54

MB90925 Series

5. A/D Converter

(1) Electrical Characteristics

(VCC = AVCC = 5.0 V 10%, 3.0V ≤ AVRH-AVss, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Parameter

Resolution

Symbol Pin name

Unit

Remarks

Min

⎯

Typ

⎯

Max

10

⎯

bit

Total error

⎯

3.0

2.5

1.9

LSB

Non-linear error

Differential linear error

⎯

AVSS −

AVSS +

Zero transition voltage

V^OT

AN0 to AN7

V

1 LSB =

1.5 LSB

0.5 LSB

2.5 LSB

(AVRH − AV^SS) /

Full scale transition

voltage

AVRH −

3.5 LSB

AVRH −

1.5 LSB

AVRH +

0.5 LSB

1024

V^FST

1.4

2.0

0.5

1.2

4.5 V ≤ AVcc ≤ 5.5 V

4.0 V ≤ AVcc ≤ 4.5 V

4.5 V ≤ AVcc ≤ 5.5 V

4.0 V ≤ AVcc ≤ 4.5 V

Sampling time

Compare time

t^SMP

⎯

16500

µs

t^CMP

I^AIN

⎯

µs

Analog port

input current

AN0 to AN7

− 0.3

+0.3

µA

Analog input voltage

Reference voltage

V^AIN

AVRH

I^A

AN0 to AN7

AVRH

AVss

⎯

AVRH

AV^CC

7.5

5

V

AVss+2.7

⎯

3.5

⎯

mA

µA

Power supply current

AVCC

I^AH

*

IR

AVRH

600

⎯

900

5

µA VAVRH = 5.0 V

Reference voltage

supply current

IRH

µA

*

Inter-channel variation

—

AN0 to AN7

⎯

4

LSB

* : Defined as supply current (when V^CC= AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in

stop mode.

55

MB90925 Series

• Notes of the external impedance of the analog input and its sampling time

A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship

between the external impedance and minimum sampling time and either adjust the register value and operating

frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,

if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• Analog input equivalent circuit

R

Analog input

Comparator

C

During sampling : ON

MB90F927/MB90F927S

R

C

4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max) 16.0 pF (Max)

4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max) 16.0 pF (Max)

MB90V925-101/102

4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max) 14.4 pF (Max)

4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max) 14.4 pF (Max)

Note : The values are reference values.

56

MB90925 Series

• The relationship between the external impedance and minimum sampling time

• At 4.5 V ≤ AVcc ≤ 5.5 V

(External impedance = 0 kΩ to 100 kΩ)

(External impedance = 0 kΩ to 20 kΩ)

MB90V925-101/102

100

MB90V925-101/102

20

90

18

16

14

12

10

8

MB90F927/F927S

80

70

60

50

40

30

20

10

0

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [µs]

• At 4.0 V ≤ AVcc ≤ 4.5 V

(External impedance = 0 kΩ to 100 kΩ)

(External impedance = 0 kΩ to 20 kΩ)

MB90V925-101/102

20

MB90V925-101/102

100

18

90

MB90F927/F927S

16

14

12

10

8

80

70

60

50

40

30

20

10

0

6

4

2

0

1

2

3

4

5

6

7

8

0

5

10

15

20

25

30

35

Minimum sampling time [µs]

• About errors

As |AVRH - AV^SS| becomes smaller, values of relative errors grow larger.

57

MB90925 Series

(2) Definition of terms

Resolution :

Analog changes that are identifiable with the A/D converter.

Non-Linear error : The deviation of the straight line connecting the zero transition point

(“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point

(“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics.

Differential linear error : The deviation of input voltage needed to change the output code by 1 LSB from the

ideal value.

Total error :

The total error is defined as a difference between the actual value and the theoretical value,

which includes zero-transition error/full-scale transition error and linear error.

Total error

3FFH

Actualconversion

value

3FEH

3FDH

1.5 LSB

{1 LSB x (N - 1) + 0.5 LSB}

004H

003H

002H

V^NT

(Measured value)

Actualconversion

value

Ideal

001H

characteristics

0.5 LSB

AVSS

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

Total error for digital output N =

[LSB]

1 LSB

AVRH − AV^SS

[V]

1 LSB(Ideal) =

1024

N : A/D converter digital output value

VOT (Ideal) = AVss + 0.5 LSB [V]

VFST (Ideal) = AVRH − 1.5 LSB [V]

VNT : Voltage at a transition of digital output from (N - 1)H to NH

(Continued)

58

MB90925 Series

(Continued)

Non-Linear error

Differential linear error

Ideal

characteristics

Actual conversion

value

{1 LSB x (N -1)

+ V^OT}

3FFH

Actualconversion

value

3FEH

3FDH

N + 1H

V^FST

(Measured

value)

NH

V(N + 1)T

(Measured

value)

VNT

N - 1H

004H

003H

002H

(Measured value)

VNT

Actualconversion

value

(Measured value)

N - 2H

Actualconversion

value

Ideal

characteristics

VOT (Measured value)

001H

AVss

AVRH

AVss

AVRH

Analog input

Non-Linear error of

digital output N

VNT − {1 LSB × (N − 1) + VOT}

=

[LSB]

1 LSB

Differential linear error

of digital output N

V (^N+ 1) T − VNT

− 1 [LSB]

1 LSB

V^FST− VOT

[V]

1 LSB =

1022

N

: A/D converter digital output value

V^OT: Voltage at transition of digital output from “000H” to “001H”

VFST : Voltage at transition of digital output from “3FEH” to “3FFH”

6. Flash Memory Program/Erase Characteristics

Value

Conditions

Parameter

Unit

Remarks

Min

Typ

Max

Excludes pre-programming before

erase

Chip erase time

⎯

1

15

s

T^A= + 25 °C

VCC = 5.0 V

Byte (8-bit width)

programming time

⎯

10000

20

32

⎯

3600

⎯

µs Excludes system-level overhead

cycle

Erase/program cycle

⎯

Flash memory data

retention time

Average

T^A= + 85 °C

⎯

year *

* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C)

59

MB90925 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90F927PF-GE1

MB90F927SPF-GE1

100-pin plastic QFP

(FPT-100P-M06)

MB90F927PFV-GE1

MB90F927SPFV-GE1

100-pin plastic LQFP

(FPT-100P-M05)

MB90V925-101

MB90V925-102

299-pin ceramic PGA

(PGA-299C-A01)

For evaluation

60

MB90925 Series

■ PACKAGE DIMENSIONS

100-pin plastic QFP

Lead pitch

0.65 mm

Package width ×

package length

14.00 × 20.00 mm

Gullwing

Lead shape

Sealing method

Mounting height

Plastic mold

3.35 mm MAX

P-QFP100-14×20-0.65

Code

(Reference)

(FPT-100P-M06)

100-pin plastic QFP

(FPT-100P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

23.90 0.40(.941 .016)

*

20.00 0.20(.787 .008)

80

51

81

50

0.10(.004)

17.90 0.40

(.705 .016)

*

14.00 0.20

(.551 .008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ^–⁺⁰⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8˚

1

30

0.65(.026)

0.32 0.05

(.013 .002)

0.17 0.06

(.007 .002)

M

0.13(.005)

0.25 0.20

(.010 .008)

(Stand off)

0.80 0.20

(.031 .008)

"A"

0.88 0.15

(.035 .006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2002 FUJITSU LIMITED F100008S-c-5-5

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

(Continued)

61

MB90925 Series

(Continued)

100-pin plastic LQFP

Lead pitch

0.50 mm

14.0 × 14.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

0.65g

Code

(Reference)

(FPT-100P-M05)

P-LFQFP100-14×14-0.50

100-pin plastic LQFP

(FPT-100P-M05)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

16.00 0.20(.630 .008)SQ

*

14.00 0.10(.551 .004)SQ

75

51

76

50

0.08(.003)

Details of "A" part

1.50 ⁺–0⁰.^.1²0⁰.059 –⁺.^.0⁰0⁰4⁸

(Mounting height)

INDEX

0.10 0.10

(.004 .004)

(Stand off)

100

26

0˚~8˚

"A"

0.50 0.20

(.020 .008)

0.25(.010)

1

25

0.60 0.15

(.024 .006)

0.50(.020)

0.20 0.05

(.008 .002)

0.145 0.055

(.0057 .0022)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003 FUJITSU LIMITED F100007S-c-4-6

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

62

MB90925 Series

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

The company names and brand names herein are the trademarks or

registered trademarks of their respective owners.

Edited

Business Promotion Dept.

F0705


型号：	MB90V925-101
厂家：	FUJITSU
描述：	16-bit Microcontrolle 16位Microcontrolle
文件：	总63页 (文件大小：932K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90V925-101 [FUJITSU]

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