MB90V930-101 [SPANSION]
暂无描述;
SPANSION 
Spansion® Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion
will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory, analog, and
microcontroller products and solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13754-3E
16-bit Microcontrollers
CMOS
F2MC-16LX MB90930 Series
MB90931/931S/F931/F931S/V930-101/V930-102
■ DESCRIPTION
The MB90930 series is a family of general-purpose FUJITSU SEMICONDUCTOR 16-bit microcontrollers de-
signed for applications such as vehicle instrument panel control.
The instruction set retains the AT architecture from the F2MC-8L and F2MC-16L families, with further refinements
including high-level language instructions, extended addressing modes, improved multiplication and division
operations (signed), and bit processing. In addition, long word processing is made possible by the inclusion of
a built-in 32-bit accumulator.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
Built-in PLL clock frequency multiplication circuit.
Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 8 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 32 MHz).
Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed.
• 16-bit input capture (8 channels)
Detects rising, falling, or both edges.
16-bit capture register × 8
The value of a 16-bit free-run timer counter is latched upon detection of an edge input to pin and an interrupt
request is generated.
• 16-bit reload timer (4 channels)
16-bit reload timer operation (select toggle output or one-shot output)
Selectable event count function
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2009-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.9
MB90930 Series
(Continued)
• Real time watch timer (main clock)
Operates directly from oscillator clock.
Interrupt can be generated by second/minute/hour/date counter overflow.
• PPG timer (6 channels)
Output pins (6 channels), external trigger input pin (1 channel)
Operation clock frequencies : fCP, fCP/22, fCP/24, fCP/26
• Delay interrupt
Generates interrupt for task switching.
Interrupts to CPU can be generated/cleared by software setting.
• External interrupts (8 channels)
8-channel independent operation
Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.
• 8/10-bit A/D converter (24 channels)
Conversion time : 3 μs (at fCP = 32 MHz)
External trigger activation available (P50/INT0/ADTG)
Internal timer activation available (16-bit reload timer 1)
• UART(LIN/SCI) (4 channels)
Equipped with full duplex double buffer
Clock-asynchronous or clock-synchronous serial transfer is available.
• CAN interface (1 channel).
Conforms to CAN specifications version 2.0 Part A and B.
Automatic resend in case of error.
Automatic transfer in response to remote frame.
16 prioritized message buffers for data and ID
Multiple message support
Flexible configuration for receive filter : Full bit compare/full bit mask/two partial bit masks
Supports up to 1 Mbps
CAN wakeup function (RX connected to INT0 internally)
• LCD controller/driver (32 segment × 4 common)
Segment driver and command driver with direct LCD panel (display) drive capability
• Reset on detection of low voltage/program loop
Automatic reset when low voltage is detected.
Program looping detection function
• Stepping motor controller (4 channels)
High current output for each channel × 4
Synchronized 8/10-bit PWM for each channel × 2
• Sound generator (2 channels)
8-bit PWM signal mixed with tone frequency from 8-bit reload counter.
PWM frequencies : 125 kHz, 62.5 kHz, 31.2 kHz, 15.6 kHz (at fCP = 32 MHz)
Tone frequencies : PWM frequency /2/ , divided by (reload frequency +1)
• Input/output ports
General-purpose input/output port (CMOS output) 93 ports
• Function for port input level selection
Automotive/CMOS-Schmitt
• Flash memory security function
Protects the contents of Flash memory (Flash memory product only)
2
DS07-13754-3E
MB90930 Series
■ PRODUCT LINEUP
Part number
MB90V930- MB90V930-
MB90F931
MB90F931S
MB90931
MB90931S
102
101
Parameter
Type
Flash memory
Mask ROM
F2MC-16LX CPU
Evaluation
CPU
PLL clock multiplier circuit ( × 1, × 2, × 3, × 4, × 6, × 8, 1/2 when PLL stopped)
Minimum instruction execution time 31.25ns (with 4 MHz oscillation clock × 8)
System clock
Sub clock pins
(X0A, X1A)
Yes
No
Yes
No
Yes
No
ROM
Flash memory 128 Kbytes
8 Kbytes
93 ports 91 ports
Mask ROM 128 Kbytes
External
RAM
30 Kbytes
I/O port
91 ports
93 ports
91 ports
93 ports
LCD controller
LIN-UART
32 segment × 4 common
UART(LIN/SCI) 4 channels
1 channel
CAN interface
16-bit input capture
16-bit reload timer
8 channels
4 channels
16-bit free-run
timer
1 channel
1 channel
Real time watch
timer
16-bit PPG timer
External interrupt
6 channels
8 channels
8/10-bit
A/D converter
24 channels
Low-voltage/CPU
operatingdetection
reset
Yes
No
Stepping motor
controller
4 channels
2 channels
Sound generator
Flash memory
security
Yes
⎯
Operating voltage
Package
3.7 V to 5.5 V
LQFP-120
4.5 V to 5.5 V
PGA-299
DS07-13754-3E
3
MB90930 Series
■ PIN ASSIGNMENT
(TOP VIEW)
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RST
P30/SEG06
P31/SEG07
P32/SEG08
P33/SEG09
P34/SEG10
P35/SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P92/X0A*1
P93/X1A*2
VCC
1
2
MD0
3
MD1
4
MD2
5
DVSS
6
DVCC
7
P87/PWM2M3/AN23
P86/PWM2P3/AN22
P85/PWM1M3/AN21
P84/PWM1P3/AN20
P83/PWM2M2/AN19
P82/PWM2P2/AN18
P81/PWM1M2/AN17
P80/PWM1P2/AN16
DVSS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LQFP-120
DVCC
VSS
P77/PWM2M1/AN15
P76/PWM2P1/AN14
P75/PWM1M1/AN13
P74/PWM1P1/AN12
P73/PWM2M0/AN11
P72/PWM2P0/AN10
P71/PWM1M0/AN09
P70/PWM1P0/AN08
DVSS
C
P44/SEG18
P45/SEG19
P46/SEG20
P47/SEG21
P90/SEG22
P91/SEG23
PD0/SIN2
PD1/SOT2
PD2/SCK2
PD3/SIN3
PD4/SOT3
PD5/SCK3
PD6/TOT2
DVCC
PE2/SGO1/IN3R
P55/INT2
RSTO
P54/SGA1/IN2R
*1 : The X0A pin is optional. The pin does not exist on the single system product.
*2 : The X1A pin is optional. The pin does not exist on the single system product.
(FPT-120P-M21)
4
DS07-13754-3E
MB90930 Series
■ PIN DESCRIPTIONS
I/O circuit
type*1
Pin no.
Pin name
Function
High-speed oscillation input pin
108
107
X0
X1
A
High-speed oscillation output pin
Low-speed oscillation input pin
General-purpose I/O port
X0A
B
I
13
P92
X1A
B
I
Low-speed oscillation output pin
General-purpose I/O port
14
90
93
P93
RST
C
Reset input pin
P00
General-purpose I/O port
F
F
F
F
F
F
F
F
SEG24
P01
LCD controller/driver segment output pin
General-purpose I/O port
94
95
SEG25
P02
LCD controller/driver segment output pin
General-purpose I/O port
SEG26
P03
LCD controller/driver segment output pin
General-purpose I/O port
96
SEG27
P04
LCD controller/driver segment output pin
General-purpose I/O port
97
SEG28
P05
LCD controller/driver segment output pin
General-purpose I/O port
98
SEG29
P06
LCD controller/driver segment output pin
General-purpose I/O port
99
SEG30
P07
LCD controller/driver segment output pin
General-purpose I/O port
100
SEG31
P10
LCD controller/driver segment output pin
General-purpose I/O port
101
102
103
PPG2
IN5
I
I
I
16-bit PPG ch.2 output pin
Input capture ch.5 trigger input pin
General-purpose I/O port
P11
TOT0
PPG3
IN4
16-bit reload timer ch.0 TOT output pin
16-bit PPG ch.3 output pin
Input capture ch.4 trigger input pin
General-purpose I/O port
P12
TIN0
PPG4
16-bit reload timer ch.0 TIN input pin
16-bit PPG ch.4 output pin
(Continued)
DS07-13754-3E
5
MB90930 Series
I/O circuit
type*1
Pin no.
Pin name
Function
P13
PPG5
P14
General-purpose I/O port
16-bit PPG ch.5 output pin
General-purpose I/O port
104
I
I
I
109
TIN2
16-bit reload timer ch.2 TIN input pin
Input capture ch.1 trigger input pin
General-purpose I/O port
IN1
P15
110
IN0
Input capture ch.0 trigger input pin
LCD controller/driver common output pin
LCD controller/driver common output pin
LCD controller/driver common output pin
LCD controller/driver common output pin
General-purpose I/O port
111
112
113
114
COM0
COM1
COM2
COM3
P22
P
P
P
P
115
116
117
118
119
120
1
F
F
F
F
F
F
F
F
F
F
F
F
SEG00
P23
LCD controller/driver segment output pin
General-purpose I/O port
SEG01
P24
LCD controller/driver segment output pin
General-purpose I/O port
SEG02
P25
LCD controller/driver segment output pin
General-purpose I/O port
SEG03
P26
LCD controller/driver segment output pin
General-purpose I/O port
SEG04
P27
LCD controller/driver segment output pin
General-purpose I/O port
SEG05
P30
LCD controller/driver segment output pin
General-purpose I/O port
SEG06
P31
LCD controller/driver segment output pin
General-purpose I/O port
2
SEG07
P32
LCD controller/driver segment output pin
General-purpose I/O port
3
SEG08
P33
LCD controller/driver segment output pin
General-purpose I/O port
4
SEG09
P34
LCD controller/driver segment output pin
General-purpose I/O port
5
SEG10
P35
LCD controller/driver segment output pin
General-purpose I/O port
6
SEG11
LCD controller/driver segment output pin
(Continued)
6
DS07-13754-3E
MB90930 Series
I/O circuit
type*1
Pin no.
Pin name
Function
P36
SEG12
P37
General-purpose I/O port
7
F
F
F
F
F
F
F
F
F
F
LCD controller/driver segment output pin
General-purpose I/O port
8
SEG13
P40
LCD controller/driver segment output pin
General-purpose I/O port
9
SEG14
P41
LCD controller/driver segment output pin
General-purpose I/O port
10
11
12
18
19
20
21
SEG15
P42
LCD controller/driver segment output pin
General-purpose I/O port
SEG16
P43
LCD controller/driver segment output pin
General-purpose I/O port
SEG17
P44
LCD controller/driver segment output pin
General-purpose I/O port
SEG18
P45
LCD controller/driver segment output pin
General-purpose I/O port
SEG19
P46
LCD controller/driver segment output pin
General-purpose I/O port
SEG20
P47
LCD controller/driver segment output pin
General-purpose I/O port
SEG21
P50
LCD controller/driver segment output pin
General-purpose I/O port
37
58
INT0
ADTG
P51
I
I
INT0 external interrupt input pin
A/D converter external trigger input pin
General-purpose I/O port
INT1
RX1
INT1 external interrupt input pin
CAN interface 1 RX input pin
P52
General-purpose I/O port
59
60
I
I
TX1
CAN interface 1 TX output pin
General-purpose I/O port
P53
INT3
INT3 external interrupt input pin
(Continued)
DS07-13754-3E
7
MB90930 Series
I/O circuit
type*1
Pin no.
Pin name
Function
P54
SGA1
IN2R
P55
General-purpose I/O port
61
I
I
Sound generator ch.1 SGA output pin
Input capture ch.2 trigger input pin
General-purpose I/O port
INT2 external interrupt input pin
General-purpose I/O port
Sound generator ch.0 SGO output pin
Free-run timer clock input pin
Input capture ch.5 trigger input pin
General-purpose I/O port
Sound generator ch.0 SGA output pin
Input capture ch.4 trigger input pin
General-purpose I/O port
A/D converter input pin
63
91
INT2
P56
SGO0
FRCK
IN5R
P57
I
I
92
SGA0
IN4R
P60
39
40
41
42
43
44
45
H
H
H
H
H
H
H
AN0
P61
General-purpose I/O port
A/D converter input pin
AN1
P62
General-purpose I/O port
A/D converter input pin
AN2
P63
General-purpose I/O port
A/D converter input pin
AN3
P64
General-purpose I/O port
A/D converter input pin
AN4
P65
General-purpose I/O port
A/D converter input pin
AN5
P66
General-purpose I/O port
A/D converter input pin
AN6
(Continued)
8
DS07-13754-3E
MB90930 Series
I/O circuit
type*1
Pin no.
Pin name
Function
P67
AN7
General-purpose I/O port
A/D converter input pin
46
H
P70
General-purpose output-only port
Stepping motor controller ch.0 output pin
A/D converter input pin
67
68
69
70
71
72
73
74
77
78
PWM1P0
AN08
L
P71
General-purpose output-only port
Stepping motor controller ch.0 output pin
A/D converter input pin
PWM1M0
AN09
L
L
L
L
L
L
L
L
L
P72
General-purpose output-only port
Stepping motor controller ch.0 output pin
A/D converter input pin
PWM2P0
AN10
P73
General-purpose output-only port
Stepping motor controller ch.0 output pin
A/D converter input pin
PWM2M0
AN11
P74
General-purpose output-only port
Stepping motor controller ch.1 output pin
A/D converter input pin
PWM1P1
AN12
P75
General-purpose output-only port
Stepping motor controller ch.1 output pin
A/D converter input pin
PWM1M1
AN13
P76
General-purpose output-only port
Stepping motor controller ch.1 output pin
A/D converter input pin
PWM2P1
AN14
P77
General-purpose output-only port
Stepping motor controller ch.1 output pin
A/D converter input pin
PWM2M1
AN15
P80
General-purpose output-only port
Stepping motor controller ch.2 output pin
A/D converter input pin
PWM1P2
AN16
P81
General-purpose output-only port
Stepping motor controller ch.2 output pin
A/D converter input pin
PWM1M2
AN17
(Continued)
DS07-13754-3E
9
MB90930 Series
I/O circuit
type*1
Pin no.
Pin name
Function
General-purpose output-only port
P82
PWM2P2
AN18
P83
79
L
L
L
L
L
L
Stepping motor controller ch.2 output pin
A/D converter input pin
General-purpose output-only port
Stepping motor controller ch.2 output pin
A/D converter input pin
80
81
82
83
84
PWM2M2
AN19
P84
General-purpose output-only port
Stepping motor controller ch.3 output pin
A/D converter input pin
PWM1P3
AN20
P85
General-purpose output-only port
Stepping motor controller ch.3 output pin
A/D converter input pin
PWM1M3
AN21
P86
General-purpose output-only port
Stepping motor controller ch.3 output pin
A/D converter input pin
PWM2P3
AN22
P87
General-purpose output-only port
Stepping motor controller ch.3 output pin
A/D converter input pin
PWM2M3
AN23
P90
General-purpose I/O port
22
23
31
32
F
F
SEG22
P91
LCD controller/driver segment output pin
General-purpose I/O port
SEG23
P94
LCD controller/driver segment output pin
General-purpose I/O port
G
G
V0
LCD controller/driver reference power supply pin
General-purpose I/O port
P95
V1
LCD controller/driver reference power supply pin
General-purpose I/O port
P96
33
34
G
V2
LCD controller/driver reference power supply pin
LCD controller/driver reference power supply pin
General-purpose I/O port
V3
⎯
PC0
48
SIN0
J
UART ch.0 serial data input pin
INT4 external interrupt input pin
INT4
(Continued)
10
DS07-13754-3E
MB90930 Series
I/O circuit
type*1
Pin no.
Pin name
Function
PC1
SOT0
INT5
IN3
General-purpose I/O port
UART ch.0 serial data output pin
INT5 external interrupt input pin
Input capture ch.3 trigger input pin
General-purpose I/O port
49
I
I
PC2
SCK0
INT6
IN2
UART ch.0 serial clock I/O pin
INT6 external interrupt input pin
Input capture ch.2 trigger input pin
General-purpose I/O port
50
PC3
51
52
53
SIN1
INT7
PC4
J
I
UART ch.1 serial data input pin
INT7 external interrupt input pin
General-purpose I/O port
SOT1
PC5
UART ch.1 serial data output pin
General-purpose I/O port
SCK1
TRG
PC6
I
UART ch.1 serial clock I/O pin
16-bit PPG ch.0 to ch.5 external trigger input pin
General-purpose I/O port
PPG0
TOT1
IN7
16-bit PPG ch.0 output pin
54
55
I
I
16-bit reload timer ch.1 TOT output pin
Input capture ch.7 trigger input pin
General-purpose I/O port
PC7
PPG1
TIN1
IN6
16-bit PPG ch.1 output pin
16-bit reload timer ch.1 TIN input pin
Input capture ch.6 trigger input pin
General-purpose I/O port
PD0
24
25
26
27
J
I
SIN2
PD1
UART ch.2 serial data input pin
General-purpose I/O port
SOT2
PD2
UART ch.2 serial data output pin
General-purpose I/O port
F
J
SCK2
PD3
UART ch.2 serial clock I/O pin
General-purpose I/O port
SIN3
UART ch.3 serial data input pin
(Continued)
DS07-13754-3E
11
MB90930 Series
(Continued)
I/O circuit
type*1
Pin no.
Pin name
Function
PD4
SOT3
PD5
General-purpose I/O port
28
I
F
I
UART ch.3 serial data output pin
General-purpose I/O port
29
30
SCK3
PD6
UART ch.3 serial clock I/O pin
General-purpose I/O port
TOT2
PE0
16-bit reload timer ch.2 TOT output pin
General-purpose I/O port
56
57
64
TOT3
IN7R
PE1
I
I
I
16-bit reload timer ch.3 TOT output pin
Input capture ch.7 trigger input pin
General-purpose I/O port
TIN3
IN6R
PE2
16-bit reload timer ch.3 TIN input pin
Input capture ch.6 trigger input pin
General-purpose I/O port
SGO1
IN3R
RSTO
DVCC
DVSS
AVCC
AVSS
AVRH
MD0
Sound generator ch.1 SGO output pin
Input capture ch.3 trigger input pin
62
N
⎯
Internal reset signal output pin
65, 75, 85
Power supply input pins dedicated for high current output buffer
Power supply GND pins dedicated for high current output buffer
A/D converter dedicated power supply input pin
A/D converter dedicated power supply GND pin
A/D converter Vref+ input pin. Vref- is fixed to AVSS.
Mode setting input pin. Connect to VCC pin.
Mode setting input pin. Connect to VCC pin.
Mode setting input pin. Connect to VSS pin.
66, 76, 86
⎯
35
38
36
89
88
87
⎯
⎯
⎯
D
MD1
D
D/E*2
MD2
External capacitor pin.
Connect a 0.1 μF capacitor between this pin and the VSS pin.
17
C
⎯
15, 105
VCC
VSS
⎯
⎯
Power supply input pins
GND power supply pins
16, 47, 106
*1 : For I/O circuit type, refer to “ ■ I/O CIRCUIT TYPE”.
*2 : The I/O circuit type is D for Flash memory products/Mask ROM products and E for evaluation products.
12
DS07-13754-3E
MB90930 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
High-speed oscillation pin
(Flash memory product, Mask ROM
product)
X1
X0
Oscillation feedback resistance :
approx. 1 MΩ
XOUT
Standby control signal
High-speed oscillation pin
(Evaluation product)
X1
X0
Oscillation feedback resistance :
approx. 1 MΩ
Xout
Standby control signal
B
low-speed oscillation pin
Oscillation feedback resistance :
approx. 10 MΩ
X1A
Xout
X0A
Standby control signal
C
Input-only pin (with pull-up resistance)
• Attached pull-up resistor :
approx. 50 kΩ
Pull-up resistor
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
CMOS hysteresis input
CMOS hysteresis input
D
Input-only pin
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
Note: The MD2 pin of the Flash
memory products uses this
circuit type.
(Continued)
DS07-13754-3E
13
MB90930 Series
Type
Circuit
Remarks
E
Input-only pin (with pull-down
resistance)
• Attached pull-down resistance :
approx. 50 kΩ
CMOS hysteresis input
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
Pull-down resistor
Note: TheMD2pinoftheMaskROM
products and the evaluation
products uses this circuit type.
F
LCD output common general-
purpose port
• CMOS output
Pout
P-ch
N-ch
(IOH/IOL =
4 mA)
• Hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
Nout
LCD input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal or
LCD input enable signal
Automotive input
Standby control signal or
LCD input enable signal
G
LCDC reference power supply com-
mon general-purpose port
• CMOS output (IOH/IOL = 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
Pout
Nout
P-ch
N-ch
(VIH/VIL = 0.8 VCC/0.5 VCC)
LCDCreferencepowersupply
input
CMOS hysteresis input
Standby control signal or
LCD output switching signal
Automotive input
Standby control signal or
LCD output switching signal
(Continued)
14
DS07-13754-3E
MB90930 Series
Type
Circuit
Remarks
H
A/D converter input common
general-purpose port
• CMOS output
Pout
P-ch
(IOH/IOL =
4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
Nout
N-ch
Analog input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal or
analog input enable signal
Automotive input
Standby control signal or
analog input enable signal
I
General-purpose port
• CMOS output (IOH/IOL = 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
Pout
Nout
P-ch
N-ch
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal
Automotive input
Standby control signal
J
General-purpose port (serial input)
• CMOS output (IOH/IOL = 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
P-ch
Pout
Nout
N-ch
(VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
CMOS hysteresis input
Standby control signal
(VIH/VIL = 0.8 VCC/0.5 VCC)
Automotive input
Standby control signal
CMOS input (SIN)
Standby control signal
(Continued)
DS07-13754-3E
15
MB90930 Series
Type
Circuit
Remarks
K
A/D converter input common gen-
eral-purpose port (serial input)
• CMOSoutput(IOH/IOL = 4mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
Pout
Nout
P-ch
N-ch
Analog output
(VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal or
analog input enable signal
Automotive input
Standby control signal or
analog input enable signal
CMOS input (SIN)
Standby control signal or
analog input enable signal
L
A/D converter input common and
high current output port (SMC pin)
CMOS output (IOH/IOL = 30 mA)
Pout
High current
Nout
P-ch
N-ch
Analog input
(Continued)
16
DS07-13754-3E
MB90930 Series
(Continued)
Type
Circuit
Remarks
M
LCDC output common general-
purpose port (serial input) )
• CMOS output (IOH/IOL = 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
Pout
Nout
P-ch
N-ch
LCDC output
(VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal or
LCDC output switching signal
Automotive input
Standby control signal or
LCDC output switching signal
CMOS input (SIN)
Standby control signal or
LCDC output switching signal
N
N-ch open-drain pin
IOL = 4 mA
Flash / Mask product
Evaluation product
P-ch
Nout
Nout
N-ch
N-ch
O
P
Input-only pin
Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
Automotive input
LCDC output pin (COM pin)
P-ch
LCDC output
N-ch
DS07-13754-3E
17
MB90930 Series
■ HANDLING DEVICES
• Strictly observe maximum rated voltages (preventing latch-up)
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are
applied to input or output pins other than medium or high withstand voltage pins, or if the voltage applied between
VCC and VSS pins exceeds the rated voltage level. If a latch-up occurs, the power supply current may increase
dramatically and may destroy semiconductor elements. When using semiconductor devices, always take suffi-
cient care to avoid exceeding maximum ratings.
When the analog system power supply is switched on or off, be careful not to apply the analog power supply
(AVCC, AVRH), the analog input voltages and the power supply voltage for the high current output buffer pins
(DVCC) in excess of the digital power supply voltage (VCC).
Once the digital power supply voltage (VCC) has been disconnected, the analog power supply (AVCC, AVRH) and
the power supply voltage for the high current output buffer pins (DVCC) may be turned on in any sequence.
• Supply voltage stabilization
Rapid fluctuations in the power supply voltage can cause malfunctions even if the Vcc power supply voltage
remains within the warranted operating range. It is recommended that the power supply be stabilized such that
ripple fluctuations (P-P value) at commercial frequencies (50 Hz/60 Hz) be limited to within 10% of the standard
VCC value, andthattransientfluctuationsduetopowersupplyswitching, etc. belimitedtoarateof0.1V/msorless.
• Precautions when turning the power on
In order to prevent the built-in step-down circuits from malfunctioning, the time taken for the voltage to rise
(0.2 V to 2.7 V) during power-on should be less than 50 μs.
• Handling unused pins
If unused input pins are left open, they may cause malfunctions or latch-up which may lead to permanent damage
to the semiconductor. Unused input pins should therefore be pulled up or pulled down through a resistor of at
least 2 kΩ.
Unused input/output pins may be set to the output state and left open, or set to the input state and connected
to a pull-up or pull-down resistance of 2 kΩ or more.
• Handling A/D converter power supply pins
Even if the A/D converter is not used, the power supply pins should be connected such as AVCC = VCC, and
AVSS = AVRH = VSS.
• Notes on using an external clock
Even when an external clock is used, an oscillation stabilization wait time is required following power-on reset
or release from sub clock mode or stop mode. Furthermore, only the X0A pin should be driven when an external
clock is used, with the X1A pin open as shown in the following diagram. Do not use high-speed oscillation pins
(X0 and X1) for external clock input.
X0A
OPEN
X1A
MB90930 Series
Sample external clock connection
18
DS07-13754-3E
MB90930 Series
• Notes on operating in PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off while the PLL clock mode is selected, a self-
oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, FUJITSU
SEMICONDUCTOR will not guarantee results of operations if such failure occurs.
• Crystal oscillator circuit
Noise around the X0/X1 may cause this device to operate abnormally. Make sure to provide bypass capacitors
via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure,
to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits while you design a
printed circuit board.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Power supply pins
Devices including multiple VCC or VSS pins are designed such that pins that need to be at the same potential
are interconnected internally to prevent malfunctions such as latch-up. To reduce unnecessary radiation, prevent
malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output
current, be sure to externally connect the VCC and VSS pins to the power supply and ground respectively.
Always connect all of the VCC pins to the same potential and all of the VSS pins to ground as shown in the
following diagram. The device will not operate correctly if multiple VCC or VSS pins are connected to different
voltages, even if those voltages are within the guaranteed operating ranges.
V
V
CC
SS
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
Power supply input pins (Vcc/Vss)
In addition, care must be given to connecting the VCC and VSS pins of this device to the current supply source
with as low impedance as possible. It is recommended that a 1.0 μF bypass capacitor be connected between
the VCC and VSS pins as close to the pins as possible.
DS07-13754-3E
19
MB90930 Series
• Sequence for connecting the A/D converter power supply and analog inputs
The A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN23) must be applied after the digital
power supply (VCC) is switched on. When turning the power off, the A/D converter power supply and analog
inputs must be disconnected before the digital power supply is switched off (VCC). Ensure that AVRH does not
exceed AVcc during either power-on or power-off. Even when pins which double as analog input pins are used
as input ports, be sure that the input voltage does not exceed AVCC (turning on/off the analog and digital power
supplies simultaneously is acceptable).
• Handling the power supply for high-current output buffer pins (DVCC, DVSS)
• Flash memory products/Mask ROM products (MB90F931/MB90F931S/MB90931/MB90931S)
In the Flash memory products/Mask ROM products, the power supply for the high-current output buffer pins
(DVCC, DVSS) is isolated from the digital power supply (VCC). Therefore, DVcc can be set to a higher voltage
than Vcc. If the power supply for the high-current output buffer pins (DVCC, DVSS) is supplied before the digital
power supply (VCC), however, care needs to be taken because it is possible that the port 7 or port 8 stepping
motor outputs may momentarily output an “H” or “L” level during the DVcc rise. In order to prevent this, connect
the digital power supply (VCC) prior to connecting the power supply for the high-current output buffer pins.
Even when the high-current output buffer pins are used as general-purpose ports, power should be supplied
to the power supply pins for the high-current output buffer pins (DVCC, DVSS).
• Evaluation product (MB90V930-102/MB90V930-101)
In the evaluation products, the power supply for the high-current output buffer pins (DVCC, DVSS) is not isolated
from the digital power supply (VCC). Therefore, DVcc must be set to a lower voltage than Vcc. The power supply
for the high-current output buffer pins (DVCC, DVSS) must always be applied after the digital power supply
(VCC) has been connected, and disconnected before the digital power supply (Vcc) is disconnected (the power
supply for the high-current output buffer pins may also be connected and disconnected simultaneously with
the digital power supply).
Even when the high-current output buffer pins are used as general-purpose ports, power should be supplied
to the power supply pins for the high-current output buffer pins (DVCC, DVSS).
• Pull-up/pull-down resistors
MB90930 series does not support internal pull-up/pull-down resistors. Use external components as necessary.
• Precautions when not using a sub clock signal
If the X0A and X1A pins are not connected to an oscillator, apply a pull-down resistance to the X0A pin and
leave the X1A pin open.
• Flash memory security function
A security bit is located within the Flash memory region. The security function is activated by writing the protection
code 01H to the security bit.
Do not write the value 01H to this address if you are not using the security function.
Please refer to following table for the address of the security bit.
Flash memory size
Address for security bit
MB90F931
MB90F931S
Built-in 1 Mbit Flash Memory
FE0001H
20
DS07-13754-3E
MB90930 Series
• Serial communication
In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a print-
ed circuit board to prevent noise from occurring. Taking account of the reception of wrong data, detect errors by
measures such as adding a checksum to the end of data. If an error is detected, retransmit the data.
• Characteristic difference between flash device and mask ROM device
In the flash device and the mask ROM device, the electrical characteristic including current consumption, ESD,
latch-up, the noise characteristic, and oscillation characteristic, etc. is different according to the difference between
the chip layout and the memory structure.
Reconfirm the electrical characteristic when the product is replaced by another product of the same series.
DS07-13754-3E
21
MB90930 Series
■ BLOCK DIAGRAM
CPU
F2MC-16LX core
Clock control circuit
Watchdog timer
Time-base timer
Interrupt controller
Low-voltage reset
Watch timer
(for sub clock)
Sound generator 0
Sound generator 1
CPU operation
detection reset
CAN controller 1
External interrupt
(8 channels)
Stepping motor controller 0
LIN-UART 0
Prescaler 0
Stepping motor controller 1
Stepping motor controller 2
LIN-UART 1
Prescaler 1
LIN-UART 2
Prescaler 2
LIN-UART 3
Prescaler 3
Stepping motor controller 3
A/D converter
(24 channels)
16-bit PPG timer 0
16-bit PPG timer 1
16-bit PPG timer 2
LCD controller/driver
(32 SEG/4 COM)
16-bit PPG timer 3
16-bit PPG timer 4
RAM
(8 Kbytes)*
16-bit PPG timer 5
Flash / ROM
(128 Kbytes)*
16-bit reload timer 0
16-bit reload timer 1
16-bit reload timer 2
16-bit reload timer 3
Real-time watch timer
16-bit ICU 0 (2 channels)
16-bit ICU 1 (2 channels)
16-bit ICU 2 (2 channels)
16-bit ICU 3 (2 channels)
16-bit free-run timer
* : Flash memory products/Mask ROM products.
22
DS07-13754-3E
MB90930 Series
■ MEMORY MAP
MB90V930-102/
MB90V930-101
MB90F931/MB90F931S
MB90931/MB90931S
000000
H
000000
H
Peripheral area
Peripheral area
0000F0
H
H
0000F0
000100
H
H
000100
Register
Register
RAM area
(8 Kbytes)
RAM area
(13.5 Kbytes)
002100
H
003700
004000
H
H
003700
004000
H
H
Peripheral area
Peripheral area
RAM area
(16 Kbytes)
008000
H
008000
010000
H
H
ROM area
(FF bank image)
ROM area
(FF bank image)
010000
H
H
F80000
FE0000
FFFFFF
H
H
ROM decoding area
Flash / ROM area
(128 Kbytes)
FFFFFF
H
: Internal access prohibited
Note: To select models without the ROM mirror function, refer to the “ROM Mirror Function Selection Module” in
Hardware Manual. The image of the ROM data in the FF bank appears at the top of the 00 bank, in order
to enable efficient use of small C compiler models. The lower 16-bits of the FF bank addresses are allocated
to the same addresses as the lower 16-bits of the 00 bank, making it possible to reference tables in ROM
without declaring the “far” modifier with the pointers. For example, when an access is made to the address
00C000H, the actual address to be accessed is FFC000H in ROM. Because the size of the FF bank ROM
area exceeds 32 Kbytes, it is not possible to view the entire region in the 00 bank image. Therefore because
the ROM data from FF8000H to FFFFFFH appears in the image from 008000H to 00FFFFH, it is recommended
that ROM data tables be stored in the area from FF8000H to FFFFFFH.
DS07-13754-3E
23
MB90930 Series
■ I/O MAP
Address
Register name
Symbol Read/write Resource name Initial value
000000H Port 0 data register
000001H Port 1 data register
000002H Port 2 data register
000003H Port 3 data register
000004H Port 4 data register
000005H Port 5 data register
000006H Port 6 data register
000007H Port 7 data register
000008H Port 8 data register
000009H Port 9 data register
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000AH,
00000BH
(Disabled)
00000CH Port C data register
00000DH Port D data register
00000EH Port E data register
00000FH
PDRC
PDRD
PDRE
R/W
R/W
R/W
Port C
Port D
Port E
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Disabled)
000010H Port 0 direction register
000011H Port 1 direction register
000012H Port 2 direction register
000013H Port 3 direction register
000014H Port 4 direction register
000015H Port 5 direction register
000016H Port 6 direction register
000017H Port 7 direction register
000018H Port 8 direction register
000019H Port 9 direction register
00001AH Analog input enable
00001BH Analog input enable
00001CH Port C direction register
00001DH Port D direction register
00001EH Port E direction register
00001FH Analog input enable
000020H Lower A/D control status register
000021H Higher A/D control status register
000022H Lower A/D data register
000023H Higher A/D data register
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
ADER6
ADER7
DDRC
DDRD
DDRE
ADER8
ADCS0
ADCS1
ADCR0
ADCR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Port 0
Port 1
00000000B
XX000000B
000000XXB
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
X0000000B
11111111B
11111111B
00000000B
X0000000B
XXXXX000B
11111111B
000XXXX0B
0000000XB
00000000B
XXXXXX00B
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 6, A/D
Port7, A/D
Port C
Port D
Port E
Port8, A/D
A/D converter
R
(Continued)
24
DS07-13754-3E
MB90930 Series
Address
000024H
000025H
000026H
000027H
Register name
Compare clear register
Symbol Read/write Resource name Initial value
R/W
R/W
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
01X00000B
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
CPCLR
TCDT
R/W
16-bit
Timer data register
free-run timer
R/W
000028H Lower timer control status register
000029H Higher timer control status register
00002AH Lower PPG0 control status register
00002BH Higher PPG0 control status register
00002CH Lower PPG1 control status register
00002DH Higher PPG1 control status register
00002EH Lower PPG2 control status register
00002FH Higher PPG2 control status register
000030H External interrupt enable
TCCSL
TCCSH
PCNTL0
PCNTH0
PCNTL1
PCNTH1
PCNTL2
PCNTH2
ENIR
R/W
R/W
R/W
16-bit PPG0
16-bit PPG1
16-bit PPG2
R/W
R/W
R/W
R/W
R/W
R/W
000031H External interrupt request
EIRR
R/W
External interrupt
000032H Lower external interrupt level
000033H Higher external interrupt level
000034H Serial mode register 0
ELVRL
ELVRH
SMR0
R/W
R/W
R/W, W
R/W, W
000035H Serial control register 0
SCR0
RDR0/
TDR0
000036H Reception/transmission data register 0
000037H Serial status register 0
R/W
00000000B
00001000B
000000XXB
SSR0
R/W, R
R/W, R
UART
(LIN/SCI) 0
Extended communication control
000038H
ECCR0
register 0
000039H Extended status control register 0
00003AH Baud rate generator register 00
00003BH Baud rate generator register 01
ESCR0
BGR00
BGR01
R/W
R/W
00000100B
00000000B
00000000B
R/W, R
00003CH
to
(Disabled)
000047H
Input capture
0/1/2/3/4/5/6/7
000048H Input capture input select register
ICISR
R/W
00000000B
000049H
(Disabled)
(Disabled)
00004AH
to
00004FH
(Continued)
DS07-13754-3E
25
MB90930 Series
Address
Register name
Symbol Read/write Resource name Initial value
000050H Lower timer control status register 0
000051H Higher timer control status register 0
TMCSR0L
TMCSR0H
R/W
R/W
00000000B
XXX10000B
XXXXXXXXB
XXXXXXXXB
00000000B
16-bit reload timer
0
000052H
TMR0/
TMRLR0
Timer register 0/reload register 0
000053H
R/W
000054H Lower timer control status register 1
000055H Higher timer control status register 1
TMCSR1L
TMCSR1H
R/W
R/W
XXX10000B
XXXXXXXXB
XXXXXXXXB
11111111B
16-bit reload timer
1
000056H
TMR1/
TMRLR1
Timer register 1/reload register 1
000057H
R/W
000058H LCD output control register 1
000059H LCD output control register 2
00005AH Lower sound control register 0
00005BH Higher sound control register 0
00005CH Frequency data register 0
00005DH Amplitude data register 0
00005EH Decrement grade register 0
00005FH Tone count register 0
LOCR1
LOCR2
SGCRL0
SGCRH0
SGFR0
SGAR0
SGDR0
SGTR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCDC
00000000B
00000000B
0XXXX100B
XXXXXXXXB
00000000B
Sound generator 0
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
000060H
Input capture register 0
000061H
IPCP0
IPCP1
IPCP2
IPCP3
R
R
R
R
Input capture 0/1
Input capture 2/3
000062H
Input capture register 1
000063H
000064H
Input capture register 2
000065H
000066H
Input capture register 3
000067H
000068H Input capture control status 0/1
000069H Input capture edge register 0/1
00006AH Input capture control status 2/3
00006BH Input capture edge register 2/3
00006CH Lower LCD control register
00006DH Higher LCD control register
ICS01
ICE01
ICS23
ICE23
LCRL
LCRH
R/W
R/W
R/W
R/W
R/W
R/W
Input capture 0/1
Input capture 2/3
XXX0X0XXB
00000000B
XXXXXXXXB
00010000B
LCD controller/
driver
00000000B
Low voltage/CPU
operation
detection reset
Low voltage/CPU operation
00006EH
LVRC
R/W
W
00111000B
detection reset control register
00006FH ROM mirror
ROMM
ROM mirror
XXXXXXX1B
(Continued)
26
DS07-13754-3E
MB90930 Series
Address
Register name
Symbol Read/write Resource name Initial value
000070H
to
Area reserved for CAN Controller 1(Refer to “■ CAN CONTROLLERS”).
00007FH
Stepping motor
controller 0
000080H PWM control register 0
000081H
PWC0
(Disabled)
PWC1
(Disabled)
PWC2
(Disabled)
PWC3
R/W
R/W
R/W
000000X0B
000000X0B
000000X0B
Stepping motor
controller 1
000082H PWM control register 1
000083H
Stepping motor
controller 2
000084H PWM control register 2
000085H
Stepping motor
controller 3
000086H PWM control register 3
R/W
R/W
000000X0B
XXXXX111B
000087H
(Disabled)
LOCR3
(Disabled)
000088H LCD output control register 3
000089H
LCDC
00008AH A/D setting register 0
00008BH A/D setting register 1
00008CH Port input level select 0
00008DH Port input level select 1
00008EH Port input level select 2
ADSR0
ADSR1
PIL0
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
XXXX0000B
XXXX0000B
A/D converter
Port input level
select
PIL1
PIL2
00008FH
to
(Disabled)
00009DH
Program address detection control
Address match
detection
00009EH
register
PACSR
DIRR
R/W
R/W
XXXX0X0XB
XXXXXXX0B
Delayed Interrupt source generation /
Release Register
00009FH
Delay interrupt
0000A0H Power saving mode control register
0000A1H Clock select register
LPMCR
CKSCR
R/W
00011000B
11111100B
Power saving
control circuit
R/W, R
0000A2H
to
(Disabled)
0000A7H
0000A8H Watchdog timer control register
0000A9H Time-base timer control register
WDTC
TBTC
R, W
Watchdog timer
Time-base timer
XXXXX111B
1XX00100B
R/W, W
Watch timer
(sub clock)
0000AAH Watch timer control register
WTC
R/W, W, R
10001000B
0000ABH
to
(Disabled)
0000ADH
(Continued)
DS07-13754-3E
27
MB90930 Series
Address
Register name
Symbol Read/write Resource name Initial value
0000AEH Flash memory control status register
0000AFH
FMCS
(Disabled)
R/W
Flash interface
000X0000B
0000B0H Interrupt control register 00
0000B1H Interrupt control register 01
0000B2H Interrupt control register 02
0000B3H Interrupt control register 03
0000B4H Interrupt control register 04
0000B5H Interrupt control register 05
0000B6H Interrupt control register 06
0000B7H Interrupt control register 07
0000B8H Interrupt control register 08
0000B9H Interrupt control register 09
0000BAH Interrupt control register 10
0000BBH Interrupt control register 11
0000BCH Interrupt control register 12
0000BDH Interrupt control register 13
0000BEH Interrupt control register 14
0000BFH Interrupt control register 15
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
Interrupt controller
0000C0H
to
(Disabled)
0000C3H
0000C4H Serial mode register 1
0000C5H Serial control register 1
SMR1
SCR1
R/W, W
R/W, W
00000000B
00000000B
Reception/transmission
0000C6H
RDR1/
TDR1
R/W
00000000B
00001000B
000000XXB
data register 1
0000C7H Serial status register 1
SSR1
R/W, R
R/W, R
UART
(LIN/SCI) 1
Extended communication
0000C8H
ECCR1
control register 1
0000C9H Extended status control register 1
0000CAH Baud rate generator register 10
0000CBH Baud rate generator register 11
0000CCH Lower watch timer control register
0000CDH Middle watch timer control register
0000CEH Higher watch timer control register
ESCR1
BGR10
BGR11
WTCRL
WTCRM
WTCRH
R/W
R/W
00000100B
00000000B
00000000B
000XXXX0B
00000000B
XXXXXX00B
(Continued)
R/W, R
R/W
Real-time
watch timer
R/W
R/W
28
DS07-13754-3E
MB90930 Series
Address
Register name
Symbol Read/write Resource name Initial value
0000CFH PLL/Sub clock control register
0000D0H Input capture control status 4/5
0000D1H Input capture edge register 4/5
0000D2H Input capture control status 6/7
0000D3H Input capture edge register 6/7
0000D4H Lower timer control status register 2
0000D5H Higher timer control status register 2
0000D6H Lower timer control status register 3
0000D7H Higher timer control status register 3
0000D8H Lower sound control register 1
0000D9H Higher sound control register 1
0000DAH Lower PPG3 control status register
0000DBH Higher PPG3 control status register
0000DCH Lower PPG4 control status register
0000DDH Higher PPG4 control status register
0000DEH Lower PPG5 control status register
0000DFH Higher PPG5 control status register
0000E0H Serial mode register 2
PSCCR
ICS45
W
R/W
PLL/Sub clock
XXXX0000B
00000000B
XXXXXXXXB
00000000B
XXX0X0XXB
00000000B
XXX10000B
00000000B
XXX10000B
00000000B
0XXXX100B
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
00000000B
00000000B
Input capture 4/5
ICE45
R/W, R
R/W
ICS67
Input capture 6/7
ICE67
R/W, R
R/W
TMCSR2L
TMCSR2H
TMCSR3L
TMCSR3H
SGCRL1
SGCRH1
PCNTL3
PCNTH3
PCNTL4
PCNTH4
PCNTL5
PCNTH5
SMR2
16-bit
reload timer 2
R/W
R/W
16-bit
reload timer 3
R/W
R/W
Sound generator 1
16-bit PPG3
R/W
R/W
R/W
R/W
16-bit PPG4
R/W
R/W
16-bit PPG5
R/W
R/W, W
R/W, W
0000E1H Serial control register 2
SCR2
RDR2/
TDR2
0000E2H Reception/transmission data register 2
0000E3H Serial status register 2
R/W
00000000B
00001000B
000000XXB
SSR2
R/W, R
R/W, R
UART
(LIN/SCI) 2
Extended communication control
0000E4H
register 2
ECCR2
0000E5H Extended status control register 2
0000E6H Baud rate generator register 20
0000E7H Baud rate generator register 21
0000E8H Serial mode register 3
ESCR2
BGR20
BGR21
SMR3
R/W
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
R/W, R
R/W, W
R/W, W
0000E9H Serial control register 3
SCR3
RDR3/
TDR3
0000EAH Reception/transmission data register 3
0000EBH Serial status register 3
R/W
00000000B
00001000B
000000XXB
SSR3
R/W, R
R/W, R
UART
(LIN/SCI) 3
Extended communication control
0000ECH
register 3
ECCR3
0000EDH Extended status control register 3
0000EEH Baud rate generator register 30
0000EFH Baud rate generator register 31
ESCR3
BGR30
BGR31
R/W
R/W
00000100B
00000000B
00000000B
(Continued)
R/W, R
DS07-13754-3E
29
MB90930 Series
Address
Register name
Symbol Read/write Resource name Initial value
001FF0H Program address detection register 0
001FF1H Program address detection register 1
001FF2H Program address detection register 2
001FF3H Program address detection register 3
001FF4H Program address detection register 4
001FF5H Program address detection register 5
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address match
detection
003700H
to
(Disabled)
0037FFH
003800H
to
0038FFH
(Disabled)
(Disabled)
003900H
to
00391FH
003920H
11111111B
11111111B
11111111B
11111111B
00000000B
00000000B
11111100B
PPG0 down counter register
003921H
PDCR0
R
003922H
PPG0 cycle setting register
003923H
PCSR0
W
16-bit PPG0
003924H
PPG0 duty setting register
003925H
PDUT0
W
003926H PPG0 output division setting register
003927H
PPGDIV0
R/W, R
(Disabled)
003928H
11111111B
11111111B
11111111B
11111111B
00000000B
00000000B
11111100B
PPG1 down counter register
003929H
PDCR1
PCSR1
R
00392AH
PPG1 cycle setting register
00392BH
W
16-bit PPG1
00392CH
PPG1 duty setting register
00392DH
PDUT1
W
00392EH PPG1 output division setting register
00392FH
PPGDIV1
R/W, R
(Disabled)
(Continued)
30
DS07-13754-3E
MB90930 Series
Address
003930H
003931H
003932H
003933H
003934H
003935H
Register name
Symbol Read/write Resource name Initial value
11111111B
PPG2 down counter register
PDCR2
PCSR2
R
11111111B
11111111B
11111111B
00000000B
00000000B
11111100B
PPG2 cycle setting register
PPG2 duty setting register
W
16-bit PPG2
PDUT2
W
003936H PPG2 output division setting register
PPGDIV2
R/W, R
003937H
to
(Disabled)
00393FH
003940H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Input capture register 4
003941H
IPCP4
IPCP5
IPCP6
IPCP7
R
R
R
R
Input capture 4/5
Input capture 6/7
003942H
Input capture register 5
003943H
003944H
Input capture register 6
003945H
003946H
Input capture register 7
003947H
003948H
to
(Disabled)
00394FH
003950H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
TMR2/
TMRLR2
16-bit reload timer
2
Timer register 2/Reload register 2
003951H
R/W
R/W
003952H
TMR3/
TMRLR3
16-bit reload timer
3
Timer register 3/Reload register 3
003953H
003954H
to
(Disabled)
003957H
003958H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XX000000B
XX000000B
XXX00000B
00X00001B
003959H Sub second data register
00395AH
WTBR
R/W
Real time
watch timer
00395BH Second data register
00395CH Minute data register
00395DH Hour data register
00395EH Day data register
00395FH
WTSR
WTMR
WTHR
WTDR
R/W
R/W
R/W
R/W
(Disabled)
(Continued)
DS07-13754-3E
31
MB90930 Series
Address
003960H
003961H
003962H
003963H
003964H
003965H
003966H
003967H
003968H
003969H
00396AH
00396BH
00396CH
00396DH
00396EH
00396FH
Register name
Symbol Read/write Resource name Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
LCD
controller/
driver
XXXXXXXXB
LCD display RAM
VRAM
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
003970H
to
(Disabled)
003973H
003974H Frequency data register 1
003975H Amplitude data register 1
003976H Decrement grade register 1
003977H Tone count register 1
SGFR1
SGAR1
SGDR1
SGTR1
R/W
R/W
R/W
R/W
XXXXXXXXB
00000000B
Sound generator 1
XXXXXXXXB
XXXXXXXXB
003978H
to
(Disabled)
00397FH
003980H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
PWM1 compare register 0
003981H
PWC10
PWC20
R/W
R/W
003982H
Stepping motor
controller 0
PWM2 compare register 0
003983H
003984H PWM1 select register 0
003985H PWM2 select register 0
PWS10
PWS20
R/W
R/W
X0000000B
003986H,
003987H
(Disabled)
(Continued)
32
DS07-13754-3E
MB90930 Series
Address
003988H
003989H
00398AH
00398BH
Register name
Symbol Read/write Resource name Initial value
XXXXXXXXB
PWM1 compare register 1
PWC11
PWC21
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
Stepping motor
controller 1
PWM2 compare register 1
00398CH PWM1 select register 1
00398DH PWM2 select register 1
PWS11
PWS21
R/W
R/W
X0000000B
00398EH,
00398FH
(Disabled)
003990H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
PWM1 compare register 2
003991H
PWC12
PWC22
R/W
R/W
003992H
Stepping motor
controller 2
PWM2 compare register 2
003993H
003994H PWM1 select register 2
003995H PWM2 select register 2
PWS12
PWS22
R/W
R/W
X0000000B
003996H,
003997H
(Disabled)
003998H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
PWM1 compare register 3
003999H
PWC13
PWC23
R/W
R/W
00399AH
Stepping motor
controller 3
PWM2 compare register 3
00399BH
00399CH PWM1 select register 3
00399DH PWM2 select register 3
PWS13
PWS23
R/W
R/W
X0000000B
00399EH
to
(Disabled)
0039A5H
0039A6H Flash write control register 0
0039A7H Flash write control register 1
FWR0
FWR1
00000000B
00000000B
R/W
Flash I/F
0039A8H
to
(Disabled)
0039BFH
0039C0H
to
0039DFH
(Disabled)
(Disabled)
0039E0H
to
0039FFH
(Continued)
DS07-13754-3E
33
MB90930 Series
(Continued)
Address
Register name
Symbol Read/write Resource name Initial value
003A00H
to
(Disabled)
003AFFH
003B00H
to
Area reserved for CAN Controller 1(Refer to “■ CAN CONTROLLERS”).
003BFFH
003C00H
to
(Disabled)
003CFFH
003D00H
to
Area reserved for CAN Controller 1(Refer to “■ CAN CONTROLLERS”).
003DFFH
003E00H
to
003EFFH
(Disabled)
(Disabled)
003F00H
to
003FFFH
34
DS07-13754-3E
MB90930 Series
■ CAN CONTROLLERS
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmission/reception message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• 2 acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers(1)
Address
Register
Abbreviation
Access
R/W, R
R/W
Initial Value
CAN1
003D00H
003D01H
003D02H
003D03H
003D04H
003D05H
003D06H
003D07H
00---000B
0----0-1B
Control status register
CSR
--------B
000-0000B
Last event indicator register
RX/TX error counter
Bit timing register
LEIR
00000000B
00000000B
RTEC
R
-1111111B
11111111B
BTR
R/W
DS07-13754-3E
35
MB90930 Series
List of Control Registers(2)
Register
Address
CAN1
Abbreviation
BVALR
TREQR
TCANR
TCR
Access
R/W
R/W
W
Initial Value
000070H
00000000B
00000000B
Message buffer valid register
Transmit request register
Transmit cancel register
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
003D08H
003D09H
003D0AH
003D0BH
003D0CH
003D0DH
003D0EH
003D0FH
003D10H
003D11H
003D12H
003D13H
003D14H
003D15H
003D16H
003D17H
003D18H
003D19H
003D1AH
003D1BH
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Transmit complete register
Receive complete register
Remote request receive register
Receive overrun register
Receive interrupt enable register
IDE register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
RCR
00000000B
00000000B
RRTRR
ROVRR
RIER
00000000B
00000000B
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
IDER
Transmit RTR register
TRTRR
RFWTR
TIER
XXXXXXXXB
XXXXXXXXB
Remote frame receive wait register
Transmit interrupt enable register
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
Acceptance mask select register
Acceptance mask register 0
Acceptance mask register 1
AMSR
AMR0
AMR1
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXX---B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXX---B
XXXXXXXXB
36
DS07-13754-3E
MB90930 Series
List of Message Buffers (ID Registers)
Register Abbreviation
Address
CAN1
Access
Initial Value
003B00H
to
003B1FH
XXXXXXXXB
to
XXXXXXXXB
General-purpose RAM
⎯
R/W
003B20H
003B21H
003B22H
003B23H
003B24H
003B25H
003B26H
003B27H
003B28H
003B29H
003B2AH
003B2BH
003B2CH
003B2DH
003B2EH
003B2FH
003B30H
003B31H
003B32H
003B33H
003B34H
003B35H
003B36H
003B37H
003B38H
003B39H
003B3AH
003B3BH
003B3CH
003B3DH
003B3EH
003B3FH
XXXXXXXXB
XXXXXXXXB
ID register 0
ID register 1
ID register 2
ID register 3
ID register 4
ID register 5
ID register 6
ID register 7
IDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXX---B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR1
IDR2
IDR3
IDR4
IDR5
IDR6
IDR7
XXXXX---B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXX---B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXX---B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXX---B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXX---B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXX---B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXX---B
XXXXXXXXB
(Continued)
DS07-13754-3E
37
MB90930 Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
CAN1
003B40H
XXXXXXXXB
XXXXXXXXB
003B41H
ID register 8
003B42H
IDR8
R/W
XXXXX---B
XXXXXXXXB
003B43H
003B44H
XXXXXXXXB
XXXXXXXXB
003B45H
ID register 9
003B46H
IDR9
IDR10
IDR11
IDR12
IDR13
IDR14
IDR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXX---B
XXXXXXXXB
003B47H
003B48H
XXXXXXXXB
XXXXXXXXB
003B49H
ID register 10
003B4AH
XXXXX---B
XXXXXXXXB
003B4BH
003B4CH
XXXXXXXXB
XXXXXXXXB
003B4DH
ID register 11
003B4EH
XXXXX---B
XXXXXXXXB
003B4FH
003B50H
XXXXXXXXB
XXXXXXXXB
003B51H
ID register 12
003B52H
XXXXX---B
XXXXXXXXB
003B53H
003B54H
XXXXXXXXB
XXXXXXXXB
003B55H
ID register 13
003B56H
XXXXX---B
XXXXXXXXB
003B57H
003B58H
XXXXXXXXB
XXXXXXXXB
003B59H
ID register 14
003B5AH
XXXXX---B
XXXXXXXXB
003B5BH
003B5CH
XXXXXXXXB
XXXXXXXXB
003B5DH
ID register 15
003B5EH
XXXXX---B
XXXXXXXXB
003B5FH
38
DS07-13754-3E
MB90930 Series
List of Message Buffers (DLC Registers)
Address
CAN1
Register
Abbreviation
DLCR0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
----XXXXB
003B60H
003B61H
003B62H
003B63H
003B64H
003B65H
003B66H
003B67H
003B68H
003B69H
003B6AH
003B6BH
003B6CH
003B6DH
003B6EH
003B6FH
003B70H
003B71H
003B72H
003B73H
003B74H
003B75H
003B76H
003B77H
003B78H
003B79H
003B7AH
003B7BH
003B7CH
003B7DH
003B7EH
003B7FH
DLC register 0
DLC register 1
DLC register 2
DLC register 3
DLC register 4
DLC register 5
DLC register 6
DLC register 7
DLC register 8
DLC register 9
DLC register 10
DLC register 11
DLC register 12
DLC register 13
DLC register 14
DLC register 15
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
DS07-13754-3E
39
MB90930 Series
List of Message Buffers (Data register)
Address
CAN1
Register
Abbreviation
Access
Initial Value
003B80H
XXXXXXXXB
to
to
Data register 0 (8 bytes)
DTR0
R/W
003B87H
XXXXXXXXB
003B88H
to
003B8FH
XXXXXXXXB
to
XXXXXXXXB
Data register 1 (8 bytes)
Data register 2 (8 bytes)
Data register 3 (8 bytes)
Data register 4 (8 bytes)
Data register 5 (8 bytes)
Data register 6 (8 bytes)
Data register 7 (8 bytes)
Data register 8 (8 bytes)
Data register 9 (8 bytes)
Data register 10 (8 bytes)
Data register 11 (8 bytes)
Data register 12 (8 bytes)
Data register 13 (8 bytes)
DTR1
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
DTR10
DTR11
DTR12
DTR13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
003B90H
to
003B97H
XXXXXXXXB
to
XXXXXXXXB
003B98H
to
003B9FH
XXXXXXXXB
to
XXXXXXXXB
003BA0H
to
003BA7H
XXXXXXXXB
to
XXXXXXXXB
003BA8H
to
003BAFH
XXXXXXXXB
to
XXXXXXXXB
003BB0H
to
003BB7H
XXXXXXXXB
to
XXXXXXXXB
003BB8H
to
003BBFH
XXXXXXXXB
to
XXXXXXXXB
003BC0H
to
003BC7H
XXXXXXXXB
to
XXXXXXXXB
003BC8H
to
003BCFH
XXXXXXXXB
to
XXXXXXXXB
003BD0H
to
003BD7H
XXXXXXXXB
to
XXXXXXXXB
003BD8H
to
003BDFH
XXXXXXXXB
to
XXXXXXXXB
003BE0H
to
003BE7H
XXXXXXXXB
to
XXXXXXXXB
003BE8H
to
XXXXXXXXB
to
003BEFH
XXXXXXXXB
(Continued)
40
DS07-13754-3E
MB90930 Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
CAN1
003BF0H
to
XXXXXXXXB
to
Data register 14 (8 bytes)
DTR14
R/W
003BF7H
XXXXXXXXB
003BF8H
to
XXXXXXXXB
to
Data register 15 (8 bytes)
DTR15
R/W
003BFFH
XXXXXXXXB
DS07-13754-3E
41
MB90930 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt control
Interrupt vector
EI2OS
Priority
register
Interrupt source
2
corresponding
*
Number
#08
Address
ICR
⎯
Address
Reset
×
×
×
×
×
×
×
08H FFFFDCH
09H FFFFD8H
0AH FFFFD4H
0BH FFFFD0H
0CH FFFFCCH
0DH FFFFC8H
0EH FFFFC4H
0FH FFFFC0H
⎯
⎯
⎯
High
INT9 instruction
Exception processing
⎯
#09
#10
#11
#12
#13
#14
#15
⎯
⎯
ICR00
0000B0H
⎯
CAN1 received
CAN1 transmitted/node status/
Input capture 0
ICR01 0000B1H*1
ICR02 0000B2H*1
ICR03 0000B3H*1
ICR04 0000B4H*1
ICR05 0000B5H*1
ICR06 0000B6H*1
DTP/ external interrupt
- ch.0/ch.1 detected
#16
10H FFFFBCH
Reload timer 0
Reload timer 2
Input capture 1
#17
#18
#19
11H FFFFB8H
12H FFFFB4H
13H FFFFB0H
DTP/ external interrupt
- ch.2/ch.3 detected
#20
14H FFFFACH
Input capture 2
#21
#22
#23
15H FFFFA8H
16H FFFFA4H
17H FFFFA0H
Reload timer 3
Input capture 3/4/5/6/7
DTP/ external interrupt
- ch.4/ ch.5 detected UART3 RX
#24
#25
#26
18H FFFF9CH
PPG timer 0
19H
FFFF98H
ICR07 0000B7H*1
ICR08 0000B8H*1
ICR09 0000B9H*1
DTP/ external interrupt
- ch.6/ ch.7 detected UART3 TX
1AH FFFF94H
PPG timer 1
#27
#28
#29
1BH FFFF90H
1CH FFFF8CH
1DH FFFF88H
Reload timer 1
PPG timer 2/3/4/5
Real time watch timer /
Watch timer (Sub clock)
×
×
#30
1EH FFFF84H
Free-run timer overflow/clear
A/D converter conversion complete
Sound generator 0/1
Time-base timer
#31
#32
#33
#34
#35
#36
1FH FFFF80H
20H FFFF7CH
ICR10 0000BAH *1
ICR11 0000BBH*1
ICR12 0000BCH*1
×
×
21H
22H
23H
FFFF78H
FFFF74H
FFFF70H
UART2 RX
UART2 TX
24H FFFF6CH
Low
(Continued)
42
DS07-13754-3E
MB90930 Series
(Continued)
Interrupt source
Interrupt control
EI2OS
corresponding
Interrupt vector
Number Address
Priority
register
2
*
ICR
Address
UART 1 RX
#37
#38
#39
#40
#41
#42
25H
26H
27H
28H
29H
2AH
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
High
ICR13 0000BDH*1
UART 1 TX
UART 0 RX
ICR14
ICR15
0000BEH*1
0000BFH*1
UART 0 TX
Flash memory status
Delay interrupt generator module
×
×
Low
: Usable, and has extended intelligent I/O services (EI2OS) stop function
: Usable
: Usable when interrupt sources sharing ICR are not in use
× : Unusable
*1 : • Peripheral functions that share the ICR register have the same interrupt level.
• If the extended intelligent I/O service (EI2OS) is used with peripheral functions that share the ICR register,
only one of the peripheral functions that share the register can be used.
• When the extended intelligent I/O service (EI2OS) is specified for one of the peripheral functions that shares
the ICR register, interrupts cannot be used from the other peripheral functions that share the register.
*2 : Priority applies when interrupts of the same level are generated.
DS07-13754-3E
43
MB90930 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
AVRH
DVCC
VI
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VCC + 0.3
VSS − 0.3 VCC + 0.3
V
V
V
V
V
V
AVCC = VCC*2
Power supply voltage*1
AVCC ≥ AVRH*2
DVCC = VCC*2
*3
Input voltage*1
Output voltage*1
VO
Maximum clamp current
ICLAMP
− 4
⎯
+ 4
40
mA *7
Total maximum clamp current Σ| ICLAMP |
mA *7
IOL1
IOL2
⎯
15
mA Except P70 to P77 and P80 to P87
mA P70 to P77 and P80 to P87
mA Except P70 to P77 and P80 to P87
mA P70 to P77 and P80 to P87
mA Except P70 to P77 and P80 to P87
mA P70 to P77 and P80 to P87
mA Except P70 to P77 and P80 to P87
mA P70 to P77 and P80 to P87
mA Except P70 to P77 and P80 to P87
mA P70 to P77 and P80 to P87
mA Except P70 to P77 and P80 to P87
mA P70 to P77 and P80 to P87
mA Except P70 to P77 and P80 to P87
mA P70 to P77 and P80 to P87
mA Except P70 to P77 and P80 to P87
mA P70 to P77 and P80 to P87
mW
“L” level maximum
output current*4
⎯
40
IOLAV1
IOLAV2
ΣIOL1
⎯
4
“L” level average output
current*5
⎯
30
⎯
100
330
50
“L” level maximum
total output current
ΣIOL2
⎯
ΣIOLAV1
ΣIOLAV2
IOH1*4
IOH2*4
IOHAV1*5
IOHAV2*5
ΣIOH1
ΣIOH2
ΣIOHAV1*6
ΣIOHAV2*6
PD
⎯
“L” level average total
output current
⎯
250
−15
−40
−4
⎯
“H” level maximum
output current
⎯
⎯
“H” level average
output current
⎯
−30
−100
−330
−50
−250
490
+ 105
+ 150
⎯
“H” level maximum
total output current
⎯
⎯
“H” level average total
output current
⎯
Power consumption
Operating temperature
Storage temperature
⎯
TA
− 40
− 55
°C
TSTG
°C
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : AVCC, AVRH must not exceed VCC, and AVRH must not exceed AVCC.
When using an evaluation product, DVCC must not exceed VCC (however, DVCC can be set to a higher voltage
than VCC when using a Flash memory product/Mask ROM product).
*3 : If the input current or the maximum input current is limited using external components, ICLAMP is the applicable
rating instead of VI.
*4 : Maximum output current is defined as the peak value of current through any one of the corresponding pins.
(Continued)
44
DS07-13754-3E
MB90930 Series
(Continued)
*5 : Average output current is defined as the average value of the current flowing through any one of the
corresponding pins within a period of 100 ms. The “average value” can be calculated by multiplying the
“operating current” by the “operating factor”.
*6 : Average total output current is defined as the average value of the current flowing through all of the
corresponding pins within a period of 100 ms. The “average value” can be calculated by multiplying the
“operating current” by the “ operating factor”.
*7 : • Applicable to pins: P00 to P07, P10 to P15, P22 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77,
P80 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the
microcontroller may partially malfunction on power supplied through the +B signal pin.
• Note that if the +B input is applied during power-on, the power supply voltage may reach a level such that
the power-on reset does not function due to the power supplied from the +B signal.
• Care must be taken not to leave +B input pins open.
• Note that analog system input/output pins (LCD common pins, comparator input pins, etc.) cannot accept
+B signal inputs.
• Sample recommended circuit :
• Input/output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistance
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-13754-3E
45
MB90930 Series
2. Recommended Operating Conditions
Value
(VSS = DVSS = AVSS = 0.0 V)
Parameter
Symbol
Unit
Remarks
Min
Max
The low voltage detection reset operates when the power
supply voltage reaches 4.0 V 0.3 V.
3.7
5.5
V
VCC,
AVCC,
DVCC
Power supply
voltage
Maintain stop operation status
The low voltage detection reset operates when the power
supply voltage reaches 4.0 V 0.3 V.
3.7
5.5
V
Use a ceramic capacitor or other capacitor of equivalent
frequency characteristics. Use a capacitor with a capaci-
tance greater than this capacitor as the bypass capacitor
for the VCC pin.
Smoothing
capacitor*
CS
TA
0.1
1.0
μF
°C
Operating
temperature
− 40
+ 105
* : Refer to the following diagram for details on the connection of the smoothing capacitor CS.
• C pin connection diagram
C
AVSS
VSS
DVSS
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
46
DS07-13754-3E
MB90930 Series
3. DC Characteristics
(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Value
Typ
Sym-
bol
Pin
name
Parameter
Conditions
Unit
Remarks
Pin inputs if
Min
Max
VIHA
⎯
⎯
0.8 VCC
⎯
⎯
V
Automotive input
levels are selected
Pin inputs if CMOS
hysteresis input
levels are selected
RST input pin
“H” level
input voltage
VIHS
VIHC
VILA
⎯
⎯
⎯
⎯
⎯
⎯
0.8 VCC
0.7 VCC
⎯
⎯
⎯
⎯
⎯
⎯
V
V
V
(CMOS hysteresis)
Pin inputs if
0.5 VCC
Automotive input
levels are selected
Pin inputs if CMOS
hysteresis input
levels are selected
RST input pin
“L” level
input voltage
VILS
VILR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
30
0.2 VCC
0.3 VCC
40
V
V
(CMOS hysteresis)
Maximum operating
frequency FCP = 32 MHz,
normal operation
Maximum operating
frequency FCP = 32 MHz,
writing Flash memory
Operating frequency
FCP = 32 MHz,
mA
ICC
⎯
⎯
⎯
40
12
55
20
mA
mA
mA
ICCS
sleep mode
Operating frequency
FCP = 2 MHz,
ICTS
0.6
1.0
time-base timer mode
Operating frequency
FCP = 32 MHz,
ICTSPLL
⎯
⎯
⎯
2.5
170
⎯
4
mA
μA
μA
Powersupply
current*
PLL timer mode,
External frequency = 4 MHz
Operating frequency
FCP = 8 kHz,
VCC
ICCL
340
270
TA = + 25 °C,
Sub clock operation
Operating frequency
FCP = 8 kHz,
ICCLS
TA = + 25 °C,
Sub sleep operation
Operating frequency
FCP = 8 kHz,
ICCT
⎯
⎯
⎯
⎯
250
170
μA
μA
TA = + 25 °C,
Watch mode
TA = + 25 °C,
Stop mode
ICCH
(Continued)
DS07-13754-3E
47
MB90930 Series
(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit Remarks
Min
Typ Max
VCC = DVCC = AVCC =
5.5 V,
VSS < VI < VCC
Input leakage
current
IIL
All input pins
⎯
⎯
⎯
10
15
μA
All pins except
VCC, VSS,
DVCC,DVSS,
AVCC, AVSS,
C,
Input
capacitance 1
CIN1
⎯
⎯
pF
pF
P70 to P77,
P80 to P87
P70 to P77,
P80 to P87
Input capacitance 2
Pull-up resistance
CIN2
RUP
⎯
⎯
⎯
⎯
⎯
⎯
45
RST
100
kΩ
Excluding
Pull-down
resistance
Flash
memory
RDOWN MD2
⎯
⎯
⎯
100
kΩ
product
All pins except
P70 to P77,
P80 to P87
General-purpose
output “H” voltage
VCC = 4.5 V,
VOH1
VOH2
VOL1
VOL2
VCC − 0.5
VCC − 0.5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
V
IOH = −4.0 mA
Stepping motor
output “H” voltage
P70 to P77,
P80 to P87
VCC = 4.5 V,
IOH = −30.0 mA
V
V
V
All pins except
P70 to P77,
P80 to P87
General-purpose
output “L” voltage
VCC = 4.5 V,
IOL = 4.0 mA
0.4
0.55
Stepping motor
output “L” voltage
P70 to P77,
P80 to P87
VCC = 4.5 V,
IOL = 30.0 mA
⎯
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
n = 0 to 3
VCC = 4.5 V,
IOH = −30.0 mA,
maximum deviation
VOH2
Stepping motor
output phase
variation “H”
ΔVOH
⎯
⎯
⎯
90
mV
mV
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
n = 0 to 3
VCC = 4.5 V,
IOL = 30.0 mA,
maximum deviation
VOL2
Stepping motor
output phase
variation “L”
ΔVOL
⎯
90
25
Between V0
and V1,
Between V1
and V2,
Between V2
and V3
6.25
8.75
12.5
kΩ Evaluation
LCD internal
divider resistance
RLCD
⎯
Flash/Mask
ROM
12.5 17.0 kΩ
(Continued)
48
DS07-13754-3E
MB90930 Series
(Continued)
(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Typ Max
V0 to V3,
COMm
(m = 0 to 3) ,
SEGn,
LCDC leakage
current
ILCDC
⎯
⎯
⎯
5.0
μA
(n = 00 to 31)
COMn
(n = 0 to 3)
kΩ
kΩ
Rvcom
Rvseg
⎯
⎯
⎯
⎯
⎯
⎯
4.5
17
LCD output
impedance
SEGn
(n = 00 to 31)
* : Power supply current values are assumed by an external clock supplied from the X1 pin. Users must be aware
that power supply current levels differ depending on whether an external clock or oscillator is used.
DS07-13754-3E
49
MB90930 Series
4. AC Characteristics
(1) Clock timing
(VCC = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Condi-
Parameter
Clock frequency
Clock cycle time
Symbol Pinname
Unit
Remarks
tions
Min
Typ
Max
1/2 (PLL stopped)
3
⎯
16
MHz When using the
oscillator circuit
4
3
⎯
⎯
⎯
⎯
⎯
32
16
MHz PLL multiplied by 1
MHz PLL multiplied by 2
FC
X0, X1
3
10.7 MHz PLL multiplied by 3
MHz PLL multiplied by 4
5.33 MHz PLL multiplied by 6
3
8
3
3
4
MHz PLL multiplied by 8
⎯
FLC
tCYL
tLCYL
X0A, X1A
X0, X1
⎯
62.5
32.768
⎯
⎯
kHz
ns
333
X0A, X1A
30.5
μs
Using main clock
MHz
FCP
FLCP
tCP
⎯
⎯
⎯
⎯
1.5
⎯
⎯
32
⎯
Internal operating
clock frequency
(PLL clock)
8.192
—
kHz Using sub clock
Using main clock
(PLL clock)
31.25
⎯
666
⎯
ns
Internal operating
clock cycle time
tLCP
122.1
μs Using sub clock
• X0, X1 clock timing
tCYL
0.8 VCC
X0
X1
0.2 VCC
PWH
PWL
tcf
tcr
• X0A, X1A clock timing
tCYL
0.8 VCC
0.2 VCC
X0A
X1A
PWH
PWL
tcf
tcr
50
DS07-13754-3E
MB90930 Series
• Guaranteed PLL Operation Range
Internal operating clock frequency vs. Power supply voltage
5.5
3.7
Range of warranted PLL operation
Normal operating range
4
32
1.5
Internal clock fCP (MHz)
Notes: • For PLL 1 × only, use with tcp = 4 MHz or greater.
• Refer to “5. A/D Converter (1) Electrical Characteristics” for details on the A/D converter operating
frequency.
(Continued)
DS07-13754-3E
51
MB90930 Series
(Continued)
Base oscillator frequency vs. Internal operating clock frequency
32
x 8*3
x 6*3
x 3*1
25
24
No multiplier
20
18
x 2*1,*2
x 1*1
16
x 4
*1,*2
12
9
8
6
4
1.5
345 6 8 10 12.5 16
20
25
32
Base oscillator clock FCP (MHz)
*1 : When the PLL multiplier is × 1, × 2, × 3 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, set
DIV2 bit = “1”*4, CS2 bit = “1” in the PSCCR register.
[Example]When using a base oscillator frequency of 24 MHz at PLL × 1 :
CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PSCCR register : DIV2 bit = “1”*4 ,CS2 bit = “1”
[Example]When using a base oscillator frequency of 6 MHz at PLL × 3 :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”
PSCCR register : DIV2 bit = “1”*4 , CS2 bit = “1”
*2 : When the PLL multiplier is × 2 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, the following
settings are also supported.
PLL × 2 : CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “0”
PLL × 4 : CKSCR register : CS1 bit = “0”, CS0 bit = “1”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “0”
*3 : When the PLL multiplier is set to × 6 or × 8, set “DIV2 bit = “0”*4 CS2 bit = “1”
and “PLL2 bit = 1” in the PSCCR register.
[Example]When using a base oscillator frequency of 4 MHz at PLL × 6 :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “1”
[Example]When using a base oscillator frequency of 3 MHz at PLL × 8 :
CKSCR register : CS1 bit = “1”, CS0 bit = “1”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “1”
Note: The DIV2 bit is assigned to bit 9 of the PSCCR register and the CS2 bit is assigned to bit 8 of the PSCCR
register. Both bits have a default value of “0”.
52
DS07-13754-3E
MB90930 Series
(2) Reset input
Parameter
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Value
Symbol Pin name
Unit
Remarks
Min
Max
⎯
During normal
operation
10
μs
Reset input time
Oscillator oscillation time* + 100 μs
⎯
ms In stop mode
tRSTL
RST
In time-base timer
mode
100
⎯
μs
μs
Width of Reset
input removal
1
⎯
⎯
*: The oscillation time of the oscillator is the time taken to reach 90% of the amplitude. The oscillation time of a
crystal oscillator is between several ms and tens of ms. The oscillation time of a ceramic oscillator is between
hundreds of μs and several ms. The oscillation time of an external clock is 0 ms.
Note: tCP is the internal operating clock cycle time. (Unit : ns)
• During normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode and power-on
t
RSTL
RST
0.2 Vcc
0.2 Vcc
90 % of
amplitude
X0
Internal
operating
clock
Oscillator
oscillation time
100 μs
Oscillation stabilization wait time
Execution of the instructions
Internal
reset
DS07-13754-3E
53
MB90930 Series
(3) Power-on reset
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to +105 °C)
Value
Sym-
bol
Pin
name
Parameter
Conditions
Unit
Remarks
Min
Max
Power supply rise time
Power supply cutoff time
tR
0.05
30
ms
ms
VCC
⎯
Waiting time until
power-on
tOFF
1
⎯
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Note: Extreme variations in power supply voltage may trigger a power-on reset. When the power
supply voltage is changed during operation, it is recommended that increases in voltage are
smoothed out as shown in the following diagram. The PLL clock of the device should not be
in use when varying the voltage. However, the PLL clock may continue to be used if the rate
of the voltage drop is 1 V/s or less.
V
CC
5.0 V
0 V
It is recommended that rises
in voltage have a slope of
50 mV/ms or less
RAM data hold
V
SS
54
DS07-13754-3E
MB90930 Series
(4) UART0/1/2/3 (LIN/SCI)
• Bit setting: ESCR0/1/2/3:SCES=0, ECCR0/1/2/3:SCDE=0
(VCC = 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCK0 to SCK3
5 tCP
⎯
ns
ns
SCK0 to SCK3,
SOT0 to SOT3
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
SCK ↓ → SOT delay time
− 50
+ 50
Valid SIN → SCK ↑
tIVSHI
tSHIXI
tSLSH
tSHSL
tCP + 80
0
⎯
⎯
⎯
⎯
ns
ns
ns
ns
SCK0 to SCK3,
SIN0 to SIN3
SCK ↑ → valid SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
3 tCP − tR
tCP + 10
SCK0 to SCK3
SCK0 to SCK3,
SOT0 to SOT3
SCK ↓ → SOT delay time
tSLOVE
⎯
2 tCP + 60
ns
External shift clock
mode output pin
CL = 80 pF + 1TTL
Valid SIN → SCK ↑
SCK ↑ → valid SIN hold time
SCK ↓ time
tIVSHE
tSHIXE
tF
30
tCP + 30
⎯
⎯
⎯
10
10
ns
ns
ns
ns
SCK0 to SCK3,
SIN0 to SIN3
SCK0 to SCK3
SCK ↑ time
tR
⎯
Notes: • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90930 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
DS07-13754-3E
55
MB90930 Series
• Internal shift clock mode
SCK
tSCYC
2.4 V
0.8 V
0.8 V
tSLOVI
2.4 V
0.8 V
SOT
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
SIN
• External shift clock mode
SCK
tSLSH
tSHSL
VIH
VIH
VIL
VIL
t
R
t
SLOVE
t
F
2.4 V
0.8 V
SOT
SIN
tIVSHE
tSHIXE
V
IH
IL
V
IH
IL
V
V
56
DS07-13754-3E
MB90930 Series
• Bit setting: ESCR0/1/2/3:SCES=1, ECCR0/1/2/3:SCDE=0
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK3
5 tCP
⎯
ns
ns
SCK0 to SCK3,
SOT0 to SOT3
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
SCK ↑ → SOT delay time
tSHOVI
− 50
+ 50
Valid SIN → SCK ↓
tIVSLI
tSLIXI
tSHSL
tSLSH
tCP + 80
0
⎯
⎯
⎯
⎯
ns
ns
ns
ns
SCK0 to SCK3,
SIN0 to SIN3
SCK ↓ → valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
3 tCP − tR
tCP + 10
SCK0 to SCK3
SCK0 to SCK3,
SOT0 to SOT3
SCK ↑ → SOT delay time
tSHOVE
⎯
2 tCP + 60
ns
External shift clock
mode output pin
CL = 80 pF + 1TTL
Valid SIN → SCK ↓
SCK ↓ → valid SIN hold time
SCK ↓ time
tIVSLE
tSLIXE
tF
30
tCP + 30
⎯
⎯
⎯
10
10
ns
ns
ns
ns
SCK0 to SCK3,
SIN0 to SIN3
SCK0 to SCK3
SCK ↑ time
tR
⎯
Notes: • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90930 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
DS07-13754-3E
57
MB90930 Series
• Internal shift clock mode
SCK
tSCYC
2.4 V
2.4 V
0.8 V
tSHOVI
2.4 V
0.8 V
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
• External shift clock mode
SCK
t
SHSL
tSLSH
V
IH
VIH
V
IL
V
IL
t
F
t
R
t
SHOVE
2.4 V
0.8 V
SOT
SIN
t
SLIXE
t
IVSLE
VIH
VIH
V
IL
V
IL
58
DS07-13754-3E
MB90930 Series
• Bit setting: ESCR0/1/2/3:SCES=0, ECCR0/1/2/3:SCDE=1
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK3
5 tCP
⎯
ns
ns
SCK0 to SCK3,
SOT0 to SOT3
SCK ↑ → SOT delay time
tSHOVI
− 50
+ 50
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
Valid SIN → SCK ↓
tIVSLI
tSLIXI
tCP + 80
⎯
⎯
ns
ns
SCK0 to SCK3,
SIN0 to SIN3
SCK ↓ → valid SIN hold time
0
SCK0 to SCK3,
SOT0 to SOT3
SOT → SCK ↓ delay time
tSOVLI
3 tCP − 70
⎯
ns
Notes: • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90930 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
t
SCYC
SCK
SOT
2.4 V
0.8 V
0.8 V
tSHOVI
t
SOVLI
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
t
SLIXI
V
V
IH
IL
V
IH
SIN
V
IL
DS07-13754-3E
59
MB90930 Series
• Bit setting: ESCR0/1/2/3:SCES=1, ECCR0/1/2/3:SCDE=1
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCK0 to SCK3
5 tCP
⎯
ns
ns
SCK0 to SCK3,
SOT0 to SOT3
SCK ↓ → SOT delay time
− 50
+ 50
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
Valid SIN → SCK ↓
tIVSHI
tSHIXI
tCP + 80
⎯
⎯
ns
ns
SCK0 to SCK3,
SIN0 to SIN3
SCK ↑ → valid SIN hold time
0
SCK0 to SCK3,
SOT0 to SOT3
SOT → SCK ↑ delay time
tSOVHI
3 tCP − 70
⎯
ns
Notes: • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90930 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
tSCYC
SCK
2.4 V
2.4 V
0.8 V
tSLOVI
tSOVHI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
60
DS07-13754-3E
MB90930 Series
(5) Timer input timing
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
tTIWH
tTIWL
TIN0, TIN1,
IN0 to IN3
Input pulse width
⎯
4 tCP
⎯
ns
Note: tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
• Timer input timing
tTIWH
tTIWL
VIH
VIH
TIN0, TIN1
IN0 to IN3
VIL
VIL
DS07-13754-3E
61
MB90930 Series
(6) Trigger input timing
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Parameter
Symbol Pin name Conditions
Unit
Remarks
Min
200
Max
⎯
During normal
operation
INT0 to INT7
ADTG
⎯
⎯
ns
ns
tTRGH,
tTRGL
Input pulse width
tCP + 200
⎯
Note: tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
• Trigger input timing
tTRGH
tTRGL
VIH
VIH
INT0 to INT7
ADTG
VIL
V
IL
62
DS07-13754-3E
MB90930 Series
(7) Low voltage detection
(VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Typ
Sym-
bol
Condi-
tions
Parameter
Pin name
Unit
Remarks
Min
Max
Flash memory
product/Mask ROM
product, during
voltage drop
Detection voltage
VDL
VCC
⎯
⎯
3.7
4.0
⎯
4.3
V
Flash memory
product/Mask ROM
product, during
voltage rise
Hysteresis width
VHYS
dV/dt
td
VCC
VCC
⎯
169
⎯
mV
Flash memory
product/Mask ROM
product, dV/dt at low
voltage reset
− 0.1
⎯
+ 0.1 V/μs
Flash memory
product/Mask ROM
product, dV/dt at
Powersupplyvoltage
change rate
⎯
−0.004
⎯
⎯
+ 0.004 V/μs standard value of
low voltage
detection/release
voltage
Flash memory
product/Mask ROM
product, when
Detection delay time
⎯
⎯
3.2
μs
dV/dt ≤ 0.004 V/μs
Internal reset
VCC
dV
dt
VHYS
t
d
td
DS07-13754-3E
63
MB90930 Series
5. A/D Converter
(1) Electrical Characteristics
(VCC = AVCC = AVRH = 4.0 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Value
Typ
⎯
Parameter
Resolution
Symbol Pin name
Unit
Remarks
Min
⎯
Max
10
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
− 3.0
− 2.5
− 1.9
⎯
+ 3.0
+ 2.5
+ 1.9
LSB
LSB
LSB
Non-linear error
Differential linear error
⎯
⎯
AN0 to
AN23
AVSS −
AVSS +
AVSS +
Zero transition voltage
VOT
V
V
1 LSB =
1.5 LSB
0.5 LSB
2.5 LSB
(AVRH − AVSS) /
Full scale transition
voltage
AN0 to
AN23
AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
1024
VFST
0.4
1.0
4.5 V ≤ AVcc ≤ 5.5 V
4.0 V ≤ AVcc ≤ 4.5 V
4.5 V ≤ AVcc ≤ 5.5 V
4.0 V ≤ AVcc ≤ 4.5 V
Sampling time
tSMP
⎯
⎯
⎯
16500
μs
μs
0.66
2.2
Compare time
tCMP
tCNV
IAIN
⎯
⎯
⎯
A/D conversion time
1.44
⎯
⎯
⎯
μs *1
Analog port
input current
AN0 to
AN23
− 1.0
+ 1.0
μA
AN0 to
AN23
Analog input voltage
Reference voltage
VAIN
0
⎯
⎯
AVRH
AVCC
V
V
AVss +
2.7
AV+
AVRH
AVCC
IA
IAH
IR
⎯
⎯
⎯
⎯
2.3
⎯
⎯
⎯
6.0
5
mA
Power supply current
μA *2
900
5
μA VAVRH = 5.0 V
μA *2
Reference voltage
supply current
AVRH
IRH
AN0 to
AN23
Inter-channel variation
—
⎯
⎯
4
LSB
*1 : The time per channel (4.5 V ≤ AVCC ≤ 5.5 V, and internal operating frequency = 32 MHz) .
*2 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in
stop mode.
64
DS07-13754-3E
MB90930 Series
• Notes on the external impedance and sampling time of analog inputs
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
If the sampling time is still not sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
MB90F931/MB90F931S/MB90931/MB90931S
R
C
4.5 V ≤ AVcc ≤ 5.5 V : 2.6 kΩ (Max) 8.5 pF (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 12.1 kΩ (Max) 8.5 pF (Max)
MB90V930-102/MB90V930-101
R
C
4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max) 14.4 pF (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max) 14.4 pF (Max)
Note : The values are reference values.
DS07-13754-3E
65
MB90930 Series
• The relationship between the external impedance and minimum sampling time
• At 4.5 V ≤ AVcc ≤ 5.5 V
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
MB90V930-102/MB90V930-101
100
MB90V930-102/MB90V930-101
20
MB90F931/MB90F931S/
MB90F931/MB90F931S/
90
18
MB90931/MB90931S
80
MB90931/MB90931S
16
70
60
50
40
30
20
10
0
14
12
10
8
6
4
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
Minimum sampling time [μs]
• At 4.0 V ≤ AVcc ≤ 4.5 V
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
MB90V930-102/MB90V930-101
MB90V930-102/MB90V930-101
100
20
MB90F931/MB90F931S/
18
MB90F931/MB90F931S/
90
80
70
60
50
40
30
20
10
0
MB90931/MB90931S
16
MB90931/MB90931S
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
35
Minimum sampling time [μs]
Minimum sampling time [μs]
•About errors
As |AVRH - AVSS| becomes smaller, the relative errors grow larger.
66
DS07-13754-3E
MB90930 Series
(2) Definition of terms
Resolution : Analog changes that are identifiable by the A/D converter.
Non-Linear error : The deviation of the straight line connecting the transition point
(“00 0000 0000” ←→ “00 0000 0001”) with the full-scale transition point
(“11 1111 1110” ←→ “11 1111 1111”) from actual conversion characteristics.
Differential linear : The deviation from the ideal value of the input voltage needed to change the output code by
error
1 LSB.
: The total error is the difference between the actual value and the theoretical value,
and includes transition error/full-scale transition error and linear error.
Total error
Total error
3FFH
3FEH
3FDH
Actual conversion
value
1.5 LSB
{1 LSB x (N - 1) + 0.5 LSB}
004H
003H
002H
VNT
(Measured value)
Actual conver-
sion value
Ideal
001H
characteristics
0.5 LSB
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
Total error for digital output N =
[LSB]
1 LSB
AVRH − AVSS
1 LSB (Ideal) =
[V]
1024
N : A/D converter digital output value
VOT (Ideal) = AVss + 0.5 LSB [V]
VFST (Ideal) = AVRH − 1.5 LSB [V]
VNT : Voltage when the digital output changes from (N - 1) to N
(Continued)
DS07-13754-3E
67
MB90930 Series
(Continued)
Non-Linear error
Differential linear error
Ideal
characteristics
Actual conversion
value
{1 LSB x (N -1)
+ VOT}
3FFH
3FEH
3FDH
Actualconversion
value
(N + 1)
VFST
(Measured
value)
N
V(N + 1)T
(Measured
value)
VNT
(N - 1)
004H
003H
002H
(Measured value)
VNT
Actual conver-
sion value
(Measured value)
Actual conver-
sion value
(N - 2)
Ideal
characteristics
001H
VOT (Measured value)
Analog input
AVss
AVRH
AVss
AVRH
Analog input
Non-linear error of
digital output N
VNT − {1 LSB × (N − 1) + VOT}
=
[LSB]
1 LSB
Differential linear error
of digital output N
V (N + 1) T − VNT
− 1 [LSB]
1 LSB
=
VFST − VOT
1 LSB =
[V]
1022
N
: A/D converter digital output value
VOT : Voltage when digital output changes from 000H to 001H
VFST : Voltage when digital output changes from 3FEH to 3FFH
68
DS07-13754-3E
MB90930 Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Conditions
Unit
Remarks
Min
Typ
Max
Excludes pre-programming
before erase
Sector erase time
⎯
0.9
3.6
s
TA = + 25 °C,
VCC = 5.0 V
Word (16-bit width)
programming time
⎯
23
370
μs
Excludes system-level overhead
Chip programming
time
TA = + 25 °C,
VCC = 5.0 V
⎯
10000
20
3.4
⎯
55
⎯
⎯
s
Erase/program cycle
⎯
cycle
year
Flash memory data
retention time
Average
TA = + 85 °C
⎯
*
* : This value is calculated from the results of evaluating the reliability of the technology (using Arrhenius equation
to translate high temperature measurements into normalized value at + 85 °C) .
DS07-13754-3E
69
MB90930 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90F931PMC
MB90F931SPMC
MB90931PMC
MB90931SPMC
120-pin plastic LQFP
(FPT-120P-M21)
MB90V930-102
MB90V930-101
299-pin ceramic PGA
(PGA-299C-A01)
Evaluation
70
DS07-13754-3E
MB90930 Series
■ PACKAGE DIMENSION
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
16.0 × 16.0 mm
Gullwing
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.88 g
Code
(Reference)
(FPT-120P-M21)
P-LFQFP120-16×16-0.50
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 0.20(.709 .008)SQ
+0.40
16.00 –0.10 .630 –+..000146 SQ
*
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
0~8
°
"A"
120
31
0.10 0.05
(.004 .002)
(Stand off)
1
30
LEAD No.
0.145 +–00..0035
0.60 0.15
(.024 .006)
0.22 0.05
(.009 .002)
M
0.50(.020)
0.08(.003)
.006 +–..000012
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F120033S-c-4-7
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13754-3E
71
MB90930 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
■ I/O CIRCUIT TYPE
■ HANDLING DEVICES
Change Results
Corrected the circuit type A and B.
13
Added the following items.
• Serial communication
• Characteristic difference between flash device and mask
ROM device
21
■ ELECTRICAL CHARACTERISTICS Added the item for “LCD output impedance”.
3. DC Characteristic
49
The vertical lines marked in the left side of the page show the changes.
72
DS07-13754-3E
MB90930 Series
MEMO
DS07-13754-3E
73
MB90930 Series
MEMO
74
DS07-13754-3E
MB90930 Series
MEMO
DS07-13754-3E
75
MB90930 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
相关型号：
©2020 ICPDF网 联系我们和版权申明