MC33099DW_技术文档

Document Number: MC33099

Rev. 6.0, 1/2007

Freescale Semiconductor

Technical Data

Adaptive Alternator Voltage

Regulator

33099

The 33099 is designed to regulate the output voltage in diode-

rectified alternator charging systems common to automotive

applications. The 33099 provides either an analog or digital fixed

frequency duty cycle (ON/OFF ratio) control of an alternator’s field

current. Load Response Control (LRC) of the alternator field current

is accomplished by selecting the duty cycle for prevailing engine

conditions to eliminate engine speed hunting and vibrations caused

by abrupt torque loading of the engine owing to sudden electrical

loads being applied to the system at low engine RPM. Four LRC rates

are selectable by connecting pins 7 and 8 to ground.

VOLTAGE REGULATOR

The 33099 uses a feedback voltage to establish an alternator field

current that is in harmony with system load currents. The output

voltage is monitored by an internal voltage divider scheme and

compared to an internal voltage ramp referenced to a bandgap

voltage. This approach provides precision output voltage control over

a wide range of temperature, electrical loads, and engine RPM.

DW SUFFIX

EG SUFFIX (PB-FREE)

98ASB42567B

16-PIN SOICW

ORDERING INFORMATION

Temperature

Features

• External High-Side MOSFET Control of a Ground-Referenced

Field Winding

Device

Package

Range (T )

A

• LRC Active During Initial Start

MC33099DW/R2

MC33099CDW/R2

MCZ33099EG/R2

MCZ33099CEG/R2

• V at ±0.1 V @ 25°C

16 SOICW

set

• <0.1 V Variation Over Engine Speeds of 2,000 to 10,000 RPM

• <0.2 V Variation Over 10% to 95% of Maximum Field Current

• Controlled MOSFET and Field Flyback Diode Recovery

Characteristics for Minimum RFI

-40°C to 125°C

16 SOICW

(Pb-FREE)

• Trimmed Devices Available at 14.6 V and 14.8 V (typical) V

set

• Pb-Free Packaging Designated by Suffix Code EG

33099

PHASE

FIELD

GATE

WINDING

SOURCE

PHASE FILTER

IGN

IGNITION

SWITCH

LAMP DRAIN

BAT

REMOTE

LRC1

LRC2

AGND

GND

CHASSIS

Figure 1. 33099 Simplified Application Diagram

Vbat

BATT

REMOTE

V

rem

MC33099

Charge

Pump

CB1

V

rs

Regulator

V

Internal

DD

V

reg

Regulator

and Bias

Current

FB

0.6 V

LB

RF

V

Bandgap

g

V

o

fb

C

V

Reference

rs

l

Low

Pass

V

l

DD

Local

pu

Cf

V

(OTC)

1.25 V

ref

(2.0 V)

(5.0 V)

A

N

D

4

V

S3

ls

GATE

Field

Sense

S1

UV

R4

R5

C

R1

uv

CB2

Min Duty

Cycle

1.25 V

R2

R3

Gate

Polling

Batt

Z1

LD

l

pd

PHASE

V

Tssc

Over

OR1

Css

S2

Voltage

SOURCE

Detect

V

OV

hvl

Ign

Delay

C

ph

C

IGN

dc

PHASE

FILTER

F1

F2

V

DAC

dac

A

N

D

1

1.25V

C

Batt

ign

V

CF

Tigm

V

Tdsc

1.25 V

I

ign

Ignition

Cds

Drain

Polling

To

Logic

LAMP

DRAIN

P₁₆

Digital

Duty Cycle

Generator

Z2

Lamp

Driver

Circuit

A

500

N

D

2

4MSB

4 LSB

Osc

A

N

D

3

OR2

LAMP

GATE

8-Bit Counter

MUX

P ₂₅₆

U/D

Counter

Lamp

Polling

Thermal

Limit

Dtl

u/d

Up/Down

Control

Switch

A/D

u/d

Comparator

& Tracking

Current

Limit

Np

Battery

Rs

Stator

LCR TEST

LCR1

LRC2

AGND

GND

Alternate S tator

Configuration

Ground

Boundry for IC

REMOTE

PHASE

Figure 2. 33099 Simplified Internal Block Diagram

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

1

2

3

4

5

6

7

8

GATE

BAT

16

15

14

13

12

11

10

9

SOURCE

PHASE

NC

GND

LAMP DRAIN

LAMP GATE

IGNITION

LRC2

PHASE FILTER

LRC TEST

NC

REMOTE

AGND

LRC1

Figure 3. 33099 Pin Connections

Table 1. PIN Function Description

Pin Number Pin Name

Formal Name

Definition

Controls the GATE of the MOSFET to control the alternator field current.

Primary power connection to the system battery.

Source lamp current and digital ground.

1

2

3

4

GATE

BAT

GATE DRIVE

BATTERY

GND

GROUND

Controls the Fault Lamp current.

LAMP

LAMP DRAIN

DRAIN

Controls the Fault Lamp internal driver as an override function.

5

6

LAMP

GATE

LAMP GATE

IGNITION

Controls the ON or OFF function of the regulator.

Inputs for selecting the LRC rate.

IGN

7

8

LRC2

LRC1

LOAD RESPONSE

CONTROL 2

LOAD RESPONSE

CONTROL 1

Ground connection for analog circuitry.

9

10

AGND

REMOTE

NC

ANALOG GROUND

REMOTE

Provides for external Kelvin connection to system battery.

No internal connection to this pin.

11, 14

12

NO CONNECT

Provides acceleration of LRC rate for testing.

LRC TEST

LOAD RESPONSE

CONTROL TEST

Provides access to Phase Resistive Divider for External Phase Filter capacitance.

Input for phase voltage.

13

PHASE

FILTER

PHASE FILTER

15

16

PHASE

PHASE SENSE INPUT

SOURCE

Coupled to source of MOSFET to provide a GATE voltage reference and to monitor

for source shorts to ground.

SOURCE

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Rating

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage

V

24

40

V

BAT

Load Dump Transient Voltage ⁽¹⁾

Negative Voltage ⁽²⁾

+V

-V

MAX

MIN

-2.5

ESD Voltage

V

Human Body Model ⁽³⁾

Machine Model ^{(3) (4)}

ESD1

ESD2

±2000

±200

THERMAL RATINGS

Operating Junction Temperature

Operating Ambient Temperature Range

Storage Temperature Range

T

150

°C

J

T

-40 to 125

-45 to 150

A

T

STG

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation @ T_A= 125°C

Thermal Resistance, Junction-to-Ambient

P_D

640

85

mW

°C/W

°C

R_ΘJA

Peak Package Reflow Temperature During Reflow ⁽⁵⁾

,

T_PPRT

Note 6

(6)

Notes

1. 125 ns wide square wave pulse.

2. Maximum time = 2 minutes.

3. ESD1 testing is performed in accordance with the Human Body Model (C

=100 pF, R

=1500 Ω). ESD2 testing is performed in

ZAP

accordance with the Machine Model (C

=200 pF, R

=0 Ω).

ZAP

4. ESD2 voltage capability of PHASE FILTER pin is greater than 150 V. All other device pins are as indicated.

5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 7.0 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Regulation Voltage @ 50% Duty Cycle

Symbol

Min

Typ

Max

Unit

V

SET

V

= V or V

< V

MC33099

14.55

14.3

14.8

14.6

15.05

14.85

rem

set

rem

Trem

= V or V

MC33099C

set

Regulation Voltage Range

10% < DC < 95%

DVSET

mV

–

210

300

Regulation Voltage Temperature Coefficient (TC)

= V or V < V

TC(V

)

mV/°C

SET

V

-13

0.9

-11

-9

rem

bat

rem

Trem

Power Up/Down IGN Threshold Voltage

Operating Drain Current (Ignition ON)

V

1.25

1.6

V

TIGN

mA

V

> V

, V

= V = V , T_A= 25°C

I

–

6.5

8.0

8.4

ign

Tign rem ph set

Q1(ON)

Q2(ON)

, V

= V = V , -40°C ≤ T_A≤ 125°C

ph set

Tign rem

Standby Drain Current (Ignition OFF)

mA

V

< V

, V = 0 V, V

= V = 12.6 V, T_A= 25°C

bat

I

–

0.6

1.0

1.5

3.4

ign

Tign ph

rem

Q1(OFF)

Q2(OFF)

, V = 0 V, V

= V = 12.6 V, -40°C ≤ T_A≤ 125°C

I

Tign ph

bat

Remote Loss Voltage Threshold

V

4.2

4.5

4.0

4.8

V

TREM

Phase Detection Threshold Voltage

Undervoltage Threshold Voltage

V

3.75

4.25

TPH

TUV

V

= 14.8 typical

= 14.6 typical

MC33099

10.9

11.35

10.95

11.6

set

MC33099C

10.35

11.55

Overvoltage Threshold Voltage

V

TOV

V

= 14.8 typical

= 14.6 typical

MC33099

16.15

15.8

16.65

16.4

17.15

17.0

set

MC33099C

Overvoltage Threshold Voltage TC

Load Dump Threshold Voltage

TC(V

)

–

-12.4

–

mV/°C

V

TOV

V

TLD

V

= 14.8 typical

= 14.6 typical

MC33099

18.9

19.25

19.15

19.8

set

MC33099C

18.45

19.85

Load Dump Threshold Voltage TC

Secondary Regulation

TC(V

)

–

-14.3

–

mV/°C

V

TLD

V

SET2

V

= 14.8 typical

= 14.6 typical

MC33099

18.0

18.5

18.8

set

MC33099C

17.65

18.15

18.75

Secondary Regulation TC

Secondary Load Dump Threshold Voltage

TC(V

)

–

-13.4

–

mV/°C

V

SET2

V

TLD2

V

= 14.8 typical

= 14.6 typical

MC33099

23.5

24

25

set

MC33099C

23.85

24.65

Secondary Load Dump Threshold Voltage TC

TC(V

)

–

-17.9

–

mV/°C

TLD2

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 7.0 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Lamp Drain Short Circuit Threshold Voltage ⁽⁷⁾

Lamp Drain Short Circuit Current

Symbol

Min

Typ

Max

Unit

V

1.8

2.0

2.25

2.5

2.85

3.0

V

Amps

V

TDSC

I

DSC

Lamp Drain ON Voltage

V

D(SAT)

I

= 0.4 A

–

0.3

2.5

lamp

Lamp Drain-to-GATE Clamping Voltage

Lamp GATE Override Resistance

V

–

48.48

4.6

55

–

V

kΩ

°C

µA

V

DG

R

LG

LIM

PU

PD

Lamp Driver Thermal Shutdown Temperature Limit ⁽⁷⁾

GATE Drive Source Current

T

–

185

300

480

12

–

I

240

400

10

340

560

15

GATE Drive Sink Current

GATE Drive GATE-to-Source Clamping Voltage

Minimum Charge Pump GATE Drive Voltage

V

GS

V

G(MIN)

V

= V

source set

21.5

1.85

23.4

2.3

–

bat

Source Short Circuit Threshold Voltage

Remote Input Resistance

V

2.75

V

TSSC

R

kΩ

REM

V

= V

set

–

68

60

73

45

–

rem

Phase Input Resistance

= V

R

kΩ

µA

PH

V

ph

set

IGN Input Pull-Down Current

= 1.25 V

I

IGN

V

40

35

90

55

ign

LRC Input Current

= 0 V

I

LRC

V

lrc

Notes

7. Not 100% tested.

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 7.0 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Duty Cycle Regulation Output Frequency

/256

Symbol

Min

Typ

Max

Unit

F_DC

Hz

f

300

375

440

OSC

Phase Rotation Detection Frequency

Low/High RPM Transition Phase Frequency

GATE Duty Cycle at Startup and WOT

F₁

44.28

267.5

49

53.8

325

Hz

%

F

2

296

DC

START

f

> f2

30

29

31.25

3.1

34.5

33.5

3.3

ph

Minimum GATE LRC Duty Cycle

< f2

DC

%

(LRC)MIN

f

ph

Minimum GATE Duty Cycle

> V

DC

MIN

V

2.1

bat

reg(max)

LRC Increasing GATE Duty Cycle Rate

%/s

Low RPM Mode (f < f2)

ph

LRC1 at GND, LRC2 at GND

LRC1 Open, LRC2 at GND

LRC1 at GND, LRC2 Open

LRC1 Open, LRC2 Open

R

–

9.31

12.45

18.71

37.42

616

–

LRC1

LRC2

LRC3

LRC4

R

High RPM Mode (f > f2)

ph

R

LRC(MAX)

Ignition Turn OFF Delay (Lamp ON)

Lamp Short Circuit ON Polling Frequency

Lamp Short Circuit ON Duty Cycle

Lamp OFF Polling Frequency

T

–

10.2

98.6

1.56

98.6

1.56

98.6

1.56

–

ms

Hz

%

ID(OFF)

F

LSC

DC

L

F

Hz

%

L(OFF)

Lamp Polling OFF Duty Cycle

DC

L(OFF)

Field Short Circuit ON Polling Frequency

Field Short Circuit Polling ON Duty Cycle

F

Hz

%

FSC

DC

F

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33099 is specifically designed for regulation of an

automotive system voltage using diode-rectified alternator

charging systems commonly found in automotive

applications. The 33099 provides either an analog or digital

duty cycle control of an ON/OFF ratio of an alternator field

current at a fixed frequency. This provides for a Load

Response Control (LRC) of the alternator field current at low

engine RPM to eliminate engine speed hunting and vibration

owing to abrupt torque loading of the engine when a sudden

electrical load is applied to the system. Four LRC rates are

selectable using a combination of pins 7 and 8 being

connected to ground.

The 33099 provides a regulated voltage feedback system

to activate the alternator field current in response to system

load current. The output voltage is monitored by an internal

voltage divider scheme and compared to an internal voltage

ramp referenced to a bandgap voltage. The 33099 regulates

the system voltage to 14.8 V for the DW suffix and to 14.6 V

for the CDW suffix by generating a pulse width modulation

(PWM) voltage waveform at the GATE of an external

MOSFET to provide an average alternator field coil current as

a function of the internal voltage comparison.

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

TYPICAL APPLICATIONS

INTRODUCTION

TYPICAL APPLICATIONS

INTRODUCTION

The 33099 is an alternator voltage regulator designed with

internal level shifting resistors to control the voltage in a 12 V

automotive system that uses a three-phase alternator with a

rotating field winding. The system shown in Figure 4 includes

an alternator with its associated field coil, stator coils and

rectifiers, an automotive battery, a fault indicator lamp, an

ignition switch, a field flyback diode, and the 33099.

REMOTE

BATT

V

rem

Charge

Pump

Regulator

CB1

V

rs

Internal

V

reg

and Bias

Current

DD

Regulator

FB

Bandgap

Reference

Regulator

0.6 V

LB

RF

Regulator

V

g

V

C

fb

Vl

rs

V

o

Local

Low

Pass

l

pu

V

Cf

DD

V

ref

(OTC)

(5.0 V)

(2.0 V)

A

N

D

4

Vls

1.25 V

S3

Local

GATE

Z1

Sense

S1

UV

R4

Min Duty

Cycle

Generator

R1

C

CB2

uv

1.25 V

R5

Gate

Polling

Circuit

R2

R3

Battery

LD

l

pd

V

Tssc

Over

OR1

PHASE

Css

S2

Voltage

Detector

V

hvl

Ign

OV

SOURCE

IGN

Delay

Circuit

C

ph

PHASE

FILTER

C

dc

F1

F2

DAC

A

N

D

1

1.25V

Tigm

C

V

Battery

ign

dac

V

Tdsc

1.25 V

I

ign

Drain

Polling

Circuit

C

ds

To

Logic

1

2

LAMP

DRAIN

P₁₆

Digital

Duty Cycle

Generator

101 kHz

Osc

Z2

Lamp

Driver

Circuit

A

N

D

2

4 MSB

4 LSB

A

10

11

OR2

N

D

3

LAMP

GATE

8-Bit Counter

P₂₅₆

MUX

U/D

Counter

Thermal

Limit

Detector

Lamp

Polling

Circuit

Dtl

u/d

Up/Down

Control

Switch

A/D Duty Cycle

Comparator

& Tracking

Circuit

u/d

Current

Limit

Np

Detector

Rs

LCR TEST

LCR1

LRC2

GND

AGND

Figure 4. 33099 Simplified Application

The 12 V system voltage (V

) is connected to a

phase rotation detection frequency (f₁) and a Low/High RPM

transition phase frequency (f₂), respectively. A PHASE

FILTER pin is provided for externally providing a filter

capacitance for filtering phase input noise.

BAT

REMOTE input by a remote wire, which provides the IC

regulator with an external Kelvin connection directly to the

battery to provide REMOTE voltage, V_rem. The system

voltage at the BAT pin is also sensed by an internal Local IC

connection as Local voltage V_l. The Local connection is

provided in the event the remote wire or remote connection

becomes faulty such as being resistive, an open, or shorted

to ground.

The regulated DC system set voltage (V_set) is achieved by

employing feedback to compare a ratioed value of V_setto an

internal IC bandgap voltage reference having a negative

temperature coefficient (TC). The GATE drive of an external

N-channel MOSFET is regulated by the IC to control the field

current in the alternator field coil as an alternating ON or OFF

state dependent on load current conditions affecting voltage

V_set. The external MOSFET receives GATE-to-source

voltage drive from between the GATE and SOURCE output

pins of the IC. The GATE-to-source voltage is a Pulse Width

33099

The PHASE input is normally connected to a tap on one

corner of the alternator's stator winding, which provides an

AC phase voltage (V_ph) for the IC to determine the rotational

frequency (f_ph) of the alternator rotor. Two frequency

comparators (F1 and F2) monitor voltage V_phto determine a

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

TYPICAL APPLICATIONS

Modulated (PWM) waveform having a variable ON/OFF duty

cycle ratio that is determined by an analog or a digital duty

cycle control circuitry that responds to variations in the

system voltage due to variations in system load current. The

PWM waveform has a duty cycle regulation output frequency

of about 395 Hz (f_dc) defined by an 8-bit division of an internal

101 kHz oscillator clock frequency (f_osc). The GATE voltage

at the GATE pin is due to a charge pump GATE voltage (V_g)

generated by voltage multiplication using an internal charge

pump voltage regulator. The high GATE-to-source voltage

applied to the external MOSFET during the ON cycle of the

PWM waveform minimizes a low drain-to-source ON

resistance (R_DS(ON)) and associated drain-to-source voltage

V_d(SAT)to maximize the field current while minimizing the

associated power dissipation in the MOSFET.

overvoltage Lamp fault indication, and is regulated at a

secondary value of about 18.5 V.

During a system load dump condition, load dump

protection circuitry prevents GATE-to-source drive to the

external MOSFET and to the internal lamp drive MOSFET.

This ensures that neither the field current nor the lamp

current is activated during load dump conditions. A drain-to-

GATE voltage clamp is also provided for the internal lamp

driver for further protection of this driver during load dump.

An ignition pin (IGN) is provided to activate the regulator

from the standby mode into a normal operating mode when

the ignition switch is ON and an ignition voltage (V ) is

ign

greater than a power up/down ignition threshold voltage

(V

). When the ignition switch is OFF, voltage V is less

Tign

ign

than voltage V

, and the regulator is switched into a low

Tign

A unique feature of the 33099 is the combinational use of

analog and digital duty cycle controllers to provide a Load

Response Control (LRC) duty cycle function when rotor

frequency f_phis less than frequency f₂. A classic analog duty

cycle function is provided at the GATE output when

current standby mode, when frequency f < f . The IGN pin

ph

1

can either be coupled to the low side of the ignition switch or

to the low side of the lamp. When the IGN pin is connected to

the low side of the lamp, the lamp must be shunted by a

resistor to ensure that ignition ON is sensed, even with an

OPEN lamp fault condition. When the lamp in ON, lamp

current is polled OFF periodically at an ignition polling

frequency in order for the IGN pin to periodically sense that

the ignition voltage is high even though the lamp is ON. An

frequency f_phis greater than frequency f₂. During the LRC

mode when f₁< f_ph< f₂, a sudden decrease in the system

voltage due to a sudden increase in system load current will

cause the analog duty cycle to rapidly increase to as great as

100%. However, the LRC circuitry causes the digital duty

cycle to increase to 100% at a controlled predetermined LRC

rate and overrides the analog duty cycle. Thus the alternator

response time is decreased in the LRC mode and prevents

the alternator from placing a sudden high torque load on the

automobile engine during this slow RPM mode. This can

occur when a high current accessory is switched on to the 12

V system, producing a sudden drop in system voltage. When

frequency f_phis greater than frequency f₂, the slow LRC

response is not in effect and the analog duty cycle controller

controls the PWM voltage waveform applied to the external

MOSFET to regulate the system voltage. By selectively

coupling the LRC1 and LRC2 pins to ground or leaving them

ignition input pull-down current (I ) is provided to pull

ign

voltage V to ground when the IGN pin is OPEN or

ign

terminated on a high resistance.

Two ground pins are provided by the 33099 to separate

sensitive analog circuit ground (AGND) from noisy digital and

high-current ground (GND).

ALTERNATOR REGULATOR BIASING AND

POWER UP/DOWN

The biasing of the regulator is derived from the BAT pin

voltage V . In the normal operating mode when the ignition

bat

switch is ON and voltage V is greater than V

(about

ign

Tign

1.25 V), a 5.0 V V_DDvoltage regulator biases the IC logic and

provides bias to a bandgap shunt voltage regulator. The

open, the user can program four different LRC rates (R

-

lrc1

R

) from 9.37%/sec to 37.4%/sec. During an initial ignition

lrc4

bandgap regulator maintains a reference voltage (V ) of

ON and engine start-up, the LRC rate is also in effect to

ref

approximately 2.0 V with an internal negative temperature

coefficient (-TC) as well as a 1.25 V Zero Temperature

Coefficient (OTC) reference voltage. Additional bias currents

and reference voltages, including a charge pump GATE

voltage V , are also generated from voltage V . The

minimize alternator torque loading on the engine during start,

even when a Wide Open Throttle (WOT) condition (f_ph> f₂)

occurs.

An internal N-Channel MOSFET is provided on the IC to

directly drive lamp current as a fault indicator. The fault lamp

is connected between the low side of the ignition switch and

the LAMP DRAIN pin of the IC. A fault is indicated during an

undervoltage battery condition when frequency f_phis greater

than frequency f₂, during an overvoltage battery condition,

and when frequency f_phis less than frequency f₁. Frequency

g

bat

typically ignition ON drain current (I

) is about 6.5 mA at

Q1(on)

25°C. When the ignition switch is OFF and voltage V is

ign

less than V

, the regulator is in a low current standby

Tign

mode, having a standby drain current of about 0.7 mA

(I ) at 25°C. During the sleep mode, some internal

Q1(off)

voltage regulators and bias currents are either terminated or

minimized. However, the V_DDregulator and the bandgap

voltage regulator continue to maintain voltages V_DDfor the

f_ph< f₁when an insufficient alternator output voltage results

or a slow or non-rotating rotor occurs due to a slipping or

broken belt. An external LAMP GATE pin is also provided for

the internal lamp driver to allow the user to override the

internal IC fault logic and externally drive the internal lamp

drive MOSFET.

logic, the 2.0 V V , and the 1.25 V reference voltage. In

ref

addition, all logic is reset in the standby mode.

After switching the ignition switch to the ON position,

voltage V will exceed voltage V

_,causing comparator

ign

Tign

When a loose wire or battery pin corrosion causes the

Remote voltage to decrease but is not a Remote Open

condition, the system voltage will increase, causing an

C

to switch states, providing an ignition-ON signal to the

ign

Ignition Delay circuit. After an Ignition start Delay Time of

500 ms, the Ignition Delay circuit activates additional current

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

TYPICAL APPLICATIONS

for the V_DDregulator and activates all other voltage

regulators and bias currents. After engine start, the LRC

mode is activated, independent of the phase frequency or

independent of a Wide Open Throttle condition. When the

the combiner CB2 is normally 0.8 V (or 1.6 V typically),

ls

while voltage V on the input of CB1 is typically 2.0 V.

rs

Because voltage V reflects the highest voltage at the input

o

of either combiner, voltage V will be voltage V in Remote

o

rs

battery system voltage increases to V , the regulator

operation with Remote connected to V . For this case,

set

bat

resumes the normal operational mode. After switching the

voltage V is filtered by a 300 Hz low-pass filter and

rs

ignition switch to the OFF position, voltage V decreases

translated to the FB buffer output. Voltage V at the FB buffer

ign

rs

below voltage V

, causing the comparator C to provide

output is then compared to a digital-to-analog converter

Tign

ign

an ignition-OFF signal to the Ignition Delay Circuit. After

output voltage ramp (V ) for duty cycle regulation.

dac

phase frequency f < f due to ignition turn OFF, supply

currents and voltages are reduced in the regulator to provide

the standby drain current drain. However, voltage V_DDfor

logic and voltage V for reference voltages remain active to

ref

ph

1

During a Remote fault condition when the remote sense

line is OPEN or grounded, voltage V at the Remote Sense

rs

input will be zero, causing comparator C to activate

rs

switches S1 and S2 to a CLOSED position. As a result,

be able to sense an ignition input voltage.

voltage V is coupled through buffer LB directly to the input

ls

In some applications, the ignition input is connected to the

low side of the fault lamp as shown in Figure 4, page 9. When

the lamp driver circuitry is generating a lamp ON signal, a

lamp polling signal causes the Lamp Drain output to be

of combiner CB2. Because the voltage V on the input of

ls

combiner CB2 is greater than voltage V (= 0 V) on the input

rs

of combiner CB1, voltage V is coupled to the output of the

ls

combiners as voltage V . Thus in this fault case, voltage V

o

ls

periodically GATED OFF. As a result, voltage V > V

is filtered and translated to the FB buffer output for being

ign

Tign

during the lamp OFF polling period, causing comparator C

compared to voltage ramp V

for regulation.

ign

dac

to periodically provides an ignition-ON signal to the Ignition

Delay Circuit. During the Lamp On condition, the Ignition

Delay Circuit provides a minimum ignition turn-off delay

During a remote fault condition in which the resistance of

the Remote sense wire increases due to the corrosion or a

loose connection, a finite external remote fault resistance

(t

) such that all currents and regulator voltages remain

id(off)

occurs causing voltage V

to decrease, but voltage V

rem rem

ON between the Lamp Off polling pulses.

remains greater than voltage V

. As a result, switches S1

Trem

and S2 remain in an OPEN condition, while the system

BATTERY AND ALTERNATOR OUTPUT VOLTAGE

SENSING

voltage will increase due to the effective increase in the

Remote resistor divider ratio. As a result, voltage V increases

l

until the voltage at the input of combiner CB2 is

The system battery voltage is directly sensed by the

REMOTE input using a remote wire as a Kelvin connection.

approximately 2.0 V, or V is about 1.2 (2.0 V), or 2.25 V due

ls

to the R4/R5 divider ratio. Because the local divider ratio

The Remote input resistance (R

) at the REMOTE input is

rem

translates voltage V to V

by about factor 7.4, the final

ls

bat

typically 68 kΩ. The voltage at the Remote Sense input (V )

rs

regulated output voltage for this condition is 7.4 (2.25), or

18.5 V. This is the secondary regulation voltage (V ).

is a ratioed value of the Remote voltage (V

). The intended

rem

set2

ratio of V

/V is about 7.45. The BAT pin voltage (V ) is

rem rs

bat

When the system voltage increases to the Overvoltage

also sensed as an internal Local voltage (V ). A Local Sense

l

Threshold (V ), a fault indication occurs by the lamp. Thus

Tov

voltage (V ) is a ratioed value of voltage V , where the

ls

l

this particular Remote fault condition produces a fault

indication, but regulates to prevent an extreme system

overvoltage condition. When the Remote fault resistance

intended ratio of V /V is also 7.45. The Local internal

l

ls

connection is provided for fault protection against the remote

wire being grounded or exhibiting a high remote wire

resistance due to being disconnected or due to a corrosive or

loose connection. Thus the Local connection ensures that

alternator regulation of the system voltage continues in well-

defined states for all possible Remote input fault conditions.

becomes great enough to cause voltage V

< V

, the

rem

Trem

regulated system voltage returns to the local regulation as

described for an OPEN or grounded Remote input.

INTERNAL CLOCK OSCILLATOR AND 8-BIT

COUNTER

LOCAL AND REMOTE VOLTAGE PROCESSING

AND SWITCHING

An internal clock oscillator is provided having a typical

oscillation frequency (f ) of 101 kHz. The output of the

osc

During Remote operation both the external Remote input

connection and internal Local connection senses

oscillator is coupled to an 8-bit counter that provides

8 counting bits to the logic and the four most significant

counting bits (MSB) to the LRC circuitry and to a digital-to-

analog converter (DAC) waveform generator. The output

approximately the same regulated system voltage of V

=

set

14.8 V. For this case, voltages V and V are approximately

rs

ls

2.0 V. Because the remote switching comparator C is

rs

MSB frequency (f

) of the 8-bit divider is about 395 Hz

msb

referenced to 0.6 V, both switches S1 and S2 are OPEN and

(f

= f

/256), which determines the PWM frequency at

msb

osc

remain open when voltage V > 0.6 V or when voltage V

rs

rem

the GATE output. An external LRC TEST pin is provided for

accelerating internal testing of the LRC function and logic.

Under normal operation, the LRC TEST pin is grounded by

an internal 10 kΩ resistance to ground. Under accelerated

test conditions, the LRC TEST voltage is 5.0 V, and a fourth

is greater than the remote loss threshold voltage (V

).

Trem

Voltage V is coupled to the input of a unity-gain combiner/

rs

buffer CB1. Voltage V is buffered and coupled to the output

ls

of a unity-gain Local Buffer (LB) and ratioed by the R5/

(R4+R5) resistor divider to provide an input voltage to a unity-

gain combiner/buffer CB2. Thus the voltage at the input of

bit (f

/16) from the 8-bit divider is used to determine the

osc

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

TYPICAL APPLICATIONS

PWM GATE frequency. Thus, the rates are accelerated by a

factor of 16.

frequency is (f /256), or 395 Hz. Since voltage V has a

osc ref

negative TC, voltage V will also have a regulation voltage

set

temperature coefficient (TC

) of about -11 mV/°C.

Vreg

LOW-PASS FILTER, DAC, AND ANALOG DUTY

CYCLE REGULATOR COMPARATOR

INPUT PHASE AND FREQUENCY SWITCH

RESPONSE

The output voltage V of combiners CB1 and CB2 is

o

coupled to an input of a 300 Hz low-pass filter (Rf, Cf) to

The phase voltage V results from the alternator's stator

ph

remove high-frequency components of system noise at V

AC output voltage being applied to the PHASE input pin.

bat

and thus associated with voltages V , or V . The output of

A phase detection threshold voltage (V

) is approximately

ls

rs

Tph

the low-pass filter is coupled to a unity-gain buffer FB that

4.0 V due to the 1.25 V phase reference voltage for the phase

provides a filter buffer FB output.

comparator (C ) and the 3.22 voltage ratio associated with

ph

the phase input resistor divider. The phase input resistance

The 4 MSBs of the 8-bit counter causes the DAC to

generate a 4-bit 395 Hz voltage waveform having

(R ) is typically 60 kΩ. A PHASE FILTER pin is coupled to

ph

the input of Comparator C , providing for an external phase

16 descending 1.75 mV steps, ramping from V to [V

-

ph

ref

filter capacitance when filtering of high frequency phase

noise is desired. A typical value of .003 µF to AGND provides

for an input phase 3.0 db roll-off frequency of about 10 kHz.

28 mV], where V is the 2.0 V reference voltage.

ref

An analog duty cycle comparator (C ) compares the DAC

dc

output voltage waveform to the voltage at the FB output (V ).

fb

Comparator C also provides about 480 mV of hysteresis at

ph

When voltage V is less then voltage [V - 28 mV],

fb

ref

the PHASE input pin. Comparator C further provides a

ph

phase signal binary output voltage having a phase frequency

comparator C outputs a logic [1], for a 100% duty cycle.

dc

When voltage V is greater than V , comparator C

dc

fb

ref

of f and is applied to digital frequency switches F1 and F2.

ph

outputs a logic [0] for a 0% duty cycle. When (V

-

ref

Switch F1 outputs a logic [1] when frequency f is less then

ph

28 mV) < V < V , comparator C outputs a duty cycle

fb

ref

dc

phase detection frequency f . Frequency f is equal to

1

defined by the High/Low output voltage ratio for each period

(about 2.54 ms) of the DAC output voltage waveform.

frequency f

/8, or 49.3 Hz for a 101 kHz oscillator

msb

frequency. Switch F2 outputs a logic [1] when the frequency

f

is greater then the low/high transition frequency f .

ph

2

BASIC SYSTEM VOLTAGE REGULATION

Frequency f₂is equal to frequency 3f

/4, or 296 Hz for a

msb

From a system voltage regulation viewpoint, the voltages

101 kHz oscillator frequency. These frequency switches are

used to define the Load Response Control region of

operation, an undervoltage at a high RPM fault condition, and

a low RPM fault condition due to a broken or loose belt.

V

and V from the Remote or Local connections,

rem

l

respectively, are scaled to the Remote Sense and Local

Sense inputs as voltages V and V respectively and

rs

ls

transferred to the FB output as voltage V . Voltage V is

fb

compared to the DAC output voltage waveform to generate

the ON and OFF time of the analog duty cycle waveform.

When voltage V is less than V - 28 mV, the output of

LOAD RESPONSE CONTROL (LRC)

The LRC circuit consists of a digital duty cycle generator,

an analog/digital (A/D) duty cycle comparator and tracking

circuit, an up/down control switch, an up/down (U/D) counter,

a programmable divider (Np), and a multiplexer (MUX).

During normal operation, the LRC circuit becomes active and

generates digital duty cycle control of the GATE drive when

fb

ref

comparator C is in a high state. This high state propagates

dc

through an AND3 GATE, an OR1 GATE, and an AND4 GATE

to activate switch S3, generating a fully ON or High GATE

drive voltage. When voltage V is greater than V , the

fb

ref

output of comparator C is in a low state. This low state

dc

frequency f is less than frequency f (f < f < f ). The slow

ph

2

1

ph

2

propagates through the AND3 GATE, the OR1 GATE, and

the AND4 GATE to activate switch S3 to generate a fully OFF

LRC response becomes inactive and the analog duty cycle

controls the GATE drive when frequency f_phis greater than

or low GATE drive voltage. Assuming voltage V is 2.0 V

ref

frequency f (f < f < f ). During initial ignition and initial

2

1

ph

2

and V = V , and the local or remote input resistive scale

fb

rs

engine start, the LRC response is in effect, independent of

factor is 7.45, the external MOSFET provides a fully ON field

current when the system voltage is less than 7.45

frequency f , until system voltage is regulating at voltage

ph

V

.

set

(V - 28 mV), or 14.6 V. The field current is also fully OFF

ref

The digital duty cycle generator receives the 4 MSBs from

the 8-bit counter as input and generates 11 discrete digital

duty cycles on 11 output lines. The frequency of each duty

when the system voltage is greater than 7.45 (V ), or

ref

14.9 V. When voltage V is less than any portion of the DAC

fb

waveform voltage, comparator C output is high to produce

dc

cycle waveform is about 395 Hz (f

), which results from the

an ON field current. When voltage V is greater than any

msb

fb

MSB of the 8-bit division of the 101 kHz OSC clock

portion of the DAC waveform voltage, comparator C output

dc

frequency. The minimum duty cycle on the first output line is

31.25% and the maximum duty cycle on the eleventh output

line is 93.75%. The duty cycle difference between each

incremental duty cycle is 6.25%. All 11 duty cycle generator

output lines are coupled as data inputs to the MUX.

is low to produce an OFF field current. Thus the system

feedback will regulate the PWM duty cycle of the field current

from 0% to 100% over about a 210 mV system regulation

voltage range (dVreg). The system voltage is centered at

14.8 V, where a 50% duty cycle field current results for an

average system load current, and the duty cycle regulation

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

TYPICAL APPLICATIONS

Normally the programmable divider Np divides frequency

by a counter divide ratio N and applies the f /N

frequency as input to the U/D counter. Divide ratio N can be

pre-selected by the user for four different divide ratios by

switching a combination of the LRC1 and LRC2 normally

digital duty cycle to track the analog duty cycle. If the analog

duty cycle increases to a value greater than the digital duty

cycle at a rate that is greater than the selected LRC digital

duty cycle rate, the A/D duty cycle comparator will output an

up signal on the u/d line to cause the digital duty cycle to

increase to the analog duty cycle at the selected LRC digital

duty cycle rate. If the analog duty cycle decreases to a value

less than the digital duty cycle, the A/D duty cycle comparator

will output a down signal on the u/d line to cause the digital

duty cycle to decrease to the analog duty cycle at a fixed rate

of about 10 ms/step. For an analog duty cycle less than

31.25%, the down count at the output of the U/D counter will

remain at 0 and the digital duty cycle will remain at 31.25%.

f

msb

open pins to ground. An LRC input current (I ) from each

lrc

LRC pin to ground is about 45 µA. The phase frequency f

ph

and an up/down (u/d) state on a u/d line from the up/down

control switch determines ratio N. In the LRC mode when

f

< f , a high, or up, state on the u/d line causes divider Np

2

ph

to output a frequency of f

/N, or 395 Hz/N. The LRC1 and

msb

LRC2 pin combinations produce N divide ratios of 66, 132,

198, and 264. When the u/d line is in the down, or low, state,

divider Np provides a divide ratio of f

/4, or 395 Hz/4.

msb

If frequency f is less than frequency f (f < f ), then the

ph

1

ph

1

When f > f₂, the output frequency of divider Np is always

ph

up/down control switch will provide a down signal on the u/d

line independent of the duty cycle comparator u/d output. The

resulting down count of 0 to the MUX control input for f < f

f

/4 = 395 Hz/4, independent of the state of the u/d input

msb

line.

ph

1

The u/d line from the up/down control switch determines

the direction of the count as well as the divide ratio N. For an

up state on the u/d line, the output of the 4-bit U/D counter

increments up at a rate of 5.98 Hz (count change every

167 ms) for N=66, 2.99 Hz (count change every 334 ms) for

N=132, 1.99 Hz (count change every 502 ms) for N= 198, or

1.496 Hz (count change every 671 ms) for N=264. For a

down state on the u/d line, the output of the 4-bit U/D counter

decrements at a rate of about 99 Hz (count decrement about

every 10 ms). The 4-bit output lines of the up/down counter

are coupled as control inputs of the MUX.

will cause the digital duty cycle to be constant at 31.25% and

provides a divide ratio of f

U/D counter.

/4 as the input frequency to the

msb

When approximately 5.0 V is applied to the LRC TEST pin,

divider Np utilizes the f /16 frequency as input to the divider

osc

instead of the normal f /256 frequency. As a result, the

osc

LRC function is accelerated by a factor of 16, which allows

the testing of all LRC associated rates to be accelerated by a

factor of 16. During normal LRC operation, the LRC pin is in

a low ground state, having an internal 10 kΩ pull-down

resistor.

The MUX couples one of the 11 digital duty cycle input

lines to the MUX output dependent upon the 4-bit control

inputs from the U/D counter. When the MUX control input

count is 0, the first 31.25% digital duty cycle is selected and

provided at the MUX output. When the control input count is

10, the eleventh 93.75% digital duty cycle is selected at

output of the MUX. A MUX control input of 11 produces a

100% duty cycle at the MUX output. Thus each of the MUX

input lines is selected and provided at the MUX output and

incremented to the next line at a rate dependent on the rate

the MUX control inputs increment. For an up state on the u/d

line, the digital duty cycle at the output of the MUX will

increment from 31.24% to 100% in 11 steps at a rate from

The duty cycle output of the AND3 GATE reflects the

minimum duty cycle at the AND3 GATE inputs. Thus when

the analog duty cycle exceeds the digital duty cycle, the

digital duty cycle becomes the controlling duty cycle at the

AND3 GATE output. When the analog duty cycle is less than

the digital duty cycle, the analog duty cycle becomes the

controlling duty cycle at the AND3 GATE output. Thus in the

LRC mode when f < f < f , an increasing step response in

1

ph

2

the analog duty cycle from 0% to 100% will cause the duty

cycle at the output of the AND3 GATE to increase rapidly

from 0% to 31.25% and then increase slowly at the LRC rate

from 31.25% to 100%. If the analog duty cycle provides a

step increase from a duty cycle greater than 31.25%, then the

resulting LRC duty cycle increase from the initial analog duty

cycle at the output of the AND3 GATE. For a decreasing step

response in the analog duty cycle, the output of the AND3

GATE will rapidly follow the decreasing analog duty cycle.

The output of the AND3 GATE drives the GATE output (and

the field current) through an OR1 GATE, an AND4 GATE,

and switch S3. Thus the minimum GATE LRC duty cycle

167 ms/step (or a fourth LRC rate (R ) of 37.42%/sec) to

lrc4

671 ms/step (or a first LRC rate (R ) of 9.31%/sec)

lrc1

dependent on the LRC1 and LRC2 pin terminations. For a

down state on the u/d line, the digital duty cycle will count

down at a rate of about 10 ms/step change.

The A/D duty cycle comparator and tracking circuit

receives the analog duty cycle from comparator C and the

dc

digital duty cycle from the MUX output. The A/D duty cycle

comparator provides a high, or up (u), output when the

analog duty cycle is greater than the digital duty cycle, and a

low, or down (d), output when the analog duty cycle is less

than the digital duty cycle.

(DC

) is 31.25%.

(LRC)min

A 0% analog duty cycle will produce a 0% duty cycle at the

output of the AND3 GATE. However, the output of the AND3

GATE is ORed with a 3.1% minimum duty cycle signal from

the minimum duty cycle generation at the OR1 GATE input to

provide a minimum 3.1% duty cycle to the AND4 GATE input.

This provides the resulting minimum GATE duty cycle

In the LRC mode when frequency f < f < f , the up/

1

ph

2

down control switch enables the u/d output of the A/D duty

cycle comparator to be coupled to the u/d line. In the steady

state, the A/D duty cycle comparator will provide an u/d input

to the U/D counter and Np divider to increase or decrease the

(DC ) of 3.1% at the GATE output, even though the analog

min

duty cycle is 0%.

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

TYPICAL APPLICATIONS

When the phase frequency is greater than frequency

condition. This GATE polling circuit provides short GATE

polling pulses to the AND4 GATE to allow the IC to test for an

unshorted condition without damaging the external MOSFET.

The polling duty cycle is 1.56%, or about a 158 µs ON pulse

f (f > f ), the N divide factor is reduced to 4. As a result,

2

ph

2

the LRC circuitry still functions as previously described, but

the rate of digital duty cycle increase or decrease is a

maximum LRC rate (R

) of about 10 ms/step. Thus a

at a frequency of f

/4, or 98.6 Hz. When the source

lrc(max)

msb

step increase in the analog duty cycle from 31.25% to 100%

will cause about a 110 ms delay before the digital duty cycle

provides a 100% duty cycle at the output of the AND3 GATE

(and GATE drive).

shorting condition is removed, comparator C_ssprovides a no-

short signal to the GATE polling circuitry, which provides a

logic [1] to the AND4 GATE, which then operates normally.

The AND4 GATE is also driven by the no load dump (LD)

line from the Overvoltage Detector circuitry. Thus during a

load dump system overvoltage condition, a logic [0] is

provided to the AND4 GATE from the Overvoltage Detector

circuit and all GATE drive is terminated.

The conditions for LRC response also occur during an

initial engine start up period after engine cranking even when

a WOT condition occurs (f > f ). When the ignition switch is

ph

2

turned ON, comparator C is activated, activating all biasing

ign

into the normal state and activating the start-up LRC mode.

After engine cranking and immediately after initial engine

start up, the system BATTERY voltage is generally low while

a WOT condition occurs. For this case, the slow LRC

response is in effect to prevent excessive torque loading on

the engine by the alternator during engine start up. The

A flyback diode MR850 is externally provided to limit the

negative source voltage on the field pin (and the SOURCE

pin) caused by a turn-OFF transition of the field current. The

forward current through this diode is approximately the peak

field current prior to field current turn OFF.

GATE duty cycle at start-up with WOT (DC

minimum LRC duty cycle and will increase at the LRC rate.

Once the system voltage returns to voltage V , the normal

) is the

start

FAULT LAMP INDICATOR—DRIVE AND

PROTECTION

set

The fault indicator lamp is driven by an internal N-channel

MOSFET lamp driver, which controls the lamp current. The

lamp is coupled between the ignition switch and the LAMP

DRAIN pin of the lamp driver. The Lamp GATE of the lamp

driver is driven by the lamp driver circuitry or from an external

LAMP GATE pin. Inputs to the lamp driver circuitry are from

an output of an AND2 GATE, an output of a thermal limit

circuit, and an output of a current limit circuit. By applying an

LRC response will occur as previously described.

FIELD COIL DRIVE AND DEVICE PROTECTION

The external MOSFET provides PWM drive current from

the system BATTERY to the field coil for system voltage

regulation. The GATE-to-Source voltage for this MOSFET is

provided by the IC's GATE-to-SOURCE pin drive voltage.

During the ON state, the AND4 GATE activates switch S3 to

external Lamp GATE override voltage (V ) to the LAMP

go

couple the GATE drive pull-up source current (I ) to the

pu

GATE pin (5), the Lamp Drain current will increase, providing

lamp current independent of the lamp driver logic state. When

the lamp driver circuity is forcing the lamp driver OFF, the

LAMP GATE pin resistance to ground will be about 4.6 kΩ.

The source of the lamp driver is coupled to ground through an

internal current sense resistor R_S. When the lamp is ON, the

GATE output. Current I drives the GATE of the MOSFET to

pu

the charge pump GATE voltage V_g(typically 23 V), causing

the MOSFET to drive the field coil pin to near the system

BATTERY voltage. Voltage V has a minimum charge pump

g

GATE voltage (V

) of 21.5 V. This high GATE-to-Source

g(min)

voltage minimizes power dissipation in the external MOSFET

by minimizing a Drain-to-Source ON resistance (R_DS(ON)) of

the MOSFET during the ON state. This results in a typical

Lamp Drain ON voltage (V

) is the Lamp Drain-to-ground

d(sat)

voltage measured at 400 mA of Lamp Drain current.

Normally, current flows through the lamp driver (and

lamp), indicating a fault when the output of the AND2 GATE

is a logic [1]. Assuming the lamp is not shorted, is not being

current limited, is not in the thermal shut down mode, and the

system is not in a load dump mode, the lamp ON current is

controlled by the output of the OR2 GATE. The output of the

OR2 GATE is a logic [1] and the lamp will normally be ON

when the UV (undervoltage) line and the F2 output line are

both a logic [1] state, indicating an undervoltage condition

when frequency f > f . The output of the OR2 GATE is also

Lamp Drain ON voltage (V

) of about 0.3 V at a Lamp

d(sat)

Drain current of 400 mA as measured from the LAMP DRAIN

pin to ground. During the OFF state, the AND4 GATE

activates switch S3 to couple a GATE drive pull-down sink

current (I ) to the GATE output. Current I pulls the GATE

pd

voltage to the Source voltage, turning OFF the MOSFET and

its associated field coil current. The limited GATE current

drive of the MOSFET GATE capacitance reduces the

magnitude and frequency of the high-frequency components

associated with the GATE duty cycle waveform, minimizing

RFI. Zener diode Z1 is employed to provide a GATE-to-

ph

2

a logic [1] when the output of the OV (overvoltage) line is a

logic [1], indicating an overvoltage condition, or the output of

the F1 line is also a logic [1], indicating a loss of phase signal

(f < f ) due to a broken phase wire, broken or slipping belt,

Source clamping voltage (V ), which limits and protects the

GATE-to-Source voltage of the external MOSFET.

gs

ph

1

When the external MOSFET fails to increase the source

(or field coil pin) voltage to within a source short circuit

or otherwise failed alternator or open field circuit.

When the lamp current exceeds a lamp drain short circuit

threshold voltage (V

) of the BATTERY pin voltage

Tssc

current (I ), the voltage across resistor Rs will exceed a

dsc

(V

< [V

- V

]), a shorted-source comparator C

Tssc

bat

source ss

current limit threshold voltage associated with the current

limit circuitry. As a result, a signal is sent to the lamp driver

outputs a short circuit signal to a GATE polling circuit. A

shorted field coil to ground is an example of this fault

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

TYPICAL APPLICATIONS

circuitry to limit the lamp drive and regulates the lamp current

protect the regulator and associated external devices. As

previously discussed, a load dump signal during load dump

will prevent GATE drive to the external MOSFET and prevent

GATE drive to the lamp driver. Thus the external and internal

MOSFETs will turn OFF during a system load dump. As

previously discussed, the undervoltage and overvoltage

signals are also provided for fault indications.

to current I . When the power dissipation of the lamp driver

dsc

causes the temperature of the lamp driver to exceed a

thermal shut-down temperature limit (T ), a temperature

Lim

sensing diode (D ) causes the thermal limit circuitry to send

tl

a signal to the lamp driver circuitry to limit the lamp drive

current and reduce the power dissipation and resulting

device temperature. When the lamp driver is ON, but the

The undervoltage signal is provided on the UV line by an

Lamp Drain pin voltage is not below the BAT pin voltage V

by at least a lamp drain short circuit threshold voltage (V

bat

)

undervoltage comparator C having a voltage reference of

uv

Tdsc

1.25 V and a resistor divider voltage transfer of 1.26 from the

or ([V - V

] < V_Tdsc), comparator C will output a lamp

bat

drain

ds

FB output to comparator C input. When voltage V_fbon the

uv

short circuit signal to the Drain Polling circuit to indicate a

lamp shorted condition. The Drain Polling circuit provides a

low duty cycle polling output to the input of the AND2 GATE

to poll the lamp driver ON, continuously testing for a lamp

short without damaging the lamp driver. The polling duty

cycle is 1.56%, (or about a 158 µs ON pulse) at a frequency

FB output becomes less than 1.52 V, the voltage at input to

comparator C becomes less than 1.25 V, causing

uv

comparator C to output an undervoltage UV signal.

uv

Because voltage V is ideally voltage V (or voltage V ),

fb

rs

ls

and the ratio of V /V (or V /V ) is 7.45, the UV signal will

r

rs

l

ls

occur when the system voltage at the Remote input (or Local

of f

/4, or 98.6 Hz. After the lamp short has been removed,

msb

input) is less than an undervoltage threshold voltage (V ),

Tuv

the comparator C outputs a lamp not-shorted signal to the

ds

or 11.35 V. However, GATE AND1 ensures that frequency

Drain Polling circuitry, which provides a logic [1] to the AND2

GATE, which then operates normally.

f

must be greater than f before an undervoltage Fault is

ph

2

indicated by the lamp.

Lamp polling is also present when the lamp is ON. In this

case, lamp polling turns OFF the lamp for a short period of

time with the lamp being ON for the remainder of the time. In

this case the lamp ON duty cycle is 98.44% (or OFF for

The load dump and overvoltage detection also utilizes

similar resistor dividers and voltage comparators in an

Overvoltage Detect circuitry where all comparators are

referenced to voltage V , or about 2.0 V. When voltage V

ref

fb

158 µs) at a frequency of f

/4, or 98.6 Hz. This causes the

msb

on the FB output is greater than 2.58 V, or 1.29 V (V /V

ref fb ref

lamp voltage on the lamp drain pin to be greater than ignition

= 1.29), an output load dump signal of a logic [0] is generated

threshold voltage V for at least 158 µs of a 10.1 ms

Tign

on the LD line. Thus during load dump, voltage V (or V )

rs local

period. During the lamp ON mode, the Ignition Turn Off Delay

of the Ignition Delay circuit is greater then the 10.1 ms period.

As a result, the regulator biasing remains ON even when the

IGN pin is coupled to the LAMP DRAIN pin and the lamp

will be about 2.58 V, and the actual load dump threshold

voltage (V ) will be about 19.25 V, or 1.3 V . When

Tld

set

voltage V on the FB output is greater than 1.117 V (V /

fb

ref fb

V

= 1.117), an output overvoltage signal is generated on

ref

drain voltage is less than voltage V _nmost of the time when

Tig

the OV line. Thus voltage V (or V ) will be about 2.235 V,

rs

l

the lamp is ON.

and the actual overvoltage threshold voltage (V ) will be

Tov

The lamp driver is also protected from load dump, since

during load dump, the LD signal is a logic [0], preventing the

AND2 GATE from activating the lamp driver. In addition, a

drain-to-GATE clamp device Z2 limits the drain-to-GATE

about 16.65 V, or 1.125 V

.

set

The regulator also indicates an overvoltage condition on

the system during the Remote fault condition when the

remote wire resistance increases to a finite value and the

system voltage is being regulated by secondary regulation at

clamping voltage (V ) to about 40 V typically.

dg

V

. When a load dump occurs during secondary

set2

UNDERVOLTAGE, OVERVOLTAGE, AND LOAD

DUMP PROTECTION

regulation, the load dump threshold increases to 1.3 V

about 24 V.

, or

set2

An undervoltage, overvoltage and load dump condition is

sensed by the regulator to generate fault indications and to

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

DW SUFFIX

EG SUFFIX (PB-FREE)

16-PIN

PLASTIC PACKAGE

98ASB42567B

ISSUE F

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

• Added Revision History page

6/2006

5.0

• Converted to Freescale format

• Update to prevailing form and style

• Updated the data sheet to the current form and style

1/2007

6.0

• Added MCZ33099EG/R2 and MCZ33099CEG/R2 to the Ordering Information block.

• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter

from Maximum ratings on page 4.

• Added notes to Maximum ratings on page 4

33099

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

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MC33099

Rev. 6.0

1/2007


型号：	MC33099DW
厂家：	Freescale
描述：	Adaptive Alternator Voltage Regulator 自适应交流发电机电压调节器调节器电机
文件：	总18页 (文件大小：682K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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