MC33099DW/R2 [MOTOROLA]
Adaptive Alternator Voltage Regulator; 自适应交流发电机电压调节器
| 型号： | MC33099DW/R2 |
| 厂家： | 
MOTOROLA |
| 描述： | Adaptive Alternator Voltage Regulator |
| 文件： | 总20页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33099
Rev 4.0, 07/2004
SEMICONDUCTOR TECHNICAL DATA
33099
Adaptive Alternator Voltage
Regulator
The 33099 is designed to regulate the output voltage in diode-rectified
alternator charging systems common to automotive applications. The 33099
provides either an analog or digital fixed frequency duty cycle (ON/OFF ratio)
control of an alternator’s field current. Load Response Control (LRC) of the
alternator field current is accomplished by selecting the duty cycle for
prevailing engine conditions to eliminate engine speed hunting and vibrations
caused by abrupt torque loading of the engine owing to sudden electrical loads
being applied to the system at low engine RPM. Four LRC rates are
selectable.
ALTERNATOR VOLTAGE
REGULATOR
The 33099 uses a feedback voltage to establish an alternator field current
that is in harmony with system load currents. The output voltage is monitored
by an internal voltage divider scheme and compared to an internal voltage
ramp referenced to a bandgap voltage. This approach provides precision
output voltage control over a wide range of temperature, electrical loads, and
engine RPM.
DW SUFFIX
CASE 751G-04
16-TERMINAL SOICW
Features
• External High-Side MOSFET Control of a Ground-Referenced Field
Winding
• LRC Active During Initial Start
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
• V at ±0.1 V @ 25°C
set
A
• <0.1 V Variation Over Engine Speeds of 2,000 to 10,000 RPM
• <0.2 V Variation Over 10% to 95% of Maximum Field Current
• Controlled MOSFET and Field Flyback Diode Recovery Characteristics
for Minimum RFI
MC33099DW/R2
MC33099CDW/R2
-40°C to 125°C
16 SOICW
• Trimmed Devices Available at 14.6 V and 14.8 V (typical) V
set
33099 Simplified Application Diagram
33099
PHASE
FIELD
WINDING
GATE
SOURCE
PHASE FILTER
IGN
IGNITION
SWITCH
LAMP DRAIN
BAT
REMOTE
LRC1
LRC2
AGND
GND
CHASSIS
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© Motorola, Inc. 2004
Freescale Semiconductor, Inc.
REMOTE
B
BAT
V
rem
Charge
Pump
Regulator
CB1
V
rs
Internal
V
V
reg
and Bias
Current
DD
Regulator
FB
Bandgap
Reference
Regulator
0.6 V
LB
RF
V
g
Regulator
V
C
fb
Vl
rs
V
o
Local
Low
Pass
l
pu
V
Cf
DD
(5.0 V)
V
ref
(OTC)
(2.0 V)
A
N
D
4
Vls
1.25 V
S3
Local
Sense
GATE
S1
UV
R4
Min Duty
Cycle
Generator
R1
C
CB2
uv
1.25 V
R5
Gate
Polling
Circuit
R2
R3
Battery
Z1
LD
l
pd
PHASE
V
Tssc
Over
OR1
Css
S2
Voltage
SOURCE
Detector
V
hvl
Ign
OV
PHASE
FILTER
Delay
Circuit
C
ph
C
IGN
dc
F1
F2
DAC
A
N
D
1
1.25V
Tigm
C
V
Battery
ign
dac
V
V
Tdsc
1.25 V
I
ign
Drain
Polling
Circuit
C
ds
To
Logic
1
2
Lm
LAMP
P16
Digital
Duty Cycle
101 kHz
Osc
Z2
DRAIN
Lamp
Driver
Circuit
A
Generator
N
D
2
4 MSB
4 LSB
A
10
11
OR2
N
D
3
Lm
LAMP
8-Bit Counter
P256
MUX
GATE
U/D
Counter
Thermal
Limit
Detector
Lamp
Polling
Circuit
Dtl
u/d
Up/Down
Control
Switch
A/D Duty Cycle
Comparator
& Tracking
Circuit
u/d
Current
Limit
Np
Detector
Rs
st
AGND
LRC TEST LRC1
LRC2
GND
Figure 1. 33099 Simplified Internal Block Diagram
33099
2
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1
2
3
4
5
6
7
8
GATE
BAT
16
15
14
13
12
11
10
9
SOURCE
PHASE
NC
GND
LAMP DRAIN
LAMP GATE
IGNITION
LRC2
PHASE FILTER
LRC TEST
NC
REMOTE
AGND
LRC1
TERMINAL FUNCTION DESCRIPTION
Terminal
Name
Terminal
Formal Name
Definition
1
2
3
4
GATE
BAT
Gate Drive
Battery
Controls the GATE of the MOSFET to control the alternator field current.
Primary power connection to the system battery.
Source lamp current and digital ground.
GND
Ground
LAMP
Lamp Drain
Controls the Fault Lamp current.
DRAIN
5
LAMP
GATE
Lamp Gate
Controls the Fault Lamp internal driver as an override function.
6
IGN
Ignition
Controls the ON or OFF function of the regulator.
Inputs for selecting the LRC rate.
7
8
LRC2
LRC1
Load Response Control 2
Load Response Control 1
9
10
AGND
REMOTE
NC
Analog Ground
Remote
Ground connection for analog circuitry.
Provides for external Kelvin connection to system battery.
No internal connection to this terminal.
11, 14
12
No Connect
LRC TEST Load Response Control Test Provides acceleration of LRC rate for testing.
13
PHASE
FILTER
Phase Filter
Provides access to Phase Resistive Divider for External Phase Filter capacitance.
15
16
PHASE
Phase Sense Input
Source
Input for phase voltage.
SOURCE
Coupled to source of MOSFET to provide a GATE voltage reference and to monitor for
source shorts to ground.
33099
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.
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
V
24
40
V
Power Supply Voltage
bat
Load Dump Transient Voltage (Note 1)
Negative Voltage (Note 2)
+V
-V
max
min
-2.5
V
ESD Voltage
V
V
ESD1
ESD2
±2000
±200
Human Body Model (Note 3)
Machine Model (Note 4) (Note 5)
THERMAL RATINGS
T
J
150
°C
°C
°C
Operating Junction Temperature
Operating Ambient Temperature Range
Storage Temperature Range
T
A
-40 to 125
-45 to 150
T
STG
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ TA = 125°C
Thermal Resistance, Junction-to-Ambient
PD
640
85
mW
°C/W
RθJA
Terminal Soldering Temperature (Note 6)
T
220
°C
SOLDER
Notes
1. 125ns wide square wave pulse.
2. Maximum time = 2 minutes.
3. ESD1 testing is performed in accordance with the Human Body Model (C
=100 pF, R
=1500 Ω).
ZAP
ZAP
4. ESD2 testing is performed in accordance with the Machine Model (C
=200 pF, R
=0 Ω).
ZAP
ZAP
5. ESD2 voltage capability of PHASE FILTER terminal is greater than 150 V. All other device terminals are as indicated.
6. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
33099
4
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STATIC ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted.
Characteristic
Regulation Voltage @ 50% Duty Cycle
Symbol
Min
Typ
Max
Unit
V
V
set
14.55
14.3
14.8
14.6
15.05
14.85
V
V
= V or V
set
< V
MC33099
rem
rem
rem
rem
Trem
Trem
= V or V
set
< V
MC33099C
dVset
mV
Regulation Voltage Range
10% < DC < 95%
–
210
300
TC(V
V
)
mV/°C
Regulation Voltage Temperature Coefficient (TC)
= V or V < V
set
-13
0.9
-11
-9
V
rem
bat
rem
Trem
1.25
1.6
V
Power Up/Down IGN Threshold Voltage
Operating Drain Current (Ignition ON)
Tign
mA
I
I
–
–
6.5
6.5
8.0
8.4
V
V
> V
> V
, V
= V = V , TA = 25°C
ph set
Q1(on
)
)
ign
ign
Tign rem
, V
= V = V , -40°C ≤ TA ≤ 125°C
ph set
Q2(on
Tign rem
mA
Standby Drain Current (Ignition OFF)
I
I
–
–
0.6
1.0
1.5
3.4
V
V
< V
, V = 0 V, V
Tign ph
= V
= V
= 12.6 V, TA = 25°C
Q1(off
Q2(off
)
)
ign
ign
rem
rem
bat
bat
< V , V = 0 V, V
Tign ph
= 12.6 V, -40°C ≤ TA ≤ 125°C
V
4.2
4.5
4.0
4.8
V
V
V
Remote Loss Voltage Threshold
T
rem
V
3.75
4.25
Phase Detection Threshold Voltage
Undervoltage Threshold Voltage
T
ph
V
T
uv
10.9
11.35
10.95
11.6
V
V
= 14.8 typical
= 14.6 typical
MC33099
set
set
10.35
11.55
MC33099C
V
V
Overvoltage Threshold Voltage
Tov
16.15
15.8
16.65
16.4
17.15
17.0
V
V
= 14.8 typical
= 14.6 typical
MC33099
set
set
MC33099C
TC(V
V
)
–
-12.4
–
mV/°C
V
Overvoltage Threshold Voltage TC
Load Dump Threshold Voltage
Tov
Tld
18.9
19.25
19.15
19.8
V
V
= 14.8 typical
= 14.6 typical
MC33099
set
set
18.45
19.85
MC33099C
TC(V
V
)
–
-14.3
–
mV/°C
V
Load Dump Threshold Voltage TC
Secondary Regulation
Tld
set2
18.0
18.5
18.8
V
V
= 14.8 typical
= 14.6 typical
MC33099
set
set
17.65
18.15
18.75
MC33099C
TC(V
V
)
2
–
-13.4
–
mV/°C
V
Secondary Regulation TC
Secondary Load Dump Threshold Voltage
set
Tld2
23.5
23.5
24
25
V
V
= 14.8 typical
= 14.6 typical
MC33099
set
set
23.85
24.65
MC33099C
TC(V
)
–
-17.9
–
mV/°C
Secondary Load Dump Threshold Voltage TC
Tld2
33099
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STATIC ELECTRICAL CHARACTERISTICS (continued) TA = 25°C unless otherwise noted.
Characteristic
Lamp Drain Short Circuit Threshold Voltage (Note 7)
Lamp Drain Short Circuit Current
Symbol
Min
Typ
Max
Unit
V
1.8
2.25
2.85
V
Tdsc
I
2.0
2.5
3.0
Amps
V
dsc
V
Lamp Drain ON Voltage
d(sat)
–
–
0.3
48.48
4.6
2.5
55
–
I
= 0.4 A
lamp
V
V
kΩ
°C
µA
µA
V
Lamp Drain-to-GATE Clamping Voltage
Lamp GATE Override Resistance
dg
R
lg
–
T
–
185
300
480
12
–
Lamp Driver Thermal Shutdown Temperature Limit (Note 7)
GATE Drive Source Current
Lim
I
240
400
10
340
560
15
pu
I
GATE Drive Sink Current
pd
V
GATE Drive GATE-to-Source Clamping Voltage
Minimum Charge Pump GATE Drive Voltage
gs
V
V
g(min)
21.5
1.85
23.4
2.3
–
V
= V
= V
source set
bat
V
2.75
V
Source Short Circuit Threshold Voltage
Remote Input Resistance
Tssc
R
kΩ
rem
–
–
68
60
73
45
–
–
V
= V
set
rem
R
kΩ
µA
µA
Phase Input Resistance
= V
ph
V
ph
set
I
IGN Input Pull-Down Current
= 1.25 V
ign
40
35
90
55
V
ign
I
LRC Input Current
= 0 V
lrc
V
lrc
Notes
7. Not 100% tested.
33099
6
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DYNAMIC ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted.
Characteristic
Duty Cycle Regulation Output Frequency
/256
Symbol
Min
Typ
Max
Unit
f
Hz
dc
300
375
49
440
53.8
325
f
osc
44.28
267.5
Hz
Hz
%
f1
Phase Rotation Detection Frequency
Low/High RPM Transition Phase Frequency
GATE Duty Cycle at Startup and WOT
f
296
2
DC
start
30
29
31.25
31.25
3.1
34.5
33.5
3.3
f
> f2
ph
DC
%
%
Minimum GATE LRC Duty Cycle
< f2
(LRC)min
f
ph
DC
min
Minimum GATE Duty Cycle
> V
2.1
V
bat
reg(max)
%/s
LRC Increasing GATE Duty Cycle Rate
Low RPM Mode (f < f2)
ph
R
–
–
–
–
–
9.31
12.45
18.71
37.42
616
–
–
–
–
–
lrc1
LRC1 at GND, LRC2 at GND
LRC1 Open, LRC2 at GND
LRC1 at GND, LRC2 Open
LRC1 Open, LRC2 Open
R
lrc2
R
lrc3
R
lrc4
High RPM Mode (f > f2)
ph
R
lrc(max)
t
–
–
–
–
–
–
–
10.2
98.6
1.56
98.6
1.56
98.6
1.56
–
–
–
–
–
–
–
ms
Hz
%
Ignition Turn OFF Delay (Lamp ON)
Lamp Short Circuit ON Polling Frequency
Lamp Short Circuit ON Duty Cycle
Lamp OFF Polling Frequency
id(off)
f
lsc
DC
l
f
Hz
%
l(off)
DC
Lamp Polling OFF Duty Cycle
l(off)
f
Hz
%
Field Short Circuit ON Polling Frequency
Field Short Circuit Polling ON Duty Cycle
fsc
DC
f
33099
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33099 is specifically designed for regulation of an
The 33099 provides a regulated voltage feedback system to
activate the alternator field current in response to system load
current. The output voltage is monitored by an internal voltage
divider scheme and compared to an internal voltage ramp
referenced to a bandgap voltage. The 33099 regulates the
system voltage to 14.8 V for the DW suffix and to 14.6 V for the
CDW suffix by generating a pulse width modulation (PWM)
voltage waveform at the GATE of an external MOSFET to
provide an average alternator field coil current as a function of
the internal voltage comparison.
automotive system voltage using diode-rectified alternator
charging systems commonly found in automotive applications.
The 33099 provides either an analog or digital duty cycle control
of an ON/OFF ratio of an alternator field current at a fixed
frequency. This provides for a Load Response Control (LRC) of
the alternator field current at low engine RPM to eliminate
engine speed hunting and vibration owing to abrupt torque
loading of the engine when a sudden electrical load is applied
to the system. Four LRC rates are selectable using a
combination of terminals 7 and 8 being connected to ground.
33099
8
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APPLICATIONS
rotating field winding. The system shown in Figure 2 includes
Introduction
an alternator with its associated field coil, stator coils and
rectifiers, an automotive battery, a fault indicator lamp, an
ignition switch, a field flyback diode, and the 33099.
The 33099 is an alternator voltage regulator designed with
internal level shifting resistors to control the voltage in a 12 V
automotive system that uses a three-phase alternator with a
33099
V
Bat
BAT
REMOTE
Remote
V
rem
Charge
Pump
Regulator
CB1
V
rs
V
Internal
DD
V
reg
Regulator
and Bias
Current
FB
0.6 V
LB
RF
V
Bandgap
g
V
V
o
fb
C
V
Reference
rs
l
Low
Pass
V
l
DD
Local
Local
pu
Cf
V
(OTC)
1.25 V
ref
(2.0 V)
(5.0 V)
A
N
D
4
V
S3
ls
GATE
Field
Sens
S1
UV
R4
R5
C
R1
uv
1.25 V
CB2
Min Duty
Cycle
R2
R3
Gate
Polling
Batt
Z1
LD
l
pd
PHASE
V
Tssc
Over
Voltage
Detect
OR1
SOURCE
Css
S2
e
V
OV
hvl
Ign
Delay
PHASE
C
ph
IGN
FILTER
C
IGN
dc
F1
F2
V
DAC
dac
A
N
D
1
1.25V
C
Batt
ign
LAMP
V
CF
Tigm
V
Tdsc
1.25 V
I
DRAIN
ign
Cds
Ignition
Drain
Polling
To
Logic
Lamp
P16
Digital
Duty Cycle
Generator
Z2
Lamp
Driver
Circuit
A
500
LAMP
GATE
N
D
2
4MSB
4 LSB
Osc
A
OR2
N
D
3
mp
8-Bit Counter
MUX
P 256
U/D
Counter
Lamp
Polling
Thermal
Limit
Dtl
u/d
Up/Down
Control
Switch
A/D
u/d
Comparator
& Tracking
Current
Limit
Np
Battery
Rs
Stator
LCR Test
LCR1 LRC2
Gnd
LCR TEST
LCR1 LCR2
GND
AGND
Alternate S tator
Configuration
Ground
Boundry for IC
Remote
Phase
Figure 2. 33099 Simplified Application
The 12 V system voltage (V ) is connected to a REMOTE
bat
terminal is provided for externally providing a filter capacitance
for filtering phase input noise.
input by a remote wire, which provides the IC regulator with an
external Kelvin connection directly to the battery to provide
REMOTE voltage, Vrem. The system voltage at the BAT
The regulated DC system set voltage (Vset) is achieved by
employing feedback to compare a ratioed value of Vset to an
terminal is also sensed by an internal Local IC connection as
Local voltage Vl. The Local connection is provided in the event
internal IC bandgap voltage reference having a negative
temperature coefficient (TC). The GATE drive of an external
N-channel MOSFET is regulated by the IC to control the field
current in the alternator field coil as an alternating ON or OFF
state dependent on load current conditions affecting voltage
the remote wire or remote connection becomes faulty such as
being resistive, an open, or shorted to ground.
The PHASE input is normally connected to a tap on one
corner of the alternator's stator winding, which provides an AC
phase voltage (Vph) for the IC to determine the rotational
V
set. The external MOSFET receives GATE-to-source voltage
drive from between the GATE and SOURCE output terminals of
the IC. The GATE-to-source voltage is a Pulse Width
frequency (fph) of the alternator rotor. Two frequency
Modulated (PWM) waveform having a variable ON/OFF duty
cycle ratio that is determined by an analog or a digital duty cycle
control circuitry that responds to variations in the system
voltage due to variations in system load current. The PWM
comparators (F1 and F2) monitor voltage Vph to determine a
phase rotation detection frequency (f1) and a Low/High RPM
transition phase frequency (f2), respectively. A PHASE FILTER
33099
9
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waveform has a duty cycle regulation output frequency of about
During a system load dump condition, load dump protection
circuitry prevents GATE-to-source drive to the external
MOSFET and to the internal lamp drive MOSFET. This ensures
that neither the field current nor the lamp current is activated
during load dump conditions. A drain-to-GATE voltage clamp is
also provided for the internal lamp driver for further protection of
this driver during load dump.
395 Hz (fdc) defined by an 8-bit division of an internal 101 kHz
oscillator clock frequency (fosc). The GATE voltage at the GATE
terminal is due to a charge pump GATE voltage (Vg) generated
by voltage multiplication using an internal charge pump voltage
regulator. The high GATE-to-source voltage applied to the
external MOSFET during the ON cycle of the PWM waveform
minimizes a low drain-to-source ON resistance (RDS(ON)) and
An ignition terminal (IGN) is provided to activate the regulator
from the standby mode into a normal operating mode when the
associated drain-to-source voltage Vd(SAT) to maximize the field
ignition switch is ON and an ignition voltage (V ) is greater
current while minimizing the associated power dissipation in the
MOSFET.
ign
than a power up/down ignition threshold voltage (V
). When
Tign
the ignition switch is OFF, voltage V is less than voltage
ign
A unique feature of the 33099 is the combinational use of
analog and digital duty cycle controllers to provide a Load
Response Control (LRC) duty cycle function when rotor
frequency fph is less than frequency f2. A classic analog duty
V
, and the regulator is switched into a low current standby
Tign
mode, when frequency f < f . The IGN terminal can either be
ph
1
coupled to the low side of the ignition switch or to the low side
of the lamp. When the IGN terminal is connected to the low side
of the lamp, the lamp must be shunted by a resistor to ensure
that ignition ON is sensed, even with an OPEN lamp fault
condition. When the lamp in ON, lamp current is polled OFF
periodically at an ignition polling frequency in order for the IGN
terminal to periodically sense that the ignition voltage is high
even though the lamp is ON. An ignition input pull-down current
(I ) is provided to pull voltage V to ground when the IGN
cycle function is provided at the GATE output when frequency
fph is greater than frequency f2. During the LRC mode when f1
< fph < f2, a sudden decrease in the system voltage due to a
sudden increase in system load current will cause the analog
duty cycle to rapidly increase to as great as 100%. However,
the LRC circuitry causes the digital duty cycle to increase to
100% at a controlled predetermined LRC rate and overrides the
analog duty cycle. Thus the alternator response time is
decreased in the LRC mode and prevents the alternator from
placing a sudden high torque load on the automobile engine
during this slow RPM mode. This can occur when a high current
accessory is switched on to the 12 V system, producing a
sudden drop in system voltage. When frequency fph is greater
ign
ign
terminal is OPEN or terminated on a high resistance.
Two ground terminals are provided by the 33099 to separate
sensitive analog circuit ground (AGND) from noisy digital and
high-current ground (GND).
than frequency f2, the slow LRC response is not in effect and
Alternator Regulator Biasing and Power Up/Down
the analog duty cycle controller controls the PWM voltage
waveform applied to the external MOSFET to regulate the
system voltage. By selectively coupling the LRC1 and LRC2
terminals to ground or leaving them open, the user can program
The biasing of the regulator is derived from the BAT terminal
voltage V . In the normal operating mode when the ignition
bat
switch is ON and voltage V is greater than V
(about
ign
Tign
four different LRC rates (R -R ) from 9.37%/sec to 37.4%/
lrc1 lrc4
1.25 V), a 5.0 V VDD voltage regulator biases the IC logic and
sec. During an initial ignition ON and engine start-up, the LRC
rate is also in effect to minimize alternator torque loading on the
engine during start, even when a Wide Open Throttle (WOT)
condition (fph > f2) occurs.
provides bias to a bandgap shunt voltage regulator. The
bandgap regulator maintains a reference voltage (V ) of
ref
approximately 2.0 V with an internal negative temperature
coefficient (-TC) as well as a 1.25 V Zero Temperature
Coefficient (OTC) reference voltage. Additional bias currents
and reference voltages, including a charge pump GATE voltage
V , are also generated from voltage V . The typically ignition
An internal N-Channel MOSFET is provided on the IC to
directly drive lamp current as a fault indicator. The fault lamp is
connected between the low side of the ignition switch and the
LAMP DRAIN terminal of the IC. A fault is indicated during an
undervoltage battery condition when frequency fph is greater
g
bat
ON drain current (I
) is about 6.5 mA at 25°C. When the
Q1(on)
ignition switch is OFF and voltage V is less than V
, the
Tign
ign
than frequency f2, during an overvoltage battery condition, and
when frequency fph is less than frequency f1. Frequency fph < f1
regulator is in a low current standby mode, having a standby
drain current of about 0.7 mA (I ) at 25°C. During the
Q1(off)
when an insufficient alternator output voltage results or a slow
or non-rotating rotor occurs due to a slipping or broken belt. An
external LAMP GATE terminal is also provided for the internal
lamp driver to allow the user to override the internal IC fault logic
and externally drive the internal lamp drive MOSFET.
sleep mode, some internal voltage regulators and bias currents
are either terminated or minimized. However, the VDD regulator
and the bandgap voltage regulator continue to maintain
voltages VDD for the logic, the 2.0 V V , and the 1.25 V
ref
reference voltage. In addition, all logic is reset in the standby
mode.
When a loose wire or battery terminal corrosion causes the
Remote voltage to decrease but is not a Remote Open
condition, the system voltage will increase, causing an
overvoltage Lamp fault indication, and is regulated at a
secondary value of about 18.5 V.
After switching the ignition switch to the ON position, voltage
V
will exceed voltage V
, causing comparator C to
ign
Tign ign
switch states, providing an ignition-ON signal to the Ignition
Delay circuit. After an Ignition start Delay Time of 500 ms, the
Ignition Delay circuit activates additional current for the VDD
33099
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regulator and activates all other voltage regulators and bias
buffered and coupled to the output of a unity-gain Local Buffer
(LB) and ratioed by the R5/(R4+R5) resistor divider to provide
an input voltage to a unity-gain combiner/buffer CB2. Thus the
currents. After engine start, the LRC mode is activated,
independent of the phase frequency or independent of a Wide
Open Throttle condition. When the battery system voltage
voltage at the input of the combiner CB2 is normally 0.8 V (or
ls
increases to V , the regulator resumes the normal operational
1.6 V typically), while voltage V on the input of CB1 is typically
rs
2.0 V. Because voltage V reflects the highest voltage at the
o
set
mode. After switching the ignition switch to the OFF position,
voltage V decreases below voltage V
, causing the
ign
Tign
input of either combiner, voltage V will be voltage V in
o
rs
comparator C to provide an ignition-OFF signal to the Ignition
ign
Remote operation with Remote connected to V . For this
bat
case, voltage V is filtered by a 300 Hz low-pass filter and
rs
translated to the FB buffer output. Voltage V at the FB buffer
rs
output is then compared to a digital-to-analog converter output
Delay Circuit. After phase frequency f < f due to ignition turn
ph
1
OFF, supply currents and voltages are reduced in the regulator
to provide the standby drain current drain. However, voltage
V
DD for logic and voltage V for reference voltages remain
ref
voltage ramp (V ) for duty cycle regulation.
dac
active to be able to sense an ignition input voltage.
During a Remote fault condition when the remote sense line
In some applications, the ignition input is connected to the
low side of the fault lamp as shown in Figure 2, page 9. When
the lamp driver circuitry is generating a lamp ON signal, a lamp
polling signal causes the Lamp Drain output to be periodically
is OPEN or grounded, voltage V at the Remote Sense input
rs
will be zero, causing comparator C to activate switches S1
rs
and S2 to a CLOSED position. As a result, voltage V is
ls
GATED OFF. As a result, voltage V > V
during the lamp
coupled through buffer LB directly to the input of combiner CB2.
ign
Tign
OFF polling period, causing comparator C to periodically
ign
Because the voltage V on the input of combiner CB2 is greater
ls
provides an ignition-ON signal to the Ignition Delay Circuit.
During the Lamp On condition, the Ignition Delay Circuit
than voltage V (= 0 V) on the input of combiner CB1, voltage
rs
V
is coupled to the output of the combiners as voltage V .
o
ls
provides a minimum ignition turn-off delay (t
) such that all
id(off)
Thus in this fault case, voltage V is filtered and translated to
ls
the FB buffer output for being compared to voltage ramp V
dac
for regulation.
currents and regulator voltages remain ON between the Lamp
Off polling pulses.
During a remote fault condition in which the resistance of the
Remote sense wire increases due to the corrosion or a loose
connection, a finite external remote fault resistance occurs
Battery and Alternator Output Voltage Sensing
The system battery voltage is directly sensed by the
REMOTE input using a remote wire as a Kelvin connection. The
causing voltage V
to decrease, but voltage V
remains
rem
rem
Remote input resistance (R ) at the REMOTE input is
rem
greater than voltage V
. As a result, switches S1 and S2
Trem
typically 68 kΩ. The voltage at the Remote Sense input (V ) is
rs
remain in an OPEN condition, while the system voltage will
increase due to the effective increase in the Remote resistor
a ratioed value of the Remote voltage (V ). The intended
rem
ratio of V /V is about 7.45. The BAT terminal voltage (V
)
bat
divider ratio. As a result, voltage V increases until the voltage
rem rs
l
is also sensed as an internal Local voltage (V ). A Local Sense
l
at the input of combiner CB2 is approximately 2.0 V, or V is
ls
voltage (V ) is a ratioed value of voltage V , where the intended
about 1.2 (2.0 V), or 2.25 V due to the R4/R5 divider ratio.
Because the local divider ratio translates voltage V to V by
ls
l
ratio of V /V is also 7.45. The Local internal connection is
ls
bat
l
ls
about factor 7.4, the final regulated output voltage for this
condition is 7.4 (2.25), or 18.5 V. This is the secondary
provided for fault protection against the remote wire being
grounded or exhibiting a high remote wire resistance due to
being disconnected or due to a corrosive or loose connection.
Thus the Local connection ensures that alternator regulation of
the system voltage continues in well-defined states for all
possible Remote input fault conditions.
regulation voltage (V
). When the system voltage increases
set2
to the Overvoltage Threshold (V ), a fault indication occurs
Tov
by the lamp. Thus this particular Remote fault condition
produces a fault indication, but regulates to prevent an extreme
system overvoltage condition. When the Remote fault
resistance becomes great enough to cause voltage
Local and Remote Voltage Processing and Switching
V
< V
, the regulated system voltage returns to the local
rem
Trem
During Remote operation both the external Remote input
connection and internal Local connection senses approximately
regulation as described for an OPEN or grounded Remote
input.
the same regulated system voltage of V = 14.8 V. For this
set
case, voltages V and V are approximately 2.0 V. Because
rs
ls
Internal Clock Oscillator and 8-Bit Counter
the remote switching comparator C is referenced to 0.6 V,
rs
An internal clock oscillator is provided having a typical
both switches S1 and S2 are OPEN and remain open when
oscillation frequency (f ) of 101 kHz. The output of the
voltage V > 0.6 V or when voltage V
is greater than the
osc
rs
rem
oscillator is coupled to an 8-bit counter that provides 8 counting
bits to the logic and the four most significant counting bits
(MSB) to the LRC circuitry and to a digital-to-analog converter
remote loss threshold voltage (V
). Voltage V is coupled
rs
Trem
to the input of a unity-gain combiner/buffer CB1. Voltage V is
ls
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(DAC) waveform generator. The output MSB frequency (f
)
current is also fully OFF when the system voltage is greater
than 7.45 (V ), or 14.9 V. When voltage V is less than any
msb
of the 8-bit divider is about 395 Hz (f
= f
/256), which
osc
ref
fb
msb
portion of the DAC waveform voltage, comparator C output is
dc
high to produce an ON field current. When voltage V is greater
fb
determines the PWM frequency at the GATE output. An
external LRC TEST terminal is provided for accelerating
internal testing of the LRC function and logic. Under normal
operation, the LRC TEST terminal is grounded by an internal
than any portion of the DAC waveform voltage, comparator C
dc
output is low to produce an OFF field current. Thus the system
feedback will regulate the PWM duty cycle of the field current
from 0% to 100% over about a 210 mV system regulation
voltage range (dVreg). The system voltage is centered at
14.8 V, where a 50% duty cycle field current results for an
average system load current, and the duty cycle regulation
frequency is (f /256), or 395 Hz. Since voltage V has a
10 kΩ resistance to ground. Under accelerated test conditions,
the LRC TEST voltage is 5.0 V, and a fourth bit (f /16) from
osc
the 8-bit divider is used to determine the PWM GATE
frequency. Thus, the rates are accelerated by a factor of 16.
Low-Pass Filter, DAC, and Analog Duty Cycle
Regulator Comparator
osc
ref
negative TC, voltage V will also have a regulation voltage
set
temperature coefficient (TC
) of about -11 mV/°C.
Vreg
The output voltage V of combiners CB1 and CB2 is coupled
o
to an input of a 300 Hz low-pass filter (Rf, Cf) to remove high-
Input Phase and Frequency Switch Response
frequency components of system noise at V
and thus
bat
associated with voltages V , or V . The output of the low-pass
ls
rs
The phase voltage V results from the alternator's stator AC
ph
output voltage being applied to the PHASE input terminal.
filter is coupled to a unity-gain buffer FB that provides a filter
buffer FB output.
A phase detection threshold voltage (V
) is approximately
Tph
4.0 V due to the 1.25 V phase reference voltage for the phase
The 4 MSBs of the 8-bit counter causes the DAC to generate
a 4-bit 395 Hz voltage waveform having 16 descending
1.75 mV steps, ramping from V to [V - 28 mV], where V
comparator (C ) and the 3.22 voltage ratio associated with the
ph
phase input resistor divider. The phase input resistance (R ) is
ph
ref
ref
ref
is the 2.0 V reference voltage.
typically 60 kΩ. A PHASE FILTER terminal is coupled to the
input of Comparator C , providing for an external phase filter
ph
An analog duty cycle comparator (C ) compares the DAC
dc
output voltage waveform to the voltage at the FB output (V ).
fb
capacitance when filtering of high frequency phase noise is
desired. A typical value of .003 µF to AGND provides for an
input phase 3.0 db roll-off frequency of about 10 kHz.
When voltage V is less then voltage [V - 28 mV],
fb
ref
comparator C outputs a logic [1], for a 100% duty cycle.
dc
Comparator C also provides about 480 mV of hysteresis at
ph
When voltage V is greater than V , comparator C outputs
the PHASE input terminal. Comparator C further provides a
ph
fb
ref
dc
a logic [0] for a 0% duty cycle. When (V - 28 mV) < V < V ,
ref
phase signal binary output voltage having a phase frequency of
ref
fb
comparator C outputs a duty cycle defined by the High/Low
dc
f
and is applied to digital frequency switches F1 and F2.
ph
output voltage ratio for each period (about 2.54 ms) of the DAC
output voltage waveform.
Switch F1 outputs a logic [1] when frequency f is less then
ph
phase detection frequency f . Frequency f is equal to
1
1
frequency f
/8, or 49.3 Hz for a 101 kHz oscillator frequency.
msb
Basic System Voltage Regulation
Switch F2 outputs a logic [1] when the frequency f is greater
ph
then the low/high transition frequency f . Frequency f2 is equal
2
From a system voltage regulation viewpoint, the voltages
V
and V from the Remote or Local connections,
to frequency 3f
/4, or 296 Hz for a 101 kHz oscillator
rem
l
msb
respectively, are scaled to the Remote Sense and Local Sense
inputs as voltages V and V respectively and transferred to
frequency. These frequency switches are used to define the
Load Response Control region of operation, an undervoltage at
a high RPM fault condition, and a low RPM fault condition due
to a broken or loose belt.
rs
ls
the FB output as voltage V . Voltage V is compared to the
fb
fb
DAC output voltage waveform to generate the ON and OFF
time of the analog duty cycle waveform. When voltage V is
fb
Load Response Control (LRC)
less than V - 28 mV, the output of comparator C is in a high
ref
dc
state. This high state propagates through an AND3 GATE, an
OR1 GATE, and an AND4 GATE to activate switch S3,
generating a fully ON or High GATE drive voltage. When
voltage V is greater than V , the output of comparator C is
The LRC circuit consists of a digital duty cycle generator, an
analog/digital (A/D) duty cycle comparator and tracking circuit,
an up/down control switch, an up/down (U/D) counter, a
programmable divider (Np), and a multiplexer (MUX). During
normal operation, the LRC circuit becomes active and
generates digital duty cycle control of the GATE drive when
fb
ref
dc
in a low state. This low state propagates through the AND3
GATE, the OR1 GATE, and the AND4 GATE to activate switch
S3 to generate a fully OFF or low GATE drive voltage.
Assuming voltage V is 2.0 V and V = V , and the local or
frequency f is less than frequency f (f < f < f ). The slow
ph
2
1
ph
2
LRC response becomes inactive and the analog duty cycle
controls the GATE drive when frequency fph is greater than
ref
fb
rs
remote input resistive scale factor is 7.45, the external
MOSFET provides a fully ON field current when the system
frequency f (f < f < f ). During initial ignition and initial
2
1
ph
2
voltage is less than 7.45 (V - 28 mV), or 14.6 V. The field
ref
33099
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engine start, the LRC response is in effect, independent of
frequency f , until system voltage is regulating at voltage V
terminations. For a down state on the u/d line, the digital duty
cycle will count down at a rate of about 10 ms/step change.
.
set
ph
The A/D duty cycle comparator and tracking circuit receives
the analog duty cycle from comparator C and the digital duty
dc
cycle from the MUX output. The A/D duty cycle comparator
provides a high, or up (u), output when the analog duty cycle is
greater than the digital duty cycle, and a low, or down (d), output
when the analog duty cycle is less than the digital duty cycle.
The digital duty cycle generator receives the 4 MSBs from
the 8-bit counter as input and generates 11 discrete digital duty
cycles on 11 output lines. The frequency of each duty cycle
waveform is about 395 Hz (f
), which results from the MSB
msb
of the 8-bit division of the 101 kHz OSC clock frequency. The
minimum duty cycle on the first output line is 31.25% and the
maximum duty cycle on the eleventh output line is 93.75%. The
duty cycle difference between each incremental duty cycle is
6.25%. All 11 duty cycle generator output lines are coupled as
data inputs to the MUX.
In the LRC mode when frequency f < f < f , the up/down
1
ph
2
control switch enables the u/d output of the A/D duty cycle
comparator to be coupled to the u/d line. In the steady state, the
A/D duty cycle comparator will provide an u/d input to the U/D
counter and Np divider to increase or decrease the digital duty
cycle to track the analog duty cycle. If the analog duty cycle
increases to a value greater than the digital duty cycle at a rate
that is greater than the selected LRC digital duty cycle rate, the
A/D duty cycle comparator will output an up signal on the
u/d line to cause the digital duty cycle to increase to the analog
duty cycle at the selected LRC digital duty cycle rate. If the
analog duty cycle decreases to a value less than the digital duty
cycle, the A/D duty cycle comparator will output a down signal
on the u/d line to cause the digital duty cycle to decrease to the
analog duty cycle at a fixed rate of about 10 ms/step. For an
analog duty cycle less than 31.25%, the down count at the
output of the U/D counter will remain at 0 and the digital duty
cycle will remain at 31.25%.
Normally the programmable divider Np divides frequency
f
by a counter divide ratio N and applies the f
/N
msb
msb
frequency as input to the U/D counter. Divide ratio N can be pre-
selected by the user for four different divide ratios by switching
a combination of the LRC1 and LRC2 normally open terminals
to ground. An LRC input current (I ) from each LRC terminal to
lrc
ground is about 45 µA. The phase frequency f and an up/
ph
down (u/d) state on a u/d line from the up/down control switch
determines ratio N. In the LRC mode when f < f , a high, or
ph
2
up, state on the u/d line causes divider Np to output a frequency
of f /N, or 395 Hz/N. The LRC1 and LRC2 terminal
msb
combinations produce N divide ratios of 66, 132, 198, and 264.
When the u/d line is in the down, or low, state, divider Np
provides a divide ratio of f
/4, or 395 Hz/4. When f > f2, the
msb
ph
If frequency f is less than frequency f (f < f ), then the
ph
1
ph
1
output frequency of divider Np is always f
/4 = 395 Hz/4,
msb
up/down control switch will provide a down signal on the u/d line
independent of the duty cycle comparator u/d output. The
resulting down count of 0 to the MUX control input for f < f
independent of the state of the u/d input line.
The u/d line from the up/down control switch determines the
direction of the count as well as the divide ratio N. For an up
state on the u/d line, the output of the 4-bit U/D counter
increments up at a rate of 5.98 Hz (count change every 167 ms)
for N=66, 2.99 Hz (count change every 334 ms) for N=132,
1.99 Hz (count change every 502 ms) for N =198, or 1.496 Hz
(count change every 671 ms) for N=264. For a down state on
the u/d line, the output of the 4-bit U/D counter decrements at a
rate of about 99 Hz (count decrement about every 10 ms). The
4-bit output lines of the up/down counter are coupled as control
inputs of the MUX.
ph
1
will cause the digital duty cycle to be constant at 31.25% and
provides a divide ratio of f
/4 as the input frequency to the
msb
U/D counter.
When approximately 5.0 V is applied to the LRC TEST
terminal, divider Np utilizes the f /16 frequency as input to the
osc
divider instead of the normal f /256 frequency. As a result,
osc
the LRC function is accelerated by a factor of 16, which allows
the testing of all LRC associated rates to be accelerated by a
factor of 16. During normal LRC operation, the LRC terminal is
in a low ground state, having an internal 10 kΩ pull-down
resistor.
The MUX couples one of the 11 digital duty cycle input lines
to the MUX output dependent upon the 4-bit control inputs from
the U/D counter. When the MUX control input count is 0, the first
31.25% digital duty cycle is selected and provided at the MUX
output. When the control input count is 10, the eleventh 93.75%
digital duty cycle is selected at output of the MUX. A MUX
control input of 11 produces a 100% duty cycle at the MUX
output. Thus each of the MUX input lines is selected and
provided at the MUX output and incremented to the next line at
a rate dependent on the rate the MUX control inputs increment.
For an up state on the u/d line, the digital duty cycle at the
output of the MUX will increment from 31.24% to 100% in
The duty cycle output of the AND3 GATE reflects the
minimum duty cycle at the AND3 GATE inputs. Thus when the
analog duty cycle exceeds the digital duty cycle, the digital duty
cycle becomes the controlling duty cycle at the AND3 GATE
output. When the analog duty cycle is less than the digital duty
cycle, the analog duty cycle becomes the controlling duty cycle
at the AND3 GATE output. Thus in the LRC mode when
f < f < f , an increasing step response in the analog duty
1
ph
2
cycle from 0% to 100% will cause the duty cycle at the output of
the AND3 GATE to increase rapidly from 0% to 31.25% and
then increase slowly at the LRC rate from 31.25% to 100%. If
the analog duty cycle provides a step increase from a duty cycle
greater than 31.25%, then the resulting LRC duty cycle
increase from the initial analog duty cycle at the output of the
11 steps at a rate from 167 ms/step (or a fourth LRC rate (R
)
lrc4
of 37.42%/sec) to 671 ms/step (or a first LRC rate (R ) of
lrc1
9.31%/sec) dependent on the LRC1 and LRC2 terminal
33099
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AND3 GATE. For a decreasing step response in the analog
duty cycle, the output of the AND3 GATE will rapidly follow the
decreasing analog duty cycle. The output of the AND3 GATE
drives the GATE output (and the field current) through an OR1
GATE, an AND4 GATE, and switch S3. Thus the minimum
switch S3 to couple a GATE drive pull-down sink current (I ) to
pd
the GATE output. Current I pulls the GATE voltage to the
pd
Source voltage, turning OFF the MOSFET and its associated
field coil current. The limited GATE current drive of the
MOSFET GATE capacitance reduces the magnitude and
frequency of the high-frequency components associated with
the GATE duty cycle waveform, minimizing RFI. Zener diode Z1
is employed to provide a GATE-to-Source clamping voltage
GATE LRC duty cycle (DC
) is 31.25%.
(LRC)min
A 0% analog duty cycle will produce a 0% duty cycle at the
output of the AND3 GATE. However, the output of the AND3
GATE is ORed with a 3.1% minimum duty cycle signal from the
minimum duty cycle generation at the OR1 GATE input to
provide a minimum 3.1% duty cycle to the AND4 GATE input.
(V ), which limits and protects the GATE-to-Source voltage of
gs
the external MOSFET.
When the external MOSFET fails to increase the source (or
field coil terminal) voltage to within a source short circuit
This provides the resulting minimum GATE duty cycle (DC
)
min
of 3.1% at the GATE output, even though the analog duty cycle
is 0%.
threshold voltage (V
) of the BATTERY terminal voltage
Tssc
(V
< [V
- V
]), a shorted-source comparator C
source ss
Tssc
bat
When the phase frequency is greater than frequency
outputs a short circuit signal to a GATE polling circuit. A shorted
field coil to ground is an example of this fault condition. This
GATE polling circuit provides short GATE polling pulses to the
AND4 GATE to allow the IC to test for an unshorted condition
without damaging the external MOSFET. The polling duty cycle
f (f > f ), the N divide factor is reduced to 4. As a result, the
2
ph
2
LRC circuitry still functions as previously described, but the rate
of digital duty cycle increase or decrease is a maximum LRC
rate (R
) of about 10 ms/step. Thus a step increase in the
lrc(max)
is 1.56%, or about a 158 µs ON pulse at a frequency of f
/4,
msb
analog duty cycle from 31.25% to 100% will cause about a
110 ms delay before the digital duty cycle provides a 100% duty
cycle at the output of the AND3 GATE (and GATE drive).
or 98.6 Hz. When the source shorting condition is removed,
comparator Css provides a no-short signal to the GATE polling
circuitry, which provides a logic [1] to the AND4 GATE, which
then operates normally.
The conditions for LRC response also occur during an initial
engine start up period after engine cranking even when a WOT
condition occurs (f > f ). When the ignition switch is turned
The AND4 GATE is also driven by the no load dump (LD) line
from the Overvoltage Detector circuitry. Thus during a load
dump system overvoltage condition, a logic [0] is provided to
the AND4 GATE from the Overvoltage Detector circuit and all
GATE drive is terminated.
ph
2
ON, comparator C is activated, activating all biasing into the
ign
normal state and activating the start-up LRC mode. After engine
cranking and immediately after initial engine start up, the
system BATTERY voltage is generally low while a WOT
condition occurs. For this case, the slow LRC response is in
effect to prevent excessive torque loading on the engine by the
alternator during engine start up. The GATE duty cycle at start-
A flyback diode MR850 is externally provided to limit the
negative source voltage on the field terminal (and the SOURCE
terminal) caused by a turn-OFF transition of the field current.
The forward current through this diode is approximately the
peak field current prior to field current turn OFF.
up with WOT (DC
) is the minimum LRC duty cycle and will
start
increase at the LRC rate. Once the system voltage returns to
voltage V , the normal LRC response will occur as previously
set
described.
Fault Lamp Indicator—Drive and Protection
The fault indicator lamp is driven by an internal N-channel
MOSFET lamp driver, which controls the lamp current. The
lamp is coupled between the ignition switch and the LAMP
DRAIN terminal of the lamp driver. The Lamp GATE of the lamp
driver is driven by the lamp driver circuitry or from an external
LAMP GATE terminal. Inputs to the lamp driver circuitry are
from an output of an AND2 GATE, an output of a thermal limit
circuit, and an output of a current limit circuit. By applying an
Field Coil Drive and Device Protection
The external MOSFET provides PWM drive current from the
system BATTERY to the field coil for system voltage regulation.
The GATE-to-Source voltage for this MOSFET is provided by
the IC's GATE-to-SOURCE terminal drive voltage. During the
ON state, the AND4 GATE activates switch S3 to couple the
GATE drive pull-up source current (I ) to the GATE output.
pu
external Lamp GATE override voltage (V ) to the LAMP GATE
go
Current I drives the GATE of the MOSFET to the charge
pu
terminal (5), the Lamp Drain current will increase, providing
lamp current independent of the lamp driver logic state. When
the lamp driver circuity is forcing the lamp driver OFF, the LAMP
GATE terminal resistance to ground will be about 4.6 kΩ. The
source of the lamp driver is coupled to ground through an
internal current sense resistor RS. When the lamp is ON, the
pump GATE voltage Vg (typically 23 V), causing the MOSFET
to drive the field coil terminal to near the system BATTERY
voltage. Voltage V has a minimum charge pump GATE voltage
g
(V
) of 21.5 V. This high GATE-to-Source voltage
g(min)
minimizes power dissipation in the external MOSFET by
minimizing a Drain-to-Source ON resistance (RDS(ON)) of the
Lamp Drain ON voltage (V
) is the Lamp Drain-to-ground
d(sat)
MOSFET during the ON state. This results in a typical Lamp
voltage measured at 400 mA of Lamp Drain current.
Drain ON voltage (V
) of about 0.3 V at a Lamp Drain
d(sat)
Normally, current flows through the lamp driver (and lamp),
indicating a fault when the output of the AND2 GATE is a
logic [1]. Assuming the lamp is not shorted, is not being current
current of 400 mA as measured from the LAMP DRAIN terminal
to ground. During the OFF state, the AND4 GATE activates
33099
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limited, is not in the thermal shut down mode, and the system is
Undervoltage, Overvoltage, and Load Dump
Protection
not in a load dump mode, the lamp ON current is controlled by
the output of the OR2 GATE. The output of the OR2 GATE is a
logic [1] and the lamp will normally be ON when the UV
(undervoltage) line and the F2 output line are both a logic [1]
state, indicating an undervoltage condition when frequency
An undervoltage, overvoltage and load dump condition is
sensed by the regulator to generate fault indications and to
protect the regulator and associated external devices. As
previously discussed, a load dump signal during load dump will
prevent GATE drive to the external MOSFET and prevent
GATE drive to the lamp driver. Thus the external and internal
MOSFETs will turn OFF during a system load dump. As
previously discussed, the undervoltage and overvoltage signals
are also provided for fault indications.
f
> f . The output of the OR2 GATE is also a logic [1] when
ph
2
the output of the OV (overvoltage) line is a logic [1], indicating
an overvoltage condition, or the output of the F1 line is also a
logic [1], indicating a loss of phase signal (f < f ) due to a
ph
1
broken phase wire, broken or slipping belt, or otherwise failed
alternator or open field circuit.
The undervoltage signal is provided on the UV line by an
When the lamp current exceeds a lamp drain short circuit
undervoltage comparator C having a voltage reference of
uv
current (I ), the voltage across resistor Rs will exceed a
dsc
1.25 V and a resistor divider voltage transfer of 1.26 from the
current limit threshold voltage associated with the current limit
circuitry. As a result, a signal is sent to the lamp driver circuitry
to limit the lamp drive and regulates the lamp current to current
FB output to comparator C input. When voltage Vfb on the FB
uv
output becomes less than 1.52 V, the voltage at input to
comparator C becomes less than 1.25 V, causing comparator
uv
I
. When the power dissipation of the lamp driver causes the
dsc
C
to output an undervoltage UV signal. Because voltage V
fb
uv
temperature of the lamp driver to exceed a thermal shut-down
temperature limit (T ), a temperature sensing diode (D )
is ideally voltage V (or voltage V ), and the ratio of V /V
rs
rs
ls
r
Lim
tl
(or V /V ) is 7.45, the UV signal will occur when the system
l
ls
causes the thermal limit circuitry to send a signal to the lamp
driver circuitry to limit the lamp drive current and reduce the
power dissipation and resulting device temperature. When the
lamp driver is ON, but the Lamp Drain terminal voltage is not
voltage at the Remote input (or Local input) is less than an
undervoltage threshold voltage (V ), or 11.35 V. However,
Tuv
GATE AND1 ensures that frequency f must be greater than f
ph
before an undervoltage Fault is indicated by the lamp.
2
below the BAT terminal voltage V
by at least a lamp drain
bat
short circuit threshold voltage (V
) or ([V - V ] <
drain
Tdsc
bat
The load dump and overvoltage detection also utilizes similar
resistor dividers and voltage comparators in an Overvoltage
Detect circuitry where all comparators are referenced to voltage
VTdsc), comparator C will output a lamp short circuit signal to
ds
the Drain Polling circuit to indicate a lamp shorted condition.
The Drain Polling circuit provides a low duty cycle polling output
to the input of the AND2 GATE to poll the lamp driver ON,
continuously testing for a lamp short without damaging the lamp
driver. The polling duty cycle is 1.56%, (or about a 158 µs ON
V
, or about 2.0 V. When voltage V on the FB output is
ref
fb
greater than 2.58 V, or 1.29 V (V /V = 1.29), an output
ref fb ref
load dump signal of a logic [0] is generated on the LD line. Thus
during load dump, voltage V (or V
) will be about 2.58 V,
rs
local
pulse) at a frequency of f
/4, or 98.6 Hz. After the lamp short
msb
and the actual load dump threshold voltage (V ) will be about
Tld
has been removed, the comparator C outputs a lamp not-
ds
shorted signal to the Drain Polling circuitry, which provides a
logic [1] to the AND2 GATE, which then operates normally.
19.25 V, or 1.3 V . When voltage V on the FB output is
set
fb
greater than 1.117 V (V /V = 1.117), an output
ref fb ref
overvoltage signal is generated on the OV line. Thus voltage
Lamp polling is also present when the lamp is ON. In this
case, lamp polling turns OFF the lamp for a short period of time
with the lamp being ON for the remainder of the time. In this
case the lamp ON duty cycle is 98.44% (or OFF for 158 µs) at
V
(or V ) will be about 2.235 V, and the actual overvoltage
rs
l
threshold voltage (V ) will be about 16.65 V, or 1.125 V
.
set
Tov
The regulator also indicates an overvoltage condition on the
system during the Remote fault condition when the remote wire
resistance increases to a finite value and the system voltage is
a frequency of f
/4, or 98.6 Hz. This causes the lamp voltage
msb
on the lamp drain terminal to be greater than ignition threshold
voltage V for at least 158 µs of a 10.1 ms period. During the
Tign
being regulated by secondary regulation at V
. When a load
set2
lamp ON mode, the Ignition Turn Off Delay of the Ignition Delay
circuit is greater then the 10.1 ms period. As a result, the
regulator biasing remains ON even when the IGN terminal is
coupled to the LAMP DRAIN terminal and the lamp drain
dump occurs during secondary regulation, the load dump
threshold increases to 1.3 V , or about 24 V.
set2
voltage is less than voltage V n most of the time when the
Tig
lamp is ON.
The lamp driver is also protected from load dump, since
during load dump, the LD signal is a logic [0], preventing the
AND2 GATE from activating the lamp driver. In addition, a
drain-to-GATE clamp device Z2 limits the drain-to-GATE
clamping voltage (V ) to about 40 V typically.
dg
33099
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PACKAGE DIMENSIONS
.
DW SUFFIX
16-TERMINAL SOICW
PLASTIC PACKAGE
CASE 751G-04
ISSUE D
M
0.25
B
2.65
2.35
A
0.25
0.10
10.55
8X 10.05
PIN'S
NUMBER
0.49
0.35
16X
6
M
0.25
T A B
1
16
PIN 1 INDEX
14X
10.45
10.15
1.27
4
A
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS A AND B TO BE DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCEED
0.15mm PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
8
9
SEATING
PLANE
T
16X
7.6
7.4
B
0.1 T
5
0.75
°
5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD
FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25mm PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
0.25 X45
0.32
0.23
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
0.62mm.
1.0
0.4
°
°
7
0
SECTION A-A
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NOTES
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NOTES
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NOTES
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