MC3310 [ETC]

Motion Processor; 移动处理器


型号：	MC3310
厂家：	ETC
描述：	Motion Processor 移动处理器
文件：	总83页 (文件大小：1080K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Pilot™Motion Processor

MC3310 Single Chip

Technical Specifications

for Brushless Servo Motion Control

Performance Motion Devices, Inc.

55 Old Bedford Road

Revision 1.7, July 2003

Lincoln, MA 01773

NOTICE

This document contains proprietary and confidential information of Performance Motion Devices,

Inc., and is protected by federal copyright law. The contents of this document may not be disclosed

to third parties, translated, copied, or duplicated in any form, in whole or in part, without the express

written permission of PMD.

The information contained in this document is subject to change without notice. No part of this

document may be reproduced or transmitted in any form, by any means, electronic or mechanical,

for any purpose, without the express written permission of PMD.

Navigator, Pilot and C-Motion are trademarks of Performance Motion Devices, Inc

Warranty

PMD warrants performance of its products to the specifications applicable at the time of sale in

accordance with PMD's standard warranty. Testing and other quality control techniques are utilized

to the extent PMD deems necessary to support this warranty. Specific testing of all parameters of

each device is not necessarily performed, except those mandated by government requirements.

Performance Motion Devices, Inc. (PMD) reserves the right to make changes to its products or to

discontinue any product or service without notice, and advises customers to obtain the latest version

of relevant information to verify, before placing orders, that information being relied on is current

and complete. All products are sold subject to the terms and conditions of sale supplied at the time

of order acknowledgement, including those pertaining to warranty, patent infringement, and

limitation of liability.

Safety Notice

Certain applications using semiconductor products may involve potential risks of death, personal

injury, or severe property or environmental damage. Products are not designed, authorized, or

warranted to be suitable for use in life support devices or systems or other critical applications.

Inclusion of PMD products in such applications is understood to be fully at the customer's risk.

In order to minimize risks associated with the customer's applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent procedural hazards.

Disclaimer

PMD assumes no liability for applications assistance or customer product design. PMD does not

warrant or represent that any license, either express or implied, is granted under any patent right,

combination, machine, or process in which such products or services might be or are used. PMD's

publication of information regarding any third party's products or services does not constitute PMD's

approval, warranty or endorsement thereof.

MC3310 Technical Specifications

iii

MC3310 Technical Specifications

Related Documents

Pilot Motion Processor User’s Guide (MC3000UG)

How to set up and use all members of the Pilot Motion Processor family.

Pilot Motion Processor Programmer’s Reference (MC3000PR)

Descriptions of all Pilot Motion Processor commands, with coding syntax and examples, listed

alphabetically for quick reference.

Pilot Motion Processor Technical Specifications

These booklets contain physical and electrical characteristics, timing diagrams, pinouts and pin

descriptions of each:

MC3110, for brushed servo motion control (MC3110TS)

MC3310, for brushless servo motion control (MC3310TS)

MC3410, for microstepping motion control (MC3410TS)

MC3510, for stepper motion control (MC3510TS)

Pilot Motion Processor Developer’s Kit Manual (DK3000M)

How to install and configure the DK3310 developer’s kit PC board.

MC3310 Technical Specifications

Table of Contents

Warranty...................................................................................................................................................... iii

Safety Notice ................................................................................................................................................ iii

Disclaimer..................................................................................................................................................... iii

Related Documents....................................................................................................................................... v

Table of Contents........................................................................................................................................ vii

1 The Pilot Family ........................................................................................................................................ 9

2 Functional Characteristics...................................................................................................................... 11

2.1

2.2

2.3

2.4

2.5

Configurations, parameters, and performance.............................................................................. 11

Physical characteristics and mounting dimensions....................................................................... 13

Environmental and electrical ratings ............................................................................................ 14

System configuration.................................................................................................................... 14

Peripheral device address mapping............................................................................................... 15

3 Electrical Characteristics........................................................................................................................ 16

3.1

3.2

DC characteristics......................................................................................................................... 16

AC characteristics......................................................................................................................... 16

4 I/O Timing Diagrams .............................................................................................................................. 18

4.1

4.2

4.3

4.4

Clock ............................................................................................................................................ 18

Quadrature encoder input ............................................................................................................. 18

Reset............................................................................................................................................. 18

Host interface, 8/16 mode (requires external logic device) .......................................................... 19

Instruction write, 8/16 mode................................................................................................. 19

Data write, 8/16 mode........................................................................................................... 19

Data read, 8/16 mode............................................................................................................ 20

Status read, 8/16 mode.......................................................................................................... 20

Host interface, 16/16 mode (requires external logic device) ........................................................ 21

Instruction write, 16/16 mode............................................................................................... 21

Data write, 16/16 mode......................................................................................................... 21

Data read, 16/16 mode.......................................................................................................... 22

Status read, 16/16 mode........................................................................................................ 22

External memory timing............................................................................................................... 23

External memory read........................................................................................................... 23

External memory write ......................................................................................................... 23

Peripheral device timing............................................................................................................... 24

Peripheral device read........................................................................................................... 24

Peripheral device write ......................................................................................................... 24

4.4.1

4.4.2

4.4.3

4.4.4

4.5

4.5.1

4.5.2

4.5.3

4.5.4

4.6

4.6.1

4.6.2

4.7

4.7.1

4.7.2

5 Pinouts and Pin Descriptions.................................................................................................................. 25

5.1

5.2

Pinouts for MC3310 ..................................................................................................................... 25

CP chip pin description table........................................................................................................ 26

MC3310 Technical Specifications

vii

6 Parallel Communication ......................................................................................................................... 30

6.1

6.2

6.3

Host interface pin description table .............................................................................................. 30

16-bit Host Interface (IOPIL16) ................................................................................................... 32

8-bit Host Interface (IOPIL8)....................................................................................................... 46

7 Application Notes..................................................................................................................................... 62

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Design Tips................................................................................................................................... 62

RS-232 Serial Interface ................................................................................................................ 64

RS 422/485 Serial Interface.......................................................................................................... 66

PWM Motor Interface .................................................................................................................. 68

12-bit Parallel DAC Interface....................................................................................................... 70

16-bit Serial DAC Interface.......................................................................................................... 72

RAM Interface.............................................................................................................................. 74

User-defined I/O........................................................................................................................... 76

12-bit A/D Interface...................................................................................................................... 78

7.10 16-bit A/D Input ........................................................................................................................... 80

7.11 External Gating Logic Index ........................................................................................................ 82

MC3310 Technical Specifications

viii

1 The Pilot Family

MC3110

MC3310

MC3410

MC3510

Number of axes

Brushless servo

Stepping

Microstepping

Stepping

Brushed servo

Motor type supported

Brushed servo

(single phase)

Commutated (6-

step or sinusoidal)

Pulse and Direction

Output format

Incremental encoder

input

√

Parallel word device

input

Parallel communication

Serial communication

S-curve profiling

√

On-the-fly changes

Directional limit

switches

Programmable bit output

√

Software-invertable

signals

PID servo control

Feedforward (accel &

vel)

Derivative sampling time

Data trace/diagnostics

PWM output

Pulse & direction output

Index & Home signals

Motion error detection

Axis settled indicator

DAC-compatible output

Position capture

√

√ (with encoder)

√

Analog input

User-defined I/O

External RAM support

Multi-chip

synchronization

Chip part numbers

Developer's Kit p/n's:

√ (MC3113)

MC3110

√ (MC3313)

MC3310

√ (MC3413)

MC3410

MC3510

DK3510

DK3110

DK3310

DK3410

Parallel communication is available via an additional logic device

Introduction

This manual describes the operational characteristics of the MC3310 Motion Processor from PMD.

This device is a member of the MC3000 family of single-chip, single-axis motion processors.

MC3310 Technical Specifications

Each device of the MC3000 family is a complete chip-based motion processor providing trajectory

generation and related motion control functions for one axis including servo loop closure or on-

board commutation where appropriate. This family of products provides a software-compatible

selection of dedicated motion processors that can handle a large variety of system configurations.

The chip architecture not only makes it ideal for the task of motion control, it allows for similarities

in software commands, so software written for one motor type can be re-used if the motor type is

changed.

Pilot Family Summary

MC3110 – This single-chip, single-axis motion processor outputs motor commands in either

Sign/Magnitude PWM or DAC-compatible format for use with brushed servo motors, or with

brushless servo motors having external commutation.

MC3310 – This single-chip, single-axis motion processor outputs sinusoidally commutated motor

signals appropriate for driving brushless motors. Depending on the motor type, the output is a two-

phase or three-phase signal in either PWM or DAC-compatible format.

MC3410 – This single-chip, single-axis motion processor outputs microstepping signals for stepping

motors. Two phased signals per axis are generated in either PWM or DAC-compatible format.

MC3510 – This single-chip, single-axis motion processor outputs pulse and direction signals for

stepping motor systems.

MC3310 Technical Specifications

2 Functional Characteristics

2.1 Configurations, parameters, and performance

Single axis, single chip.

Configuration

Closed loop (motor command is driven from output of servo filter)

Open loop (motor command is driven from user-programmed register)

Operating modes

8/16 parallel (8 bit external parallel bus with 16 bit internal command word size)

Communication modes

16/16 parallel (16 bit external parallel bus with 16 bit internal command word

size)

Point to point asynchronous serial

Multi-drop asynchronous serial

1,200 baud to 416,667 baud

Serial port baud rate range

Position range

-2,147,483,648 to +2,147,483,647 counts

-32,768 to +32,767 counts/sample with a resolution of 1/65,536 counts/sample

-32,768 to +32,767 counts/sample²with a resolution of 1/65,536 counts/sample²

0 to ½ counts/sample³, with a resolution of 1/4,294,967,296 counts/sample³

S-curve point-to-point (Velocity, acceleration, jerk, and position parameters)

Velocity range

Acceleration/deceleration ranges

Jerk range

Profile modes

Trapezoidal point-to-point (Velocity, acceleration, deceleration, and position

parameters)

Velocity-contouring (Velocity, acceleration, and deceleration parameters)

Scalable PID + Velocity feedforward + Acceleration feedforward + Bias. Also

includes integration limit, settable derivative sampling time, and output motor

command limiting

Filter modes

16 bits

Filter parameter resolution

Position error tracking

Motion error window (allows axis to be stopped upon exceeding programmable

window)

Tracking window (allows flag to be set if axis exceeds a programmable position

window)

Axis settled (allows flag to be set if axis exceeds a programmable position

window for a programmable amount of time after trajectory motion is compete)

PWM (9-bit resolution at 20 kHz)

DAC (16 bits)

Motor output modes

20 kHz

Commutation rate

Incremental (up to 5 million counts/sec)

Parallel-word (up to 160 million counts/sec)

16 bits

Maximum encoder rate

Parallel encoder word size

Parallel encoder read rate

Servo loop timing range

Minimum servo loop time

Multi-chip synchronization

20 kHz (reads all axes every 50 µsec)

153.6 µsec to 32.767 milliseconds

153.6 µsec

<10µsec difference between master and slave servo cycle

MC3313 chipset only

2 per axis: one for each direction of travel

2 per axis: index and home signals

Limit switches

Position-capture triggers

MC3310 Technical Specifications

1 AxisIn signal per axis, 1 AxisOut signal per axis

Other digital signals (per axis)

Software-invertable signals

Index, Home, AxisIn, AxisOut, PositiveLimit, NegativeLimit (all individually

programmable)

8 10-bit analog inputs

Analog input

256 16-bit wide user defined I/O

User defined discrete I/O

RAM/external memory support

65,536 blocks of 32,768 16-bit words per block. Total accessible memory is

2,147,483,648 16 bit words

one-time

Trace modes

continuous

Max. number of trace variables

Number of traceable variables

Number of host instructions

152

MC3310 Technical Specifications

2.2 Physical characteristics and mounting dimensions

All dimensions are in inches (with millimeters in brackets).

Dimension

Minimum

(inches)

Maximum

(inches)

1.070

0.934

1.088

1.090

0.966

1.112

0.800 nominal

MC3310 Technical Specifications

2.3

Environmental and electrical ratings

Storage Temperature (Ts)

-55 °C to 150 °C

0 °C to 70 °C*

400 mW

Operating Temperature (T^a)

Power Dissipation (P^d)

20.0 MHz

Nominal Clock Frequency (F^clk)

Supply Voltage limits (V^cc)

Supply Voltage operating range (V^cc)

-0.3V to +7.0V

4.75V to 5.25V

* An industrial version with an operating range of -40°C to 85°C is also available. Please contact

PMD for more information.

2.4 System configuration

The following figure shows the principal control and data paths in an MC3310 system.

Host

HostIntrpt

Serial Port

Parallel port

Home

Index

Pilot Motion Processor

System clock

(40 MHz)

20MHz clock

Parallel Communication

PLD/FPGA

16 bit data/address bus

External memory

Limit

switches

D/A

converter

Motor

Amplifier

DAC output

User I/O

Parallel-word input

Serial port configuration

The shaded area shows the CPLD/FPGA that must be provided by the designer if parallel

communication is required. A description and the necessary logic (in the form of schematics) of this

device are detailed in section 6 of this manual. The CP chip contains the profile generator, which

calculates velocity, acceleration, and position values for a trajectory; and the digital servo filter, which

stabilizes the motor output signal.

MC3310 Technical Specifications

The filter produces one of two types of output:

•

a Pulse-Width Modulated (PWM) signal output; or

a DAC-compatible value routed via the data bus to the appropriate D/A converter.

Axis position information returns to the motion processor in the form of encoder feedback using

either the incremental encoder input signals, or via the bus as parallel word input.

2.5 Peripheral device address mapping

Device addresses on the CP chip’s data bus are memory-mapped to the following locations:

Address

Device

Description

0200h

Serial port data

Contains the configuration data (transmission rate,

parity, stop bits, etc) for the asynchronous serial port

0800h

1000h

2000h

4000h

8000h

Parallel-word encoder Base address for parallel-word feedback devices

User-defined

Base address for user-defined I/O devices

Page pointer to external memory

RAM page pointer

Motor-output DACs

Parallel interface

Base address for motor-output D/A converters

Base address for parallel interface communication

MC3310 Technical Specifications

3 Electrical Characteristics

3.1 DC characteristics

(V_ccand T_aper operating ratings, F_clk= 20.0 MHz)

Symbol

Parameter

Supply Voltage

Supply Current

Minimum Maximum

Conditions

V_cc

I_dd

4.75 V

5.25 V

80 mA

open outputs

Input Voltages

V_ih

V_il

V_ihclk

Logic 1 input voltage

Logic 0 input voltage

Logic 1 voltage for clock pin

(ClockIn)

2.0 V

-0.3 V

3.0 V

V_cc+ 0.3 V

0.8 V

V_cc+ 0.3 V

V_oclk

Logic 0 voltage for clock pin

(ClockIn)

-0.3 V

0.7 V

V_ihreset

Logic 1 voltage for reset pin (reset) 2.2 V

V_cc+ 0.3 V

Output Voltages

V_oh

V_ol

Logic 1 Output Voltage

Logic 0 Output Voltage

2.4 V

@CP I_o= -23 mA

@CP I_o= 6 mA

0.33 V

Other

I_out

I_in

Tri-State output leakage current

Input current

@CP

0 < V_out< V_cc

@CP

0 < V_i< V_cc

-5 µA

-10 µA

15 pF

5 µA

10 µA

C_io

Input/Output capacitance

@CP typical

Analog Input

Z_ai

Analog input source impedance

9kΩ

E_dnl

Differential nonlinearity error.

Difference between the step width

and the ideal value.

-1

1.5 LSB

E_inl

Integral nonlinearity error.

Maximum deviation from the best

straight line through the ADC

transfer characteristics, excluding

the quantization error.

+/-1.5 LSB

3.2 AC characteristics

See timing diagrams, Section 4, for Tn numbers. The symbol “~” indicates active low signal.

Timing Interval

Minimum

Maximum

Clock Frequency (F_clk)

Clock Pulse Width

Clock Period (note 2)

Encoder Pulse Width

Dwell Time Per State

~HostSlct Hold Time

> 0 MHz

25 nsec

50 nsec

150 nsec

75 nsec

0 nsec

20 MHz (note 1)

MC3310 Technical Specifications

Timing Interval

Minimum

Maximum

~HostSlct Setup Time

HostCmd Setup Time

HostCmd Hold Time

0 nsec

Read Data Access Time

Read Data Hold Time

~HostRead High to HI-Z Time

HostRdy Delay Time

~HostWrite Pulse Width

Write Data Delay Time

Write Data Hold Time

Read Recovery Time (note 2)

Write Recovery Time (note 2)

Read Pulse Width

Address Setup Delay Time

Data Access Time

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27

T28

T29

T30

T31

T32

T33

T34

T35

T36

T37

T38

T39

T40

T50

T51

T52

T53

T54

T55

T56

25 nsec

10 nsec

20 nsec

150 nsec

100 nsec

70 nsec

35 nsec

0 nsec

60 nsec

70 nsec

7 nsec

19 nsec

2 nsec

7 nsec

Data Hold Time

Address Setup Delay Time

Address Setup to WriteEnable High

RAMSlct Low to WriteEnable High

Address Hold Time

WriteEnable Pulse Width

Data Setup Time

Data Setup before Write High Time

Address Setup Delay Time

Data Access Time

72 nsec

79 nsec

17 nsec

39 nsec

3 nsec

42 nsec

7 nsec

71 nsec

2 nsec

7 nsec

Data Hold Time

Address Setup Delay Time

Address Setup to WriteEnable High

PeriphSlct Low to WriteEnable High

Address Hold Time

WriteEnable Pulse Width

Data Setup Time

Data Setup before Write High Time

Read to Write Delay Time

Reset Low Pulse Width

RAMSlct Low to Strobe Low

Strobe High to RAMSlct High

WriteEnable Low to Strobe Low

Strobe High to WriteEnable High

PeriphSlct Low to Strobe Low

Strobe High to PeriphSlct High

122 nsec

129 nsec

17 nsec

89 nsec

3 nsec

92 nsec

50 nsec

5.0 µsec

1 nsec

4 nsec

1 nsec

3 nsec

1 nsec

4 nsec

Note 1 Performance figures and timing information valid at F_clk= 20.0 MHz only. For timing

information and performance parameters at F_clk< 20.0 MHz see section 7.1.

Note 2 The clock low/high split has an allowable range of 45-55%.

MC3310 Technical Specifications

4 I/O Timing Diagrams

For the values of Tn, please refer to the table in Section 3.2.

The host interface timing shown in diagrams 4.4 and 4.5 is only valid when an external logic device is

used to provide a parallel communication interface. Refer to section 6 for more information.

4.1 Clock

ClockIn

4.2 Quadrature encoder input

Quad A

Quad B

~Index

4.3 Reset

V_cc

ClockIn

~RESET

T50

MC3310 Technical Specifications

4.4 Host interface, 8/16 mode (requires external logic device)

4.4.1 Instruction write, 8/16 mode

see note

~HostSlct

HostCmd

see note

T18

T14

~HostWrite

T16

HostData0-7

HostRdy

High byte

Low byte

T15

T13

Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.

4.4.2 Data write, 8/16 mode

~HostSlct

see note

HostCmd

T18

T14

~HostWrite

T16

High byte

Low byte

HostData0-7

HostRdy

T15

T13

Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this

point.

MC3310 Technical Specifications

4.4.3 Data read, 8/16 mode

~HostSlct

see note

HostCmd

~HostRead

T19

T12

High

byte

High-Z

Low byte

HostData0-7

HostRdy

T10

T11

T13

Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this

point.

4.4.4 Status read, 8/16 mode

~HostSlct

HostCmd

T17

~HostRead

T19

T12

High-Z

High

byte

Low byte

HostData0-7

T10

T11

MC3310 Technical Specifications

4.5 Host interface, 16/16 mode (requires external logic device)

4.5.1 Instruction write, 16/16 mode

~HostSlct

HostCmd

T14

~HostWrite

T16

HostData0-15

HostRdy

T15

T13

4.5.2 Data write, 16/16 mode

~HostSlct

HostCmd

T14

~HostWrite

T16

HostData0-15

T15

HostRdy

T13

MC3310 Technical Specifications

4.5.3 Data read, 16/16 mode

~HostSlct

HostCmd

T19

~HostRead

T12

High-Z

HostData0-15

HostRdy

T10

T11

T13

4.5.4 Status read, 16/16 mode

~HostSlct

HostCmd

~HostRead

T19

T12

High-Z

HostData0-15

T10

T11

MC3310 Technical Specifications

4.6 External memory timing

4.6.1 External memory read

Note: PMD recommends using memory with an access time no greater than 15 nsec.

T20

T40

~RAMSlct

Addr0-Addr15

W/~R

~WriteEnbl

T21

Data0-Data15

T51

T52

~Strobe

4.6.2 External memory write

T23

~RAMSlct

Addr0-Addr15

R/~W

T24

T25

T26

W/~R

T29

~WriteEnbl

Data0-Data15

~Strobe

T28

T27

T53

T54

MC3310 Technical Specifications

4.7 Peripheral device timing

4.7.1 Peripheral device read

T30

T40

~PeriphSlct

Addr0-Addr15

W/~R

T31

~WriteEnbl

T31

Data0-Data15

T55

T32

T56

~Strobe

4.7.2 Peripheral device write

T33

~PeriphSlct

Addr0-Addr15

R/~W

T34

T35

T36

W/~R

T39

~WriteEnbl

Data0-Data15

~Strobe

T38

T37

T53

T54

MC3310 Technical Specifications

5 Pinouts and Pin Descriptions

5.1 Pinouts for MC3310

2, 7, 13, 21, 35, 36, 40, 47, 50,

52, 60, 62, 66, 93, 103, 121

130

129

132

~WriteEnbl

R/~W

VCC

AnalogVcc

AnalogRefHigh

AnalogRefLow

AnalogGnd

Analog1

100

101

102

~Strobe

~PeriphSlct

~RAMSlct

~Reset

W/~R

SrlRcv

SrlXmt

SrlEnable

~HostIntrpt

ClockIn

Addr0

Addr1

Addr2

Addr3

Addr4

Addr5

Addr6

Addr7

Addr8

Analog2

Analog3

Analog4

Analog5

Analog6

Analog7

Analog8

PosLim1

NegLim1

AxisOut1

AxisIn1

PWMMag1

PWMMag2

PWMMag3

PWMSign1

PWMSign2

QuadA1

QuadB1

~Index1

~Home1

Hall1A

Hall1B

Hall1C

NC/Synch

110

111

112

114

115

116

117

118

119

122

123

124

125

126

127

128

Addr9

Addr10

Addr11

Addr12

Addr13

Addr14

Addr15

Data0

Data1

Data2

Data3

Data4

I/OIntrpt

PrlEnable

Data5

Data6

Data7

Data8

Data9

Data10

Data11

Data12

Data13

Data14

Data15

GND

3, 8, 14, 20, 29, 37, 46, 56, 59,

61, 71, 92, 104, 113, 120

Unassigned

5, 30-34, 38, 39, 42, 45, 48, 49,

51, 55, 57, 95, 105, 106, 107-

109, 131

AGND

78-81

MC3310 Technical Specifications

5.2 CP chip pin description table

Pin Name and number Direction

Description

~WriteEnbl

output

When low, this signal enables data to be written to the bus.

This signal is high when the CP chip is performing a read, and low when it is

performing a write.

R/~W

~Strobe

output

This signal is low when the data and address are valid during CP

communications.

~PeriphSlct

~RAMSlct

~Reset

130

129

output

input

This signal is low when peripheral devices on the data bus are being addressed.

This signal is low when external memory is being accessed.

This is the master reset signal. When brought low, this pin resets the processor to

its initial conditions.

W/~R

132

output

input

This signal is the inverse of R/~W; it is high when R/~W is low, and vice versa. For

some decode circuits, this is more convenient than R/~W.

This pin receives serial data from the asynchronous serial port. If serial

communication is not used, this pin should be tied to V_cc.

SrlRcv

SrlXmt

output

This pin transmits serial data to the asynchronous serial port.

SrlEnable

This pin sets the serial port enable line. SrlEnable is always high for the point-to-

point protocol and is high during transmission for the multi-drop protocol.

When low, this signal causes an interrupt to be sent to the host processor.

This signal interrupts the CP chip when a host I/O transfer is complete. It

should be connected to CPIntrpt of the parallel interface chip.

If the parallel interface is disabled (see below) this signal can be left unconnected

or tied to V_cc.

~HostIntrpt

I/OIntrpt

output

input

PrlEnable

input

This signal enables/disables the parallel communication with the host. If this

signal is tied high, the parallel interface is enabled. If this signal is tied low the

parallel interface is disabled. See section 6 of this manual for more information

on parallel communication.

WARNING! This signal should only be tied high if an external

logic device that implements the parallel communication logic

included in the design. This signal is an output during device reset

and as such any connection to GND or V_ccmust be via a series

resistor.

Data0

Data1

Data2

Data3

Data4

Data5

Data6

Data7

Data8

Data9

Data10

Data11

Data12

Data13

Data14

Data15

bi-directional Multi-purpose data lines. These pins comprise the CP chip’s external data bus,

used for all communications with peripheral devices such as external memory or

DACs. They may also be used for parallel-word input and for user-defined I/O

operations.

MC3310 Technical Specifications

Pin Name and number Direction

Description

Addr0

Addr1

Addr2

Addr3

Addr4

Addr5

Addr6

Addr7

Addr8

Addr9

Addr10

Addr11

Addr12

Addr13

Addr14

Addr15

ClockIn

110

111

112

114

115

116

117

118

119

122

123

124

125

126

127

128

output

Multi-purpose Address lines. These pins comprise the CP chip’s external address

bus, used to select devices for communication over the data bus.

They may be used for DAC output, parallel word input, or user-defined I/O

operations. See the Pilot Motion Processor User’s Guide for a complete memory map.

input

This is the clock signal for the Motion Processor. It is driven at a nominal

20MHz.

CP chip analog power supply voltage. This pin must be connected to the analog

input supply voltage, which must be in the range 4.5-5.5 V

AnalogVcc

If the analog input circuitry is not used, this pin must be connected to V_cc.

AnalogRefHigh 85

AnalogRefLow 86

input

CP chip analog high voltage reference for A/D input. The allowed range is

AnalogRefLow to AnalogVcc.

If the analog input circuitry is not used, this pin must be connected to V_cc.

CP chip analog low voltage reference for A/D input. The allowed range is

AnalogGND to AnalogRefHigh.

If the analog input circuitry is not used, this pin must be connected to GND.

AnalogGND

CP chip analog input ground. This pin must be connected to the analog input

power supply return.

If the analog input circuitry is not used, this pin must be connected to GND.

Analog1

Analog2

Analog3

Analog4

input

These signals provide general-purpose analog voltage levels, which are sampled

by an internal A/D converter. The A/D resolution is 10 bits.

The allowed range is AnalogRefLow to AnalogRefHigh.

Analog5

Analog6

Analog7

Any unused pins should be tied to AnalogGND.

If the analog input circuitry is not used, these pins should be tied to GND.

Analog8

PWMMag1

PWMMag2

PWMMag3

PWMSign1

PWMSign2

100

101

102

output

These pin provide the Pulse Width Modulated signals for each phase to the

motor. The PWM resolution is 9 bits at a frequency of 20.0 KHz.

In 2 or 3-phase PWM 50/50 mode, PWMMag1/2/3 are the only signals and

encode both the magnitude and direction in the one signal.

In single-phase PWM sign/magnitude mode, PWMMag1 and PWMSign1 are the

PWM magnitude and direction signals respectively.

In 2-phase PWM sign/magnitude mode, PWMMag1 and PWMSign1 are the

PWM magnitude and direction signals for Phase A. PWMMag2 and PWMSign2,

are the PWM magnitude and direction signals for Phase B.

Unused pins may be left unconnected.

MC3310 Technical Specifications

Pin Name and number Direction

Description

QuadA1

QuadB1

input

These pins provide the A and B quadrature signals for the incremental encoder.

When the axis is moving in the positive (forward) direction, signal A leads signal

B by 90°.

The theoretical maximum encoder pulse rate is 5.1 MHz. Actual maximum rate

will vary, depending on signal noise.

NOTE: Many encoders require a pull-up resistor on each signal to establish a

proper high signal. Check your encoder’s electrical specification.

This pin provides the Index signal for the incremental encoder. A valid index

pulse is recognized by the chip when this signal transitions from high to low.

~Index1

input

There is no internal gating of the index signal with the encoder A

and B inputs. This must be performed externally if desired. Refer

to the Application Notes section at the end of this manual for an

example.

~Home1

PosLim1

NegLim1

input

This pin provides the Home signal, general-purpose inputs to the position-

capture mechanism. A valid Home signal is recognized by the chip when ~Home

goes low.

WARNING! If this pin is not used, its signal should be tied high.

This signal provides input from the positive-side (forward) travel limit switch.

On power-up or Reset this signal defaults to active low interpretation, but the

interpretation can be set explicitly using the SetSignalSense instruction.

WARNING! If this pin is not used, its signal should be tied high.

This signal provides input from the negative-side (reverse) travel limit switch. On

power-up or Reset this signal defaults to active low interpretation, but the

interpretation can be set explicitly using the SetSignalSense instruction.

WARNING! If this pin is not used, its signal should be tied high.

This signal is an output during device reset and as such any

connection to GND or V_ccmust be via a series resistor.

AxisOut1

AxisIn1

output

input

This pin can be programmed to track the state of any bit in the Status registers.

If this pin is not used it may be left unconnected.

This is a general-purpose or programmable input. It can be used as a breakpoint

input, to stop a motion axis, or to cause an Update to occur.

If this pin is not used it may be left unconnected.

Hall1A

Hall1B

Hall1C

Input

Hall sensor inputs. Each set (A, B, and C) of signals encodes 6 valid states as

follows: A on, A and B on, B on, B and C on, C on, C and A on. A sensor is

defined as being on when its signal is high.

These signals should only be connected to Hall sensors that are

mounted at a 120° offset. Schemes that provide Hall signals 60°

apart will not work.

If these pins are not used they may be left unconnected.

NC/Synch

input/output On the MC3310 this pin is not used.

On the MC3313 this pin is the synchronization signal. In the disabled mode, the

pin is configured as an input and is not used. In the master mode, the pin

outputs a synchronization pulse that can be used by slave nodes or other devices

to synchronize with the internal chip cycle of the master node. In the slave

mode, the pin is configured as an input and a pulse on the pin synchronizes the

internal chip cycle.

MC3310 Technical Specifications

Pin Name and number Direction

Description

V_cc

2, 7, 13, 21, 35, 36, 40, CP digital supply voltage. All of these pins must be connected to the supply

47, 50, 52, 60, 62, 66, voltage. V_ccmust be in the range 4.75 - 5.25 V

93, 103, 121

WARNING! Pin 35 must be tied HIGH with a pull-up resistor. A

nominal value of 22K Ohms is suggested.

GND

3, 8, 14, 20, 29, 37, 46, CP ground. All of these pins must be connected to the power supply return.

56, 59, 61, 71, 92, 104,

113, 120

AGND

78-81

These signals must be tied to AnalogGND.

If the analog input circuitry is not used, these pins must be tied to GND.

unassigned

45, 48, 49, 51, 55, 105, These signals may be connected to GND for better noise immunity and reduced

106, 107, 108, 109

power consumption or they can be left unconnected (floating).

5, 30-34, 38, 39, 42,

57, 95, 131

These signals must be left unconnected (floating).

MC3310 Technical Specifications

6 Parallel Communication

With the addition of an external logic device, the Pilot motion processor can communicate with a

host processor using a parallel data stream. This offers a higher communication rate than a serial

interface and may be used in configurations where a serial connection is not available or not

convenient. This section details the required logic that must be implemented in the external device

as well as the necessary connections to the CP chip.

The reference design files for the parallel interface chip, in Actel/ViewLogic format, are available

from PMD. There are two versions of the design, one for interfacing with host processors that have

an 8-bit data bus and one for host processors that have a 16-bit data bus. The designs are called

IOPIL8 and IOPIL16 respectively. The interface to the CP chip is essentially identical in both.

The function of the I/O chip is to provide a shared-memory style interface between the host and CP

chip, comprised of four 16-bit wide locations. These are used for transferring commands and data

between the host and Pilot motion processor. The CP chip accesses the command/data registers

using its 16-bit external data bus while the host accesses the registers via a parallel interface with chip

select, read, write and command/data signals. If necessary, the host side interface can be modified

by the designer to match specific requirements of the host processor.

6.1 Host interface pin description table

Pin Name

Direction

input

Description

HostCmd

This signal is asserted high to write a host instruction to the motion processor, or to

read the status of the HostRdy and HostIntrpt signals. It is asserted low to read or write

a data word.

This signal is used to synchronize communication between the motion processor

and the host. HostRdy will go low (indicating host port busy) at the end of a read or

write operation according to the interface mode in use, as follows:

Interface Mode HostRdy goes low

HostRdy

output

8/16

16/16

serial

after the second byte of the instruction word

after the second byte of each data word is transferred

after the 16-bit instruction word

after each 16-bit data word

n/a

HostRdy will go high, indicating that the host port is ready to transmit, when the last

transmission has been processed. All host port communications must be made

with HostRdy high (ready).

A typical busy-to-ready cycle is 12.5 microseconds, but can be substantially longer,

up to 100 microseconds.

~HostRead

~HostWrite

~HostSlct

CPIntrpt

input

output

When ~HostRead is low, a data word is read from the motion processor.

When ~HostWrite is low, a data word is written to the motion processor.

When ~HostSlct is low, the host port is selected for reading or writing operations.

I/O chip to CP chip interrupt. This signal sends an interrupt to the CP chip

whenever a host–chipset transmission occurs. It should be connected to CP chip

pin 53, I/OIntrpt.

CPR/~W

input

This signal is high when the I/O chip is reading data from the I/O chip, and low

when it is writing data. It should be connected to CP chip pin 4, R/W.

CPStrobe

This signal goes low when the data and address become valid during Motion

processor communication with peripheral devices on the data bus, such as external

memory or a DAC. It should be connected to CP chip pin 6, Strobe.

MC3310 Technical Specifications

Pin Name

Direction

input

Description

CPPeriphSlct

This signal goes low when a peripheral device on the data bus is being addressed. It

should be connected to CP chip pin 130, PeriphSlct.

CPAddr0

CPAddr1

CPAddr15

input

These signals are high when the CP chip is communicating with the I/O chip (as

distinguished from any other device on the data bus). They should be connected to

CP chip pins 110 (Addr0), 111 (Addr1), and 128 (Addr15).

MasterClkIn

input

This is the master clock signal for the motion processor. It is driven at a nominal

40 MHz

This signal provides the clock pulse for the CP chip. Its frequency is half that of

MasterClkIn (pin 89), or 20 MHz nominal. It is connected directly to the CP chip

I/Oclk signal (pin 58).

CPClk

output

HostData0

HostData1

HostData2

HostData3

HostData4

HostData5

HostData6

HostData7

HostData8

HostData9

HostData10

HostData11

HostData12

HostData13

HostData14

HostData15

CPData0

bi-directional, These signals transmit data between the host and the Motion processor through

tri-state

the parallel port. Transmission is mediated by the control signals ~HostSlct,

~HostWrite, ~HostRead and HostCmd.

In 16-bit mode, all 16 bits are used (HostData0-15). In 8-bit mode, only the low-

order 8 bits of data are used (HostData0-7).

bi-directional

These signals transmit data between the I/O chip and pins Data0-15 of the CP chip,

CPData1

via the motion processor data bus.

CPData2

CPData3

CPData4

CPData5

CPData6

CPData7

CPData8

CPData9

CPData10

CPData11

CPData12

CPData13

CPData14

CPData15

MC3310 Technical Specifications

6.2 16-bit Host Interface (IOPIL16)

This design implements a parallel interface with a host processor utilizing a 16-bit data bus. An

understanding of the underlying operation of the design is only necessary if the designer intends to

make modifications. In most cases this design can be implemented without changes. The following

notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The

timing for the host to I/O chip communication can be found in section 4.5 and the timing for the

CP to I/O chip communication can be found in section 4.7.

The description below identifies the key elements of each schematic starting with the host side

signals. The paragraph title identifies the key schematic(s) being described in the text.

IOPIL16 3

The host interface is shown in sheet IOPIL16 3. The incoming data HD[15:0] is latched in the

transparent latches when ~HG1 and ~HG2 go high. This would be the result of a write from the

host to the CP. The latched data HI[15:8] and HI[7:0] go to schematic IOPIL16 1 and IOPIL16 5.

Data from the interface to the host, HO[15:8] and HO[7:0] is enabled onto the host bus, HD[15:0],

by HOES2 and HOES1 respectively. The output latches, which present the data during a host read,

are always transparent because GOUT is connected to VDD. The latched I/O is an I/O option on

the Actel part used and could be omitted in the host interface if a different CPLD or FPGA does not

have this feature.

IOPIL16 1

The control for the host interface starts on IOPIL16 1. HOES1 and HOES2 are the AND of

~HSEL and ~HRD and enable read data onto the host bus, as previously described. HRDY is a

handshaking signal to the host to allow asynchronous communication between the host and the CP.

The host must wait until HRDY is true before attempting to communicate with the CP. This signal

is copied as a bit in the host status register. The host status register may be read at any time to

determine the state of HRDY, or the HRDY output may be used as an interrupt to the host.

~HSEL, ~HRD, ~HWR, and HA0 are the buffered inputs of the host control signals.

HOST INTERFACE/IOPIL16 5

Data from the host HI[15:8] and HI[7:0] is written into REG1 and REG2 on the schematic HOST

INTERFACE by ~EN1 and ~EN2. These registers have a 2 to 1 multiplexed input with both the

host data and the CP data being written to these registers. This is convenient for diagnostic purposes

and is very efficient in the Actel A42MX FPGA's, which are multiplexer based but if the

configuration of the logic device used demands it, separate registers could be used for the host and

CP data. The schematic for this register is shown as DFME8. Only commands and checksums are

written to registers REG1 and REG2 while data is written and read from the set of data registers,

DATREG shown on IOPIL16 5. These 3 data registers buffer data sent to and from the CP,

reducing the number of interrupts the CP must handle. The output from REG1 and REG2,

CIQ[15:8] and CIQ[7:0] go to IOPIL16 5, where they are multiplexed with the other data registers.

The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] - the

output of the host status registers REG3 and REG4. As previously mentioned, HRDY becomes

HST15 so it can be read by the host. The rest of the status register is written by the CP to provide

information to the host. HA0 acts as an address bit, and usually is an address bit on the bus. When

the host is writing, HA0 low indicates data and HA0 high indicates a command. When the host is

reading, HAO low indicates data and HA0 high indicates status. Read status is the only transaction

MC3310 Technical Specifications

allowed while HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two

flops latch the incoming data in the interface latches by driving ~HG1, and ~HG2 low from the

start of the write transaction until the first negative clock transition after the first positive transition

following the start of the write cycle. This tail-biting circuit removes the requirement for hold time

on the data bus.

HICTLA

Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at

the top generates HCYC one clock interval after the interface has been accessed and the host has

finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is

preserved in the three flops F13, F8, and F9. A host write or a CP write, DSIW, enable REG1 and

REG2 on the HOST INTERFACE schematic discussed previously. A host data write generates

~ENHD1 and ~ENHD2 for the data registers on the DATREG schematic. The logic at the bottom

of the page generates the CP interrupt, the HRDY and the HCMDFL. The HCMDFL is used in the

CP status to indicate a command. DSIW, the CP writing to REG1 and REG2 on the HOST

INTERFACE schematic clears the interrupt and reasserts HRDY. HRDY is de-asserted during all

host transactions except read status, and stays de-asserted until the CP has completed the DSIW

cycle that clears the interrupt and reasserts HRDY. As mentioned previously data transfers to and

from the host use the data registers and do not interrupt the CP. The CP knows the number of data

transfers that must take place after decoding the command. It places this number, 0-3, in the 2 least

significant bits of the host status register, HST[1:0]. These become DPNT[1:0] on this page of the

schematic and enable an interrupt at 0 for a read and 1 or 0 for a write. The CP always leaves theses

bit set to 0 unless setting up a multiple word data transfer. If INTEN is true and LRDST, latched

read status, is false, HCYC will generate an interrupt to the CP. This will also hold HRDY false until

after the CP writes to the interface register, DSIW, thereby generating ~CLRFLGS.

IOPIL16 4

The CP interface is shown in sheet IOPIL16 4. The incoming data DSD[15:0] is latched in the

transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from

the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL16 1 and

IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and

DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output

latches, which present the data during a CP read, are always transparent because GOUT is connected

to VDD. The latched I/O in the Actel part contains both input and output latches. The output

latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature.

The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal

is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.

IOPIL16 2

The CP control starts on IOPIL16 2. The I/O control is generated from ~CPSTRB, ~CPIS,

CPSEL and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out-

enable the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold

times on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be

used for this interface and the CP.

MC3310 Technical Specifications

DSPWA

The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to

save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits,

LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register

and selecting the page for the successive transfers. A read from address 0 reads the status register on

all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The

write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown

on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY.

DSWST writes to the host status register also shown on the HOST INTERFACE schematic.

DSWDREG implements writing to the data registers shown on IOPIL16 5 and DATREG. Finally

the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over

that implements the actual writes to the registers. The use of the data bus latches and the post bus

cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices,

without requiring clocking at several times the bus speed.

DSPRA

The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the

CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15

(indicating the CP is interrupting the host), bits 13 and 14 (both 0 indicating a 16 bit host interface)

and bit 0 (set to 1 during a host command transfer and 0 during data transfer).

HOST INTERFACE

Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts.

This special mode is under the control of the CP and is transparent to the host. When the CP

receives a command from the host it initializes the transfer by setting the number of transfers

expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST

INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on

IOPIL16 5. Note that a Q8 low, which indicates a host command, asynchronously clears this

a host data transfer, and SINT goes high indicating the end of a host cycle the counter is

decremented. MXAD2 selects address RA from the CP latched address bits if the page register

contains 6, or the counter contents DPNT[1:0] if not. This allows the CP to have direct access to

registers 1, 2, and 3, using addresses 1,2,and 3 on page 6. The host on the other hand can only read

or write to the data register, HA0 low and the counter will auto decrement from 3 down to 0

allowing the host to access the registers on DATREG where REG1=R1 and R2, REG2=R3 and R4,

and REG3=R5 and R6. The writes are enabled by the two decoders DECE2X4, while the reads are

selected by the two 4x8 muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and

MDS0. The output data IQ[15:0] goes to HOST INTERFACE schematic below IOPIL16 1 and to

DSPRA below IOPIL16 2. The write data is HI[15:8], HI[7:0] from the host and DSI[15:8] and

DSI[7:0] from the CP.

MC3310 Technical Specifications

HINTF

HSEL

HRD

INBUF

IN17

PAD

HSTSEL

HSTRD

HSTWR

HADR0

HSEL

HRD

HWR

HA0

HOST INTERFACE

(HINTRFA)

IN18

HWR

HA0

HO[7:0]

HO[15:8]

IN19

HI[7:0]

HI[15:8]

DSI[15:8]

DSI[7:0]

DPNT[1:0]

HI[15:8]

IN20

CIQ[7:0]

DSI[15:8]

DSI[7:0]

HST[1:0]

CIQ[7:0]

CIQ[15:8]

DSWST

DSIW

DSWST

DSIW

SINT

HG1

HG2

HG1

HG2

IQ[7:0]

HST14

ST15

IQ[15:8]

HCMDFL

DSPINTR

ST0

DSPINTR

OUTBUF

CLK

HST15

ENHD1

ENHD2

RDY

PAD

HRDY

ENHD1

ENHD2

HRD

HOES1

HOES2

AND2B

HSEL

HRD

AND2B

HSEL

OUTBUF

DSPINTR

PAD

DSPINT

OUT5

IOPIL16 1

22 OCT 2002

DBS

DRAWN BY:

PNT0

PNT1

CSEL0

CSEL1

DSPRA

DSWDREG

ST0

ST15

DSI[7:0]

DSIW

DSWST

PP6

DSIW

DSWST

PP6

DSI[7:0]

IQ[15:0]

PP4

IN27

INBUF

PAD

CPSEL

DG3

IN28

CPR-W

DO[15:0]

LA0

LA1

LA0

LA1

DO[15:0]

IN26

INBUF

PAD

STRB

IN30

CPSEL

R/W

CPSTRB

CPIS

CPSTRB

CPIS

LA0

LA1

LA0

LA1

CKBUF

CPCYC

20CK

CLK

DSPRA

DSPWA

CLKINT

CPSTRB

CPIS

CSACC

NAND3B

CPSEL

DOE1

DOE2

20CK

AND4B

DF1A

R/W

IB1

INBUF

PAD

CLKIN

40CK

CLK

AND4B

DG1

DG2

NAND3B

CSACC

CLK

CQ1

CQ3

DF1

CSACC

CQ3

DG3

NAND4B

CLK

IOPIL16 2

24 OCT 2002

DBS

DRAWN BY:

HIGH SLEW

PAD

HO0

HD0

HI0

PAD

HO4

HD4

HI4

HO8

HD8

HI8

HO12

HD12

HI12

GOUT

VDD

BBDLHS

GIN

HIGH SLEW

PAD

HO1

HD1

HI1

PAD

HO5

HD5

HI5

HO9

HD9

HI9

HO13

HD13

HI13

GOUT

BBDLHS

GIN

HIGH SLEW

PAD

HO2

HD2

HI2

PAD

HO6

HD6

HI6

HO10

HD10

HI10

HO14

HD14

HI14

GOUT

BBDLHS

GIN

HIGH SLEW

PAD

HO3

HD3

HI3

HO7

HD7

HI7

HO15

HD15

HI15

PAD

HO11

HD11

HI11

GOUT

BBDLHS

GIN

HI[7:0]

HI[15:0]

HG1

HO[15:8]

HG2

HO[7:0]

HG2

VCC

HOES1

HOES2

VDD

IOPIL16 3

21 OCT 2002

DBS

DRAWN BY:

DOE1

DO0

HIGH SLEW

DOE1

DO4

DOE2

DO8

DOE2

HIGH SLEW

PAD

DSD0

DSI0

PAD

DSD4

DSI4

DSD8

DSI8

DO12

DSD12

DSI12

GOUT

VDD

GOUT

VDD

BBDLHS

GIN

DOE1

DO1

HIGH SLEW

DOE1

DOE2

HIGH SLEW

PAD

DSD1

DSI1

PAD

DO5

DSD5

DSI5

DO9

DSD9

DSI9

DO13

DSD13

DSI13

GOUT

BBDLHS

GIN

DOE1

DO2

HIGH SLEW

DOE1

DO6

DOE2

DO10

DOE2

DO14

HIGH SLEW

PAD

DSD2

DSI2

PAD

DSD6

DSI6

DSD10

DSI10

DSD14

DSI14

GOUT

BBDLHS

GIN

DOE1

DO7

DOE2

DO15

DOE1

DO3

DOE2

DO11

HIGH SLEW

PAD

DSD7

DSI7

DSD15

DSI15

PAD

DSD3

DSI3

DSD11

DSI11

GOUT

BBDLHS

GIN

DSI[7:0]

DSI[15:8]

DG1

DO[15:8]

DG2

DO[7:0]

DOE2

DG2

DOE1

GND

VCC

GND

HIGH SLEW

PAD

CPA1

VDD

PAD

CPA0

GOUT

IOPIL16 4

OUTBUF

LA1

20CK

PAD

CLKOUT

LA0

BBDLHS

GIN

DG3

GIN

DG3

21 OCT 2002

DBS

DRAWN BY:

ENHD1

DSWDREG

END1

END2

OR2A

DREG

DOE1

PP4

ENHD2

DOE1

PP4

OR2A

CIQ[7:0]

CIQ[15:8]

HI[7:0]

CIQ[15:8]

HI[7:0]

HI[15:8]

DSI[7:0]

DSI[15:8]

RA[1:0]

LA[1:0]

SINT

HIH[15:8]

DSI[7:0]

DSI[15:8]

RA[1:0]

IQ[7:0]

DPINC

AND3

DPNT0

DPNT1

IQ[15:8]

NAND2B

IQ[15:8]

LA[1:0]

PP6

END1

END2

CLK

END1

END2

CLK

DATREG

DCNT2

DSWST

SLOAD

ENABLE

ACLR

DPINC

CLK

CLOCK

DPNT[1:0]

MXAD2

Q[1:0]

DSI[1:0]

DATA[1:0]

RA[1:0]

DATA0_[1:0]

DATA1_[1:0]

RESULT[1:0]

LA[1:0]

LA0

LA1

IOPIL16 5

PP6

22 OCT 2002

DBS

DRAWN BY:

REG1

EN1

HST[1:0]

MUX1

MUX2X8

EN1

IQ[7:0]

REG3

DFME8

REG6

HI[7:0]

HO[7:0]

DATA0_[7:0]

DATA1_[7:0]

A[7:0]

B[7:0]

CIQ[7:0]

DSWST

HST[7:0]

RESULT[7:0]

ENABLE

Q[7:0]

DSI[7:0]

CLK

CLOCK

HST[7:2]

Q[5:0]

DSI[7:2]

DATA[5:0]

BUF1

DSIW

CLK

DSL

REG2

REG4

BUF

REG7

EN2

EN1

BUF2

DSWST

VDD

ENABLE

ACLR

DSLA

DFME8

HA0

BUF

CLK

CLOCK

HI[15:8]

HST[14:8]

A[7:0]

B[7:0]

CIQ[15:8]

Q[6:0]

Q[7:0]

DSI[14:8]

DSI[15:8]

DATA[6:0]

HST14

MUX2

IQ[15:8]

MUX2X8

HICTLA

HO[15:8]

DATA0_[7:0]

DATA1_[7:0]

RESULT[7:0]

ENHD1

ENHD2

SINT

ENHD2

SINT

HST[1:0]

DPNT[1:0]

HST[15:8]

HSEL

HWR

HRD

HA0

HSEL

HWR

HRD

HA0

EN1

EN2

EN1

EN2

HRDY

HST15

DSPINTR

HCMDFL

DSPINTR

HCMDFL

DSIW

CLK

DSIW

HA0

HICTLA

HWR

HSEL

HG1

HG2

NAND2

HOST INTERFACE

(HINTRFA)

AND2B

DF1

DF1C

CLK

NAND2

CLK

24 OCT 2002

DBS

DRAWN BY:

INV1

HRD

F13

INV

HCYC

LWR

HWR

HRD

JKF2C

HCYC

GND

CLK

VDD

DF1

OA1C

HSEL

CLR

DFM6A

CLK

CLR

HWR

VCC

HSEL

HWR

SHWR

AND2B

HSEL

HCYC

INV3

INV

HCYC

HCMD

JKF2C

CLK

VDD

CLR

HSEL

HWR

HA0

SHCMD

AND3B

INV4

HCYC

LRDST

INV

JKF2C

CLK

VDD

CLR

G10

HSEL

HRD

HA0

SLRDST

AND3B

INV2

DSPINTR

INV

HWR

EN2

EN1

ENHD2

G21

NOR2

NAND2

DSIW

HRDY

NOR4

F10

NOR2

ENHD1

DF1

NAND2

CLK

DPNT[1:0]

DPNT0

DPNT1

LWR

RDEN

WREN

NAND3B

NAND2B

HCYC

INTEN

EBSY

OR3C

OA4

DSPINTR

SINT

CLRFLGS

SINTR

AND3

JKF

CLK

LRDST

HCYC

AND2A

G19

HCYC

HCMD

HCCYC

HCMDFL

AND2

JKF

CLK

HICTLA

DSIW

CLRFLGS

INV

21 OCT 2002

DBS

DRAWN BY:

DSI[7:0]

DSI0

PNT0

PNT1

PNT2

PP4

PP6

DFE1B

AND3B

AND3A

CLK

DSI1

DFE1B

CLK

DSDWSPI2NT

CLK

DFE1B

CLK

CPCYC

ADW0

DEC2

DSWPNT

NAND2

DECE2X4D

LA0

LR/W

LA1

ADW2

ADW3

R/W

LR/W

DL1B

DG3

G11

CPCYC1

PP4

DSIW

AND3

ADW2

CPCYC1

PP4

G12

DSWST

ADW3

ADW0

LR/W

VCC

DSWDREG

AND4B

CPCYC1

PP6

DFE3A

CLK

CLR

INV

BUF2

CPCYC

BUF

GND

INV

BUF3

CPCYC1

BUF

DFM6A

CPS

DSPWA

CPIS

CLK

CLR

VCC

CPSTRB

CPSEL

CPS

AND3B

CLK

24 OCT 2002

DBS

DRAWN BY:

ST0

CH0

BUF

ST15

CH15

BUF

MUX2X16

CH15,GND,GND,GND[12:1],CH0

IQ[15:0]

DO[15:0]

DATA0_[15:0]

DATA1_[15:0]

RESULT[15:0]

GND[12:1]

BUF

$ARRAY=12

LA0

LA1

IQSEL

OR2

GND

DSPRA

24 OCT 2002

DBS

DRAWN BY:

A[7:0]

B[7:0]

EN1

Q[7:0]

DFME8

19 NOV. 2002

DBS

DRAWN BY:

MUX1

MUX4X8

EN1R1

DSPSEL

HI[7:0]

EN1

EN1R3

EN1

CIQ[7:0]

R1[7:0]

DFME8

DSPSEL2

HI[7:0]

DFME8

DATA0_[7:0]

IQ[7:0]

DATA1_[7:0]

DATA2_[7:0]

DATA3_[7:0]

A[7:0]

B[7:0]

EN1

R1[7:0]

RESULT[7:0]

Q[7:0]

A[7:0]

B[7:0]

R3[7:0]

R2[7:0]

R3[7:0]

Q[7:0]

DSI[7:0]

EN2R1

EN2R3

EN1

DFME8

CLK

DFME8

HIH[15:8]

CLK

A[7:0]

B[7:0]

R1[15:8]

Q[7:0]

HIH[15:8]

MDS1

MDS0

A[7:0]

B[7:0]

R3[15:8]

DSI[15:8]

Q[7:0]

DSI[15:8]

MUX2

MUX4X8

LA0

EN1R2

EN1

LA1

DSIR

CIQ[15:8]

R1[15:8]

AND4A

PP4

DOE1

DSPSEL1

HI[7:0]

DFME8

DATA0_[7:0]

DATA1_[7:0]

DATA2_[7:0]

DATA3_[7:0]

IQ[15:8]

RA0

RA1

RESULT[7:0]

A[7:0]

B[7:0]

R2[7:0]

R2[15:8]

R3[15:8]

Q[7:0]

MDS0

MDS1

MX2

DSI[7:0]

GND

EN2R2

EN1

DEC1

DATA0

GND

DECE2X4

EQ0

DFME8

EN1R1

EN1R2

EN1R3

DATA1

EQ1

EQ2

EQ3

CLK

HIH[15:8]

MDS1

MDS0

A[7:0]

B[7:0]

R2[15:8]

Q[7:0]

DSI[15:8]

LA[1:0]

END1

ENABLE

PP6

DSPSEL

DSPSEL1

DSPSEL2

BUF

RA[1:0]

DEC2

DECE2X4

RA0

RA1

DATA0

DATA1

EQ0

EQ1

EQ2

EQ3

EN2R1

EN2R2

EN2R3

DATREG

END2

ENABLE

24 OCT 2002

DBS

DRAWN BY:

6.3 8-bit Host Interface (IOPIL8)

This design implements a parallel interface with a host processor utilizing an 8-bit data bus. An

understanding of the underlying operation of the design is only necessary if the designer intends to

make modifications. In most cases this design can be implemented without changes. The following

notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The

timing for the host to I/O chip communication can be found in section 4.4 and the timing for the

CP to I/O chip communication can be found in section 4.7.

The description below identifies the key elements of each schematic starting with the host side

signals. The paragraph title identifies the key schematic(s) being described in the text.

IOPIL8 3

The host interface for IOPIL8 is shown in sheet IOPIL8 3. The incoming data HD[7:0] is latched in

the transparent latches when ~HG1 goes high. This would be a write from the host to the CP. The

latched data HI[7:0] goes to IOPIL8 1 and IOPIL8 5. Data from the interface to the host, HO[7:0]

is enabled onto the host bus, HD[7:0], by HOES1. The output latches, which present the data

during a host read, are always transparent because GOUT is connected to VDD. The latched I/O is

an I/O option on the Actel part used and could be omitted in the host interface if a different CPLD

or FPGA does not have this feature. HD[15:8] are tri-stated outputs because Actel grounds unused

I/O pins and this would interfere with using existing PMD test equipment. These reserved I/O's can

be ommitted in a different implementation with an 8 bit bus.

IOPIL8 1

The control for the host interface starts on IOPIL8 1. HOES1 is the AND of ~HSEL and ~HRD,

and enable read data onto the host bus, as previously described. HRDY is a handshaking signal to

the host to allow asynchronous communication between the host and the CP. The host must wait

until HRDY is true before attempting to communicate with the CP. This signal is copied as a bit in

the host status register. The host status register may be read at any time to determine the state of

HRDY, or the HRDY output may be used as an interrupt to the host. ~HSEL, ~HRD, ~HWR, and

HA0 are the buffered inputs of the host control signals.

HOST INTERFACE/IOPIL8 5

Data from the host HI[7:0] is written into REG1 and REG2 on the schematic HOST INTERFACE

by ~EN1 and ~EN2. All transfers are 16 bits and take two writes or reads on the 8-bit bus. These

registers have a 2 to 1 multiplexed input with both the host data and the CP data being written to this

This is convenient for diagnostic purposes and is very efficient in the Actel A42MX FPGA's, which

are multiplexer based but if the configuration of the logic device used demands it, separate registers

could be used for the host and CP data. The schematic for this register is shown as DFME8. Only

commands and checksums are written to registers REG1 and REG2 while data is written and read

from the set of data registers, DATREG shown on IOPIL8 5. These 3 data registers buffer data sent

to and from the CP, reducing the number of interrupts the CP must handle. The output from REG1

and REG2, CIQ[15:8] and CIQ[7:0] go to IOPIL8 5, where they are multiplexed with the other data

registers. The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] -

the output of the host status registers REG3 and REG4. This four input mux, MUX4X8, also

muxes the 16 bit data onto the 8-bit bus. As previously mentioned HRDY becomes HST15 so it can

be read by the host. The rest of the status register is written by the CP to provide information to the

MC3310 Technical Specifications

host. HA0 acts as an address bit, and usually is an address bit on the bus. When the host is writing,

HA0 low indicates data and HA0 high indicates a command. When the host is reading, HAO low

indicates data and HA0 high indicates status. Read status is the only transaction allowed while

HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two flops latch the

incoming data in the interface latches by driving ~HG1 low from the start of the write transaction

until the first negative clock transition after the first positive transition following the start of the write

cycle. This tail-biting circuit removes the requirement for hold time on the data bus.

HICTLA

Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at

the top generates HCYC one clock interval after the interface has been accessed and the host has

finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is

preserved in the three flops F13, F8, and F9. Since 16 bit transfers must take place over an 8 bit bus

two transfers are required. The toggle flop is used to determine whether a cycle is the first or second

of the 2 required. The toggle flop may be initialized to the 0 state, which indicates that this is the

first transfer (high byte), by the CP writing a one to host status bit 15. This status bit is read by the

host as the HRDY bit and is not writable by the CP. In addition flop F12 and the associated gating

determine if the present command transaction is the first or second byte of a command. If the

toggle flop gets into the wrong state due to a missed or aborted transfer the next command will set it

back to the correct state. A host write or a CP write, DSIW, enable REG1 and REG2 on the HOST

INTERFACE schematic discussed previously. A host data write generates ~ENHD1 and

~ENHD2 for the data registers on the DATAREG schematic. For host writes ~EN2, ~EN1,

~ENHD2, and ~ENHD1 are also determined by the state of the toggle flop using HIEN and

LOEN. 1CMD is used in this logic to ensure correct behavior when the command is correcting the

state of the toggle. The logic at the bottom of the page generates the CP interrupt, the HRDY and

the HCMDFL. The HCMDFL is used in the CP status to indicate a command. DSIW, the CP

writing to REG1 and REG2 on the HOST INTERFACE schematic clears the interrupt and reasserts

HRDY. HRDY is de-asserted during all host transactions except read status, and stays de-asserted

until the CP has completed the DSIW cycle that clears the interrupt and reasserts HRDY. As

mentioned previously data transfers to and from the host use the data registers and do not interrupt

the CP. The CP knows the number of data transfers that must take place after decoding the

command. It places this number, 0-3, in the 2 least significant bits of the host status register,

HST[1:0]. These become DPNT[1:0] on this page of the schematic and enable an interrupt at 0 for a

read and 1 or 0 for a write. The CP always leaves these bits at 0 unless setting up a multiple word

data transfer. If INTEN is true and LRDST, latched read status, is false, HCYC will generate an

interrupt to the CP. This will also hold HRDY false until after the CP writes to the interface register,

DSIW, thereby generating ~CLRFLGS.

IOPIL8 4

The CP interface is shown in sheet IOPIL8 4. The incoming data DSD[15:0] is latched in the

transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from

the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL8 1 and

IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and

DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output

latches, which present the data during a CP read, are always transparent because GOUT is connected

to VDD. The latched I/O in the Actel part contains both input and output latches. The output

latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature.

The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal

is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.

MC3310 Technical Specifications

IOPIL8 2

The CP control starts on IOPIL8 2. The I/O control is generated from ~CPSTRB, ~CPIS, CPSEL

and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out-enable

the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold times

on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be used for

this interface and the CP.