FAN73832MX [FREESCALE]
Half-Bridge Gate-Drive IC; 半桥栅极驱动器IC
| 型号： | FAN73832MX |
| 厂家： | 
Freescale |
| 描述： | Half-Bridge Gate-Drive IC |
| 文件： | 总16页 (文件大小：1115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2006
FAN73832
Half-Bridge Gate-Drive IC
Features
Description
Floating Channel for Bootstrap Operation to +600V
The FAN73832 is a half-bridge, gate-drive IC with shut-
down and programmable dead-time control functions for
driving MOSFETs and IGBTs, operating up to +600V.
Typically 350mA/650mA Sourcing/Sinking Current
Driving Capability for Both Channels
Extended Allowable Negative VS Swing to -9.8V for
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side driver under high dv/dt noise circumstances.
Signal Propagation at VDD=VBS=15V
High-Side Output in Phase of IN Input Signal
Built-in UVLO Functions for Both Channels
An advanced level-shift circuit allows high-side gate
driver operation up to VS=-9.8V (typical) for VBS=15V.
Built-in Common-Mode dv/dt Noise Canceling Circuit
Internal 400nsec Minimum Dead-Time at RDT=20KΩ
Programmable Turn-on Delay-Time Control
The UVLO circuits for both channels prevent malfunction
when VDD and VBS are lower than the specified thresh-
old voltage.
(Dead-Time)
Output drivers typically source/sink 350mA/650mA,
respectively, which is suitable for all kinds of half- and
full-bridge inverters.
Applications
SMPS
Motor Drive Inverter
Fluorescent Lamp Ballast
HID Ballast
8 SOP
8-DIP
Ordering Information
Part Number
FAN73832M(1)
FAN73832MX(1)
FAN73832N
Package
8-SOP
Pb-Free
Operating Temperature Range Packing Method
Tube
Yes
-40°C ~ 125°C
Tape & Reel
Tube
8-DIP
Note:
1. These devices passed wave soldering test by JESD22A-111.
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
Typical Application Diagrams
DBOOT
VDC
VDD
IN
1
2
3
4
8
7
6
5
VB
PWM
HO
GND
CBOOT
VS
DT/SD
VDD
PWM IC
Shutdown
LO
RDT
Control
FAN73832
FAN73832 Rev:00
Figure 1. Application Circuit for Half-Bridge Switching Power Supply
VDC
VCC
VDD
VDD
VB
VB
HO
HO
IN
VS
PHA
PHB
SD
Forward
VS
IN
M
FAN73832
FAN73832
Reverse
DC Motor
Controller
LO
LO
DT/
DT/
SD
SD
GND
GND
FAN73832 Rev:00
Figure 2. Application Circuit for Full-Bridge DC Motor Driver
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
2
Internal Block Diagram
8
7
VB
UVLO
HO
R
R
NOISE
CANCELLER
S
Q
6
4
VS
HS(ON/OFF)
1
3
IN
SCHMITT
TRIGGER INPUT
UVLO
VDD
RDTINT
LS(ON/OFF)
DEAD- TIME
CONTROL
DELAY
LO
DT/
5
2
SD
GND
FAN73832 Rev:00
Figure 3. Functional Block Diagram of FAN73832
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
3
Pin Assignments
IN
GND
DT/SD
VDD
VB
HO
VS
1
2
3
4
8
7
6
5
LO
FAN73832 Rev:00
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
2
3
4
5
6
7
8
IN
Logic Input
GND
DT/SD
Ground
Dead-Time Control with External Resistor and Shutdown Function
Low-Side Supply Voltage
V
DD
LO
Low-Side Driver Output
V
High-Side Floating Supply Return
High-Side Driver Output
S
HO
V
High-Side Floating Supply
B
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
4
Absolute Maximum Ratings
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are
not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the condi-
tions for actual device operation. T =25°C unless otherwise specified.
A
Symbol
Characteristics
High-side offset voltage
Min.
Max.
Unit
V
V
V -25
V +0.3
V
S
B
B
High-side floating supply voltage
High-side floating output voltage HO
Low-side and logic-fixed supply voltage
Low-side output voltage LO
-0.3
625
V
B
V
V
V -0.3
V +0.3
V
HO
DD
S
B
-0.3
-0.3
-0.3
-0.3
25
V
V
V
V
+0.3
+0.3
V
LO
DD
DD
V
Logic input voltage (IN)
V
V
IN
V
Dead-time and shutdown control voltage
Logic ground
5.0
DT/SD
GND
V
-25
V
+0.3
V
DD
DD
dV /dt
Allowable offset voltage slew rate
50
V/nsec
W
S
8-SOP
8-DIP
8-SOP
8-DIP
0.625
1.25
200
(2)(3)(4)
D
P
Power dissipation
θ
Thermal resistance, junction-to-ambient
°C/W
JA
100
T
Junction temperature
Storage temperature
150
°C
°C
J
T
150
STG
Notes:
2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
3. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - Natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
4. Do not exceed P under any circumstances.
D
Recommended Operating Conditions
Symbol
Parameter
High-side floating supply voltage
High-side floating supply offset voltage
Low-side supply voltage
Condition
Min.
V +15
Max.
Unit
V
V
V +20
V
V
B
S
S
6-V
600
20
S
DD
V
V
15
V
DD
HO
High-side (HO) output voltage
Low-side (LO) output voltage
Logic input voltage (IN)
V
V
V
S
B
V
GND
GND
-40
V
V
V
LO
DD
DD
V
V
IN
T
Ambient temperature
125
°C
A
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
5
Electrical Characteristics
V
(V , V )=15.0V, R =20KΩ,T =25°C, unless otherwise specified. The V and I parameters are referenced
BIAS
DD BS DT A IN IN
to GND. The V and I parameters are referenced to GND and V is applicable to HO and LO.
O
O
S
Symbol
Characteristics
Test Condition
Min. Typ. Max. Unit
SUPPLY CURRENT SECTION
I
I
Quiescent V supply current
V =0V or 5V
35
90
QBS
BS
IN
Quiescent V supply current
V =0V or 5V, R =20KΩ
300
650
400
650
450
900
700
850
10
QDD
(4)
DD
IN
DT
I
Shutdown supply current
DT/SD=GND
SD
µA
I
Operating V supply current
f =20kHz, rms value
IN
PBS
BS
I
Operating V supply current
f =20kHz, rms value
IN
PDD
DD
I
Offset supply leakage current
V =V =600V
LK
B
S
POWER SUPPLY SECTION
and V supply under-voltage
V
V
DD
DDUV+
BS
10.7
10.0
11.6
10.8
0.8
12.5
11.6
V
V
V
V
positive going threshold
BSUV+
V
V
DD
and V supply under-voltage
DDUV-
BS
V
negative going threshold
BSUV-
V
V
DD
supply under-voltage lockout
DDUVH
V
hysteresis
DEAD-TIME CONTROL SECTION
Internal dead-time setting resistance
Normal voltage at DT
GATE DRIVER OUTPUT SECTION
High-level output voltage, V
BSUVH
R
20
KΩ
DTINT
V
R
=20KΩ
3.0
V
DT
DT
V
-V
I =20mA
1.0
0.6
V
V
OH
BIAS
O
O
V
Low-level output voltage, V
O
OL
O+
I
Output high short-circuit pulse current V =0V, V =5V with PW<10µs 250
350
650
mA
O
IN
V =15V,
O
I
Output low short-circuit pulsed current
500
mA
V
O-
V =0V with PW<10µs
IN
Allowable negative V pin voltage for
IN signal propagation to HO
S
V
-9.8
-7.0
S
LOGIC INPUT SECTION (INPUT and SHUTDOWN)
V
Logic "1" input voltage
2.9
V
V
IH
V
Logic "0" input voltage
1.2
100
2.0
1.2
IL
I
Logic "1" input bias current
Logic "0" input bias current
Shutdown "1" input voltage
Shutdown "0" input voltage
Input pull-down resistance
V =5V
50
µA
µA
V
IN+
IN
I
V =0V
IN
IN-
SD+
SD-
2.9
V
R
100
KΩ
PD
Note:
4. This parameter, although guaranteed, is not 100% tested in production.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN73832 Rev. 1.0.0
6
Dynamic Electrical Characteristics
V
(V , V )=15.0V, V =GND, C =1000pF, R =20KΩ and T = 25°C, unless otherwise specified.
BIAS
DD
BS
S
L
DT
A
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
t
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
V =0V, R =20KΩ
580
180
50
730
230
100
80
ON
S
DT
t
V =0V, R =20KΩ
S DT
OFF
t
C =1000pF
L
R
t
Turn-off fall time
C =1000pF
30
F
L
(5)
SD
nsec
t
Shutdown propagation delay
100
400
1.68
0
180
500
2.30
60
R
R
R
R
=20KΩ
300
Dead-time LO OFF to HO ON & HO
OFF to LO ON
DT
DT
DT
DT
DT1, DT2
= 200KΩ
= 20KΩ
=200KΩ
1.20
DMT
Dead-time matching
0
150
Note:
5. This parameter, although guaranteed, is not 100% tested in production.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN73832 Rev. 1.0.0
7
Typical Characteristics
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
12.0
11.8
11.6
11.4
11.2
11.0
10.8
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 5. VDD/VDD UVLO (+) vs. Temperature
Figure 6. VDD/VBS UVLO (-) vs. Temperature
100
80
60
40
20
0
500
400
300
200
100
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 7. VDD Quiescent Current vs. Temperature
Figure 8. VBS Quiescent Current vs. Temperature
1000
800
600
400
200
0
800
600
400
200
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 9. VDD Operating Current vs. Temperature
Figure 10. VBS Operating Current vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
8
Typical Characteristics (Continued)
100
80
60
40
20
0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 11. Logic Input Current vs. Temperature
Figure 12. Logic Input High Voltage vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 13. Logic Input Low Voltage vs. Temperature
Figure 14. SD Positive Threshold vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0.0
800
600
400
200
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 15. SD Negative Threshold vs. Temperature
Figure 16. Turn-on Delay Time vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
9
Typical Characteristics (Continued)
500
450
400
350
300
300
250
200
150
100
50
0
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 17. Turn-off Delay Time vs. Temperature
Figure 18. Dead Time (RDT=20kΩ) vs. Temperature
2.0
1.6
1.2
0.8
0.4
0.0
2.4
2.2
2.0
1.8
1.6
1.4
1.2
20
40
60
80
100 120 140 160 180 200
RDT [kohm]
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 19. Dead Time (RDT=200kΩ) vs. Temperature
Figure 20. RDT vs. Dead Time
-6
-8
-10
-12
-14
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 21. Allowable Negative VS Voltage for Signal
Propagation to High Side vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
10
Switching Time Definitions
10μF 100nF
+15V
10μF 100nF
+15V
IN
1
2
3
4
8
7
6
5
VB
HO
GND
DT/SD
VDD
HO
1nF
VS
SD
LO
20K
Control
LO
FAN73832
1nF
FAN73832 Rev:00
Figure 22. Switching Time Test Circuit
IN
HO
LO
DT/SD
Shutdown
Shutdown
DT1
DT2
DT2
DT1
DT1
FAN73832 Rev.00
Figure 23. Input / Output Waveforms
50%
IN
50%
tOFF
90%
tON
LO
10%
90%
tON
HO
tOFF
10%
FAN73832 Rev.00
Figure 24. Switching Time Waveform Definitions
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
11
50%
DT/SD
90%
HO or LO
tSD
FAN73832 Rev.00
Figure 25. Shutdown Waveform Definition
90%
HO
LO
10%
DT1
DT2
90%
MDT= |DT1 - DT2|
10%
FAN73832 Rev.00
Figure 26. Dead-Time Control Waveform Definition
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
12
Typical Application Information
1. Normal Operating Consideration
3. Layout Consideration
The FAN73832 is a single PWM input, half-bridge, gate-
drive IC with programmable dead-time and shutdown
functions.
For optimum performance of the high- and low-side gate
drivers, considerations must be taken during printed
circuit board (PCB) layout.
The dead-time is set with a resistor (R ) at the DT/SD
3.1 Supply Capacitors
DT
pin. The wide dead-time programming range provides
the flexibility to optimize drive signal timing for a
selection of switching devices (MOSFET or IGBT) and
applications.
If the output stages are able to quickly turn-on a
switching device with a high value of current, the supply
capacitors must be placed as close as possible to the
device pins (V and GND for the ground-tied supply, V
DD
B
The turn-on time delay circuitry (Dead-Time)
and V for the floating supply) to minimize parasitic
S
accommodates resistor values from 20kΩ to 200kΩ with
inductance and resistance.
a dead-time proportional to the R resistance.
DT
3.2 Gate Drive Loop
If the DT/SD pin voltage decreases below 1.2V in the
normal operation, the IC enters shutdown mode.
Current loops behave like an antenna, able to receive
and transmit noise. To reduce the noise coupling/emis-
sion and improve the power switch turn-on and off per-
formances, gate drive loops must be reduced as much
as possible.
The external dead-time setting resistor (R ) is at least
DT
above 20KΩ for normal operation in typical applications.
2. Under Voltage Lockout (UVLO)
3.3 Ground Plane
The FAN73832 has an under-voltage lockout (UVLO)
protection circuit for high- and low-side channels to
Ground plane must not be placed under or nearby the
high-voltage floating side to minimize noise coupling.
prevent malfunction when V
and V are lower than
DD
BS
the specified threshold voltage. The UVLO circuitry
monitors the supply voltage (V and bootstrap
)
DD
capacitor voltage (V ) indepently.
BS
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
13
Mechanical Dimensions
8-SOP
Dimensions are in millimeters (inches) unless otherwise noted.
0.1~0.25
0.004~0.001
MIN
1.55 0.20
0.061 0.008
#8
#5
#1
#4
6.00 0.30
0.236 0.012
1.80
0.071
MAX
3.95 0.20
0.156 0.008
5.72
0.225
0.50 0.20
0.020 0.008
January 2001, Rev. A
8sop225_dim.pdf
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
14
Mechanical Dimensions (Continued)
8-DIP
Dimensions are in millimeters (inches) unless otherwise noted.
6.40 0.20
0.252 0.008
#1
#4
#8
#5
3.30 0.30
0.130 0.012
5.08
0.200
MAX
7.62
0.300
3.40 0.20
0.134 0.008
0.33
0.013
MIN
+0.10
–0.05
0.25
+0.004
–0.002
0.010
°
0~15
September 1999, Rev B
pdip8_dim.pdf
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
15
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As used herein:
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which, (a) are intended for surgical implant into the body or
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when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life
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effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without
notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data; supplementary data will
be published at a later date. Fairchild Semiconductor reserves the
right to make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at any time
without notice to improve design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed
for reference information only.
Rev. I20
© 2006 Fairchild Semiconductor Corporation
FAN73832 Rev. 1.0.0
www.fairchildsemi.com
16
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