FAN7384 [FAIRCHILD]
Half-Bridge Gate-Drive IC; 半桥栅极驱动器IC
| 型号： | FAN7384 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Half-Bridge Gate-Drive IC |
| 文件： | 总17页 (文件大小：1803K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2007
FAN7384
Half-Bridge Gate-Drive IC
Features
Description
Floating Channel for Bootstrap Operation to +600V
The FAN7384 is a monolithic half-bridge gate-drive IC
designed for high voltage, high speed driving MOSFETs
and IGBTs operating up to +600V.
Typically 250mA/500mA Sourcing/Sinking Current
Driving Capability for Both Channels
Extended Allowable Negative VS Swing to -9.8V for
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side drivers under high-dv/dt noise circumstances.
Signal Propagation at VDD=VBS=15V
Matched Propagation Delay Below 50ns
Output In-Phase with Input Signal
An advanced level-shift circuit allows high-side gate
driver operation up to VS = -9.8V (typical) for VBS =15V.
3.3V and 5V Input Logic Compatible
Built-in Shoot-Through Prevention Logic
Built-in Common Mode dv/dt Noise Canceling Circuit
Built-in UVLO Functions for Both Channels
Built-in Cycle-by-Cycle Shutdown Function
Built-in Soft-Off Function
The UVLO circuits prevent malfunction when VDD and
VBS are lower than the specified threshold voltage.
Output drivers typically source/sink 250mA/500mA,
respectively, which is suitable for half-bridge and full-
bridge applications in motor drive systems.
Built-in Bi-Directional Fault Function
Built-in Short-Circuit Protection Function
14-SOP
Applications
Motor Inverter Driver
Normal Half-Bridge and Full-Bridge Driver
Switching Mode Power Supply
Ordering Information
Operating Temperature
Part Number
FAN7384M(1)
FAN7384MX(1)
Package
Pb-Free
Range
Packing Method
Tube
14-SOP
Yes
-40°C ~ 125°C
Tape & Reel
Note:
1. These devices passed wave soldering test by JESD22A-111.
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
Typical Application Diagrams
VDC
VCC
VDD
VDD
VB
VDD
HO
HO
HO
U
VS
U
VB
VS
UU
UL
HIN
LIN
V
VU
UL
3-Phase
Motor
Controller
V
HIN
LIN
W
VB
VS
WU
WL
HIN
LIN
FO
W
FO
SD
FO
SD
SD
LO
LO
LO
CSC
CSC
CSC
GND
GND
GND
VSL
VSL
VSL
FAN7384 Rev.02
Figure 1. 3-Phase Motor Drive Application
VDC
VCC
VDD
VB
VDD
VB
HO
HO
LIN
VS
PHA
PHB
Forward
HIN
VS
LIN
HIN
FO
FO
M
FAULT
SHUTDOWN
SD
Reverse
SD
LO
LO
DC Motor
Controller
VSL
CSC
VSL
CSC
FAN7384 Rev.01
Figure 2. DC Motor Drive Application
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
2
Internal Block Diagram
14 VB
13 HO
12 VS
UVLO
R
R
S
NOISE
CANCELLER
HS(ON/OFF)
Q
SCHMITT
LIN
HIN
SD
1
3
2
TRIGGER INPUT
VDD_UVLO
UVLO
4
9
8
VDD
LO
VSL
SHOOT-THROUGH
PREVENTION
GND/VSL
LS(ON/OFF)
DELAY
LEVEL SHIFTER
CONTROL LOGIC
FAULT
LOGIC
SOFT-OFF
ISOFT
CSC
GND
6
7
ONE-SHOT
TRIGGER
ONE-SHOT
TRIGGER
0.5V
5
FO
V
DD_UVLO
FAN7384 Rev.03
Figure 3. Functional Block Diagram
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
3
Pin Configuration
LIN
SD
1
2
3
4
5
6
7
14
13
12
11
10
9
VB
HO
VS
HIN
VDD
NC
NC
LO
VSL
FO
CSC
GND
8
FAN7384 Rev.00
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
1
Name
Description
LIN
SD
Logic Input for low-side gate driver
Shutdown control input with active low
Logic Input for high-side gate driver
Low-side power supply voltage
Bi-direction fault pin with open drain
Short-circuit current detection input
Ground
2
3
HIN
VDD
FO
4
5
6
CSC
GND
VSL
LO
7
8
Low-side supply offset voltage
Low-side gate driver output
No connection
9
10
11
12
13
14
NC
NC
No connection
VS
High-side floating supply offset voltage
High-side gate driver output
High-side floating supply voltage
HO
VB
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
VS
Parameter
High-side offset voltage VS
Min.
VB-25
-0.3
Max.
VB+0.3
625
Unit
V
VB
High-side floating supply voltage VB
High-side floating output voltage
Low-side and logic-fixed supply voltage
Logic input voltage (HIN, LIN, SD)
Current sense input voltage
Fault output voltage
V
VHO
VS-0.3
-0.3
VB+0.3
25
V
VDD
V
VIN
-0.3
VDD+0.3
VDD+0.3
VDD+0.3
50
V
VCSC
VFO
-0.3
V
-0.3
V
dVS/dt
Allowable offset voltage slew rate
Power dissipation
V/ns
W
(2)(3)(4)
PD
1.0
θJA
TJ
Thermal resistance, junction-to-ambient
Junction temperature
110
°C/W
°C
°C
150
TS
Storage temperature
-55
150
Notes:
2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
3. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
4. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VB
Parameter
High-side floating supply voltage
High-side floating supply offset voltage
Supply voltage
Condition
Min.
VS+13
6-VDD
13
Max.
VS+20
600
Unit
V
VS
V
VDD
VHO
VLO
VIN
20
V
High-side output voltage
Low-side output voltage
Logic input voltage (HIN, LIN, SD)
Fault output voltage
VS
VB
V
GND
GND
-0.3
VDD
V
VDD
V
VFO
TA
VDD+0.3
125
V
Ambient temperature
-40
°C
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
5
Electrical Characteristics
VBIAS (VDD, VBS) = 15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND.
The VO and IO parameters are referenced to GND and VS is applicable to HO and LO.
Symbol
Characteristics
Condition
Min. Typ. Max. Unit
LOW SIDE POWER SUPPLY SECTION
IQDD
IPDD
Quiescent VDD supply current
Operating VDD supply current
VLIN=0V or 5V
fLIN=20kHz, rms value
600 800
μA
950 1300 μA
VDD supply under-voltage positive going
threshold
VDDUV+
VDDUV-
VDDHYS
V
DD=Sweep
10.9 11.9 12.9
V
V
V
VDD supply under-voltage negative going
threshold
VDD=Sweep
VDD=Sweep
10.4 11.4 12.4
0.5
VDD supply under-voltage lockout
hysteresis
BOOTSTRAPPED POWER SUPPLY SECTION
VBS supply under-voltage positive going
threshold
VBSUV+
V
BS=Sweep
10.6 11.5 12.4
10.1 11.0 11.9
V
V
V
VBS supply under-voltage negative going
threshold
VBSUV-
VBS=Sweep
VBS=Sweep
VBS supply under-voltage lockout
hysteresis
VBSHYS
0.5
ILK
Offset supply leakage current
Quiescent VBS supply current
Operating VBS supply current
VB=VS=600V
10
90
400 600
μA
μA
μA
IQBS
IPBS
VHIN=0V or 5V
50
fHIN=20kHz, rms value
GATE DRIVER OUTPUT SECTION
VOH
VOL
IO+
High-level output voltage, VBIAS-VO
IO=0mA (No Load)
100 mV
100 mV
mA
Low-level output voltage, VO
IO=0mA (No Load)
Output HIGH short-circuit pulse current
VO=0V, VIN=5V with PW<10µs
200 250
420 500
IO-
Output LOW short-circuit pulsed current VO=15V, VIN=0V with PW<10µs
mA
Allowable negative VS pin voltage for IN
signal propagation to HO
VS
-9.8 -7.0
V
V
V
SL-GND VSL-GND/GND-VSL voltage educability
-7.0
7.0
1.2
SHUTDOWN CONTROL SECTION (SD)
SD+
SD-
Shutdown "1" input voltage
Shutdown "0" input voltage
V
V
2.5
2.5
0.5
LOGIC INPUT SECTION (HIN, LIN)
VIH
VIL
Logic "1" input voltage
Logic "0" input voltage
V
V
1.2
VINHYS Logic input hysteresis voltage
V
IIN+
IIN-
Logic "1" input bias current
Logic "0" input bias current
VIN=5V
VIN=0V
10
15
20
μA
μA
2.0
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
VBIAS (VDD, VBS) = 15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND.
The VO and IO parameters are referenced to GND and VS is applicable to HO and LO.
Symbol
Characteristics
Condition
Min. Typ. Max. Unit
SHORT-CIRCUIT PROTECTION
VCSCREF Short-circuit detector reference voltage
ICSCIN Short-circuit input current
0.47 0.50 0.53
V
VCSCIN=1V, RCSCIN=100KΩ
5
5
10
10
15
15
μA
mA
ISOFT
Soft turn-off source current
VDD=15V
Voltage on CSC pin up to -12V,
Time<2μs
-VCSC Negative CSC pin immunity(5)
-20
1.2
V
FAULT DETECTION SECTION
VFINH
VFINL
Fault input high level voltage
2.5
4.7
V
Fault input low level voltage
V
VFINHYS Fault input hysteresis voltage(5)
0.5
60
V
VFOH
VFOL
tFO
Fault output high level voltage
Fault output low level voltage
Fault output pulse width
VCSC=0V, RPULL-UP=4.7KΩ
VCSC=1V, IFO=2mA
VCSCIN=1V
V
0.8
V
100
µs
Note:
5. These parameters, although guaranteed, not 100% tested in production.
Dynamic Electrical Characteristics
TA=25°C, VBIAS (VDD, VBS) = 15.0V, VS = GND, CLoad = 1000pF unless otherwise specified.
Symbol
Parameter
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Conditions
Min. Typ. Max. Unit
ton
toff
VS=0V
VS=0V
180
170
50
260
240
100
80
ns
ns
ns
ns
ns
ns
µs
ns
ns
tr
tf
Turn-off fall time
30
MT
DT
tUVFLT
Delay matching
50
Dead-time
Under-voltage filtering time(6)
80
120
16
170
tCSCFLT CSC pin filtering time(6)
tCSCFO Time from CSC triggering to FO(6)
300
350
Time from CSC triggering to low-side From VCSC=1V to starting gate
tCSCLO
600
ns
gate output(6)
turn-off
Shutdown to FO propagation delay(6)
60
ns
ns
tSDFO
tSDOFF Shutdown to HIGH/LOW-side gate off(6)
100
Note:
6. These parameters, although guaranteed, not 100% tested in production.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7384 Rev. 1.0.3
7
Typical Characteristics
13.5
13.0
12.5
12.0
11.5
11.0
10.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 5. VDD UVLO (+) vs. Temperature
Figure 6. VDD UVLO (-) vs. Temperature
1.0
13.0
12.5
12.0
11.5
11.0
10.5
10.0
0.8
0.6
0.4
0.2
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 7. VDD UVLO Hysteresis vs. Temperature
Figure 8. VBS UVLO (+) vs. Temperature
12.5
12.0
11.5
11.0
10.5
10.0
9.5
1.0
0.8
0.6
0.4
0.2
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 9. VBS UVLO (-) vs. Temperature
Figure 10. VBS UVLO Hysteresis vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
8
Typical Characteristics (Continued)
1000
800
600
400
200
0
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 11. VDD Quiescent Current vs. Temperature
Figure 12. VBS Quiescent Current vs. Temperature
1000
800
600
400
200
0
1600
1400
1200
1000
800
600
400
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 13. VDD Operating Current vs. Temperature
Figure 14. VBS Operating Current vs. Temperature
30
25
20
15
10
5
20
16
12
8
4
0
-40
0
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 15. Logic Input Current vs. Temperature
Figure 16. ICSCIN vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
9
Typical Characteristics (Continued)
20
15
10
5
120
100
80
60
40
20
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 17. ISOFT vs. Temperature
Figure 18. Turn-on Rising Time vs. Temperature
100
80
60
40
20
0
300
250
200
150
100
50
0
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 19. Turn-off Falling Time vs. Temperature
Figure 20. Turn-on Delay Time vs. Temperature
300
250
200
150
100
50
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 21. Turn-off Delay Time vs. Temperature
Figure 22. Logic Input High Voltage vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
10
Typical Characteristics (Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.0
0.8
0.6
0.4
0.2
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 23. Logic Input Low Voltage vs. Temperature
Figure 24. Logic Input Hysteresis vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 25. SD Positive Threshold vs. Temperature
Figure 26. SD Negative Threshold vs. Temperature
0.60
0.55
0.50
0.45
0.40
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 27. VCSCREF vs. Temperature
Figure 28. Fault Input High Voltage vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
11
Typical Characteristics (Continued)
6.0
5.6
5.2
4.8
1.0
0.8
0.6
0.4
0.2
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 29. Fault Output High Voltage vs.
Temperature
Figure 30. Fault Output Low Voltage vs. Temperature
-7
-8
-9
200
160
120
80
-10
-11
-12
-13
40
0
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 31. Allowable Negative VS Voltage for Signal
Propagation to High Side vs. Temperature
Figure 32. Dead Time vs. Temperature
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
12
Switching Time Definitions
The overall switching timing waveforms definition of FAN7384 as shown Figure 33.
LIN
SD
Shutdown
Disable Skip
Low-Side Output
Disable
Low-Side Output
Disable
UVLO-
VDD
tUVFLT
0.5V
VCSC
tCSCFO
tCSCFO
tFO
tFO
FO
tCSCLO
LO
tCSCLO
Soft-Off
Operating
Soft-Off
Operating
Shutdown
Disable Point
Shutdown
Enable Point
Short-Circuit
Detection Point
Under-Voltage
Detection Point
FAN7384 Rev.03
Figure 33. Switching Timing Waveforms Definition
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
13
Typical Application Information
1. Protection Function
HIN/LIN
LIN/HIN
HO/LO
LO/HO
1.1 Under-Voltage Lockout (UVLO)
The high- and low-side drivers include under-voltage
lockout (UVLO) protection circuitry that monitors the
supply voltage (VDD) and bootstrap capacitor voltage
(VBS) independently. It can be designed to prevent
malfunction when VDD and VBS are lower than the
Shoot-Through Prevent
specified threshold voltage. Moreover, the UVLO
hysteresis prevents chattering during power supply
transitions. If the supply voltage (VDD) maintains an
After DT
under-voltage condition over under-voltage filtering times
(typically 16µs), the fault and soft-off circuits are
activated, as shown Figure 34.
FAN7384 Rev.01
LIN
Figure 36. Waveforms for Shoot-Through Prevention
UVLO+
UVLO-
1.3 Over-Current Protection Function
VDD
The FAN7384 has over-current detection circuitry that
monitors the current-by-current sensing resistor con-
nected from the low-side switch source (VSL) to ground.
tUVFLT
tFO
tCSCFO
FO
It is a built-in time-filler from the over-current event to
prevent malfunction from a noise source, such as lead-
ing-edge pulse in inductive load application, as shown
Figure 37.
90%
LO
tCSCLO
t1
t2
t3
FAN7384 Rev.01
The sensing current is calculated as follows:
Figure 34. Waveforms for Under-Voltage Lockout
VCSCREF
(1)
ICS
=
[ A]
RCS
1.2 Shoot-Through Prevention Function
where,
The FAN7384 has a shoot-through prevention circuitry
that monitors the high- and low-side inputs. It can be
designed to prevent outputs of high- and low-side turning
on at same time, as shown Figure 35 and 36.
VCSCREF: Reference voltage of current sense
comparator
RCS: Current sensing resistor
HIN/LIN
LIN
Low-Side Output
Disable
LIN/HIN
0.5V
VCSC
Shoot-Through Prevent
tCSCFO
tFO
HO/LO
FO
After DT
tCSCLO
LO
Soft-Off
Operating
LO/HO
Short-Circuit
Detection Point
After DT
FAN7384 Rev.03
FAN7384 Rev.00
Figure 35. Waveforms for Shoot-Through Prevention
Figure 37. Waveforms for Short-Circuit Protection
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
14
2.2 Gate-Drive Loop
2. Layout Considerations
For optimum performance, considerations must be taken
during printed circuit board (PCB) layout.
Current loops behave like antennae, able to receive and
transmit noise. To reduce the noise coupling/emission
and improve the power switch turn-on and off perfor-
mance, gate-drive loops must be reduced as much as
possible.
2.1 Supply Capacitors
If the output stages are able to quickly turn on a switch-
ing device with a high value of current, the supply capac-
itors must be placed as close as possible to the device
pins (VDD and GND for the ground-tied supply, VB and
VS for the floating supply) to minimize parasitic induc-
tance and resistance.
2.3 Ground Plane
To minimize noise coupling, the ground plane should not
be placed under or near the high-voltage floating side.
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
15
Package Dimensions
14-SOP
Dimensions are in millimeters unless otherwise noted.
0.05
0.002
MIN
1.55 0.10
0.061 0.004
#14
#1
#8
#7
6.00 0.30
0.236 0.012
1.80
MAX
0.071
3.95 0.20
0.156 0.008
5.72
0.225
0.60 0.20
0.024 0.008
January 2001, Rev. A
Figure 38. 14-Lead Small Outline Package (SOP)
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
16
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE
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LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT
THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
or (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected
to result in significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Advance Information
Product Status
Definition
Formative or In Design
This datasheet contains the design specifications for product develop-
ment. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data, and supplementary data will
be published at a later date. Fairchild Semiconductor reserves the right
to make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to
improve design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild semiconductor. The datasheet is printed for
reference information only.
Rev. I22
© 2006 Fairchild Semiconductor Corporation
FAN7384 Rev. 1.0.3
www.fairchildsemi.com
17
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