FAN73833MX [ONSEMI]
625 V、3.3/5 V 输入逻辑兼容、0.65/0.35 A 灌电流/源电流，具有固定死区时间的半桥式栅极驱动;
| 型号： | FAN73833MX |
| 厂家： | 
ONSEMI |
| 描述： | 625 V、3.3/5 V 输入逻辑兼容、0.65/0.35 A 灌电流/源电流，具有固定死区时间的半桥式栅极驱动 栅极驱动 光电二极管 接口集成电路 |
| 文件： | 总15页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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2013 年 11 月
FAN73833
半桥栅极驱动 IC
特性
说明
浮动通道可实现高达 +600V 的自举运行
FAN73833 是半桥栅极驱动 IC，用于驱动 MOSFET 和
IGBT，工作电压高达 +600V。
两个通道的350 mA/650 mA的典型源电流/灌电流驱动
能力
飞兆的高压流程和共模噪声消除技术可使高端驱动器在高
dv/dt 噪声环境下稳定运行。
将容许负 VS 摆幅扩展至 -9.8V，在当 VDD=VBS=15V 时
的信号传播时
先进的电平转换电路使高侧栅极驱动器在 VBS=15 V 时可
耐受高达 VS=-9.8 V （典型值）时仍然正常工作。
兼容 3.3V 和 5V 逻辑输入电平
输出与输入信号同相
当 VDD 和 VBS 小于指定阈值电压时，两个通道的欠压闭
锁 (UVLO) 电路可防止发生故障。
两个通道均内置欠压闭锁 (UVLO) 功能
内置直通预防电路
输出驱动器的源电流 / 灌电流典型值分别为 350mA/
650mA，适用于各种各样的半桥和全桥逆变器。
内置共模 dv/dt 噪声消除电路
内部死区时间典型值 400 ns
8-SOP
应用
SMPS
电机驱动逆变器
萤光灯镇流器
HID 镇流器
订购信息
器件编号
FAN73833M
FAN73833MX
封装
工作温度范围
-40°C 至 +125°C
包装方法
塑料管
8-SOP
卷带和卷盘
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.2
www.fairchildsemi.com
典型应用电路
Up to 600V
RBOOT DBOOT
VDD
1
2
3
4
8
7
6
5
LIN
HIN
VB
LIN
HIN
HO
VS
CBOOT
VDD
Load
COM
LO
图 1. 半桥应用电路
内部框图
VB
8
7
UVLO
HO
R
R
S
NOISE
CANCELLER
Q
VS
6
3
SCHMITT
TRIGGER INPUT
HS(ON/OFF)
UVLO
2
VDD
HIN
100K
100K
SHOOT-THROUGH
PREVENTION
LS(ON/OFF)
DELAY
LIN
1
5
4
LO
DEAD-TIME
{ 400ns }
COM
图 2. 功能框图
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev.1.0.2
2
引脚布局
1
2
3
4
LIN
HIN
VDD
8
7
6
5
VB
HO
VS
LO
COM
图 3. 引脚布局 （顶视图）
引脚定义
引脚号
名称
LIN
HIN
VDD
COM
LO
说明
1
2
3
4
5
6
7
8
低侧驱动器的逻辑输入
高侧驱动器的逻辑输入
低端电源电压
逻辑接地和低侧驱动器返回
低侧驱动输出
VS
高侧浮动电源返回
高侧驱动输出
HO
VB
高侧浮动电源
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev.1.0.2
3
绝对最大额定值
应力若超过绝对最大额定值，可能会损坏器件。在超出推荐的工作条件的情况下，该器件可能无法正常工作，所以不建
议让器件在这些条件下长期工作。此外，长期在超出推荐的工作条件下工作，会影响器件的可靠性。绝对最大额定值仅
是应力规格值。除非另有规定，否则 TA=25°C。
符号
VS
参数
最小值
VB-25
-0.3
最大值
VB+0.3
625
单位
V
高侧偏置电压
VB
V
高侧浮动电源电压
高侧浮动输出电压 HO
VHO
VDD
VLO
VIN
VS-0.3
-0.3
VB+0.3
25
V
V
低侧和逻辑固定电源电压
低侧输出电压 LO
逻辑输入电压 (HIN/LIN)
逻辑接地和低侧驱动器返回
容许偏置电压变化速率
功耗
-0.3
VDD+0.3
VDD+0.3
VDD+0.3
50
V
-0.3
V
COM
VDD-25
V
dVS/dt
V/ns
W
(1)(2)(3)
PD
0.625
200
θJA
TJ
°C/W
°C
°C
结至环境热阻
150
结温
TSTG
-55
150
存储温度
注意：
1. 安装到 76.2 x 114.3 x 1.6 mm PCB 板 （FR-4 环氧玻璃材料）。
2. 参考以下标准：
JESD51-2: 集成电路热测试方法环境条件 - 自然对流
JESD51-3: 含铅表面贴装封装的低有效导热系数测试板
3. 在任何情况下，都不要超过 PD。
推荐工作条件
推荐的操作条件表明确了器件的真实工作条件。指定推荐的工作条件，以确保器件的最佳性能达到数据表中的规格。
飞兆半导体建议不要超过推荐工作条件，也不能按照绝对最大额定值进行设计。
符号
VB
参数
最小值
VS+11
6-VDD
11
最大值
VS+20
600
单位
V
高侧浮动电源电压
VS
V
高侧浮动电源偏置电压
低侧电源电压
VDD
VHO
VLO
VIN
TA
20
V
VS
VB
V
高侧 (HO) 输出电压
低侧 (LO) 输出电压
逻辑输入电压 (HIN/LIN)
环境温度
COM
COM
-40
VDD
VDD
125
V
V
°C
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev.1.0.2
4
电气特性
除非另有规定，否则 VBIAS (VDD，VBS) = 15.0 V 和 TA=25°C。VIN 和 IIN 参数是以 COM 为参考点的值。VO 和 IO 参数
是以 VS 和 COM 为参考点的值，并分别适用于输出 HO 和 LO。
符号
参数
条件
最小值 典型值 最大值 单位
电源电流部分
IQBS
IQDD
35
80
100
200
750
750
10
µA
µA
µA
µA
µA
静态 VBS 电源电流
VIN=0 V 或 5 V
静态 VDD 电源电流
工作 VBS 电源电流
工作 VDD 电源电流
偏置电源的漏电流
VIN=0 V 或 5 V
IPBS
420
420
fIN=20 kHz， rms 值
fIN=20 kHz， rms 值
VB=VS=600 V
IPDD
ILK
电源部分
VDDUV+
VBSUV+
V
DD 和 VBS 电源欠压正向（电压从高
8.2
7.2
9.2
8.3
0.9
10.1
9.2
V
V
V
到低）阈值
VDDUV-
VBSUV-
VDD 和 VBS 电源欠压负向（电压从低
到高）阈值
VDDUVH
VBSUVH
VDD 电源欠压闭锁滞回电压回差
栅极驱动器输出部分
VOH
VOL
IO=20 mA
1.0
0.6
V
V
高电平输出电压， VBIAS-VO
低电平输出电压， VO
(4)
IO+
250
500
350
650
mA
mA
输出高电平短路脉冲电流
输出低电平短路脉冲电流
V =0 V
，
V =5 V
和
和
PW<10 µs
PW<10 µs
O
IN
(4)
IO-
V =15 V
， V =0 V
O
IN
IN 信号传播到 HO 时允许的 VS 引脚
负电压
VS
-9.8
-7.0
V
逻辑输入部分 （输入和关断）
VIH
VIL
2.5
V
V
逻辑 “1” 输入电压
逻辑 “0” 输入电压
逻辑 “1” 输入偏置电流
逻辑 “0” 输入偏置电流
输入下拉电阻
1.2
100
2.0
IIN+
IIN-
VIN=5 V
VIN=0 V
50
µA
µA
KΩ
RPD
100
注：
4. 参数由设计者提供
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev.1.0.2
5
动态电气特性
除非另有规定，否则 VBIAS (VDD， VBS)=15.0 V， VS=COM， CL=1000 pF 和 TA = 25°C。
符号
tON
tOFF
tR
参数
导通传播延迟时间
工作条件
最小值 典型值 最大值 单位
VS=0 V
VS=0 V
150
140
50
270
250
100
80
ns
ns
ns
ns
ns
关断传播延迟时间
导通上升时间
关断下降时间
死区时间
tF
30
DT
330
450
580
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev.1.0.2
6
典型特性
300
250
200
150
100
50
300
250
200
150
100
50
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 4. 导通传播延时 vs 温度
图 5. 关断传播延时 vs 温度
120
100
80
80
60
40
20
0
60
40
20
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 6. 导通上升时间 vs 温度
图 7. 关断下降时间 vs 温度
700
600
500
400
300
100
80
60
40
20
0
200
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 8. 死区时间 vs 温度
图 9. 逻辑输入高偏置电流 vs 温度
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev.1.0.2
7
典型特性 （续）
200
160
120
80
100
80
60
40
20
0
40
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 10. 静态 VDD 电源电流
与温度的关系
图 11. 静态 VBS 电源电流
与 温度的关系
750
750
600
450
300
150
0
600
450
300
150
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 12. 工作 VDD 电源电流与温度的关系
图 13. 工作 VBS 电源电流与温度的关系
9.2
8.8
8.4
8.0
7.6
7.2
10.0
9.6
9.2
8.8
8.4
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 14.VDD UVLO+ 与温度的关系
图 15.VDD UVLO- 与 温度的关系
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev. 1.0.2
8
典型特性 （续）
10.0
9.6
9.2
8.8
8.4
9.2
8.8
8.4
8.0
7.6
7.2
-40
-20
0
20
40
60
80
100
100
100
120
120
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 16.VBS UVLO+ 与温度的关系
图 17.VBS UVLO- 与 温度的关系
1.0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.8
0.6
0.4
0.2
0.0
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 18. 高电平输出电压 vs 温度
图 19. 低电平输出电压与 温度的关系
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 20. 逻辑高输入电压 vs 温度
图 21. 逻辑低输入电压 vs 温度
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev. 1.0.2
9
典型特性 （续）
0
-2
-4
-6
-8
-10
-12
-14
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
图 22. 容许负 VS 电压与 温度的关系
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev. 1.0.2
10
应用信息
1. 保护功能
2. 开关时间定义
1.1 欠压锁定 (UVLO)
50%
50%
50%
高侧和低侧驱动器的每个通道包括欠压闭锁 (UVLO) 保护
电路，用于分别监控电源电压 (VDD) 和自举电容电压
(VBS)。当 VDD 和 VBS 小于指定阈值电压时，欠压闭锁
(UVLO) 保护电路启动保护可防止发生故障。 UVLO 滞回
特性防止电源变化过程中的抖动。
LIN
More than
dead-time
More than
dead-time
50%
50%
HIN
tOFF
tOFF
1.2 直通预防功能
90%
90%
tON
LO
FAN73833 具有直通预防电路，用于监控高侧和低侧控制
输入。可防止同时导通高侧和低侧输出，如图 23 和 28 中
所示。
10%
tOFF
90%
tON
HO
10%
HIN
图 25. 开关时间定义
LIN
Shoot-Through Prevent
HO
After DT
LO
After DT
图 23. 直通预防波形
HIN
LIN
Shoot-Through Prevent
HO
After DT
LO
图 24. 直通预防波形
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev.1.0.2
11
机械尺寸
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.51
0.33
0.10 C
x 45?
OPTION A - BEVEL EDGE
0.50
0.25
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8?
0?
0.90
0.40
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
图 26. 8- 引脚式小尺寸封装 (SOP)
封装图纸是作为一项服务而提供给考虑选用飞兆半导体产品的客户。具体参数可能会有变化，且不会做出相应通知。请注意图纸上的版
本和 / 或日期，并联系飞兆半导体代表核实或获得最新版本。封装规格并不超出飞兆公司全球范围内的条款与条件，尤其指保修，保修
涵盖飞兆半导体的全部产品。
随时访问飞兆半导体在线封装网页，可以获取最新的封装图纸：
http://www.fairchildsemi.com/packaging/
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev. 1.0.2
12
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73833 • Rev. 1.0.2
13
ON Semiconductor and
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