FAN73833MX [FAIRCHILD]
Half-Bridge Gate-Drive IC; 半桥栅极驱动器IC
| 型号： | FAN73833MX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Half-Bridge Gate-Drive IC |
| 文件： | 总12页 (文件大小：1503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2008
FAN73833
Half-Bridge Gate-Drive IC
Features
Description
Floating Channel for Bootstrap Operation to +600V
The FAN73833 is a half-bridge gate-drive IC for driving
MOSFETs and IGBTs, operating up to +600V.
Typically 350mA/650mA Sourcing/Sinking Current
Driving Capability for Both Channels
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side driver under high-dv/dt noise circumstances.
Extended Allowable Negative VS Swing to -9.8V for
Signal Propagation at VDD=VBS=15V
3.3V and 5V Input Logic Compatible
An advanced level-shift circuit allows high-side gate
driver operation up to VS=-9.8V (typical) for VBS=15V.
Outputs in Phase with Input Signals
Built-in UVLO Functions for Both Channels
Built-in Shoot-Through Prevention Circuit
Built-in Common-Mode dv/dt Noise Canceling Circuit
Internal Dead-Time: 400ns Typical
The UVLO circuits for both channels prevent malfunction
when VDD and VBS are lower than the specified thresh-
old voltage.
Output drivers typically source/sink 350mA/650mA,
respectively, which is suitable for all kinds of half- and
full-bridge inverters.
Applications
SMPS
Motor Drive Inverter
Fluorescent Lamp Ballast
HID Ballast
8-SOP
Ordering Information
Operating
Part Number
FAN73833M
Package
Temperature Range
Eco Status
Packing Method
Tube
8-SOP
-40°C to +125°C
RoHS
FAN73833MX
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
www.fairchildsemi.com
Typical Application Circuit
Up to 600V
RBOOT DBOOT
VDD
1
2
3
4
8
7
6
5
LIN
HIN
VB
LIN
HIN
HO
VS
CBOOT
VDD
Load
COM
LO
Figure 1. Application Circuit for Half-Bridge
Internal Block Diagram
VB
8
7
UVLO
R
HO
R
S
NOISE
CANCELLER
Q
VS
6
3
SCHMITT
TRIGGER INPUT
HS(ON/OFF)
UVLO
2
1
VDD
HIN
LIN
100K
100K
SHOOT-THOUGH
PREVENTION
LS(ON/OFF)
DELAY
5
4
LO
DEAD TIME
{ 400ns }
COM
Figure 2. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
2
Pin Configuration
1
2
3
4
LIN
HIN
VDD
8
7
6
5
VB
HO
VS
LO
COM
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
2
3
4
5
6
7
8
LIN
HIN
VDD
COM
LO
Logic Input for Low-Side Driver
Logic Input for High-Side Driver
Low-Side Supply Voltage
Logic Ground and Low-Side Driver Return
Low-Side Driver Output
VS
High-Side Floating Supply Return
High-Side Driver Output
HO
VB
High-Side Floating Supply
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
VS
Parameter
High-side Offset Voltage
Min.
VB-25
-0.3
Max.
VB+0.3
625.0
VB+0.3
25.0
Unit
V
VB
High-side Floating Supply Voltage
High-side Floating Output Voltage HO
Low-side and Logic-fixed Supply Voltage
Low-side Output Voltage LO
V
VHO
VDD
VLO
VIN
VS-0.3
-0.3
V
V
-0.3
VDD+0.3
VDD+0.3
VDD+0.3
50
V
Logic Input Voltage (HIN/LIN)
-0.3
V
COM
dVS/dt
PD
Logic Ground and Low-side Driver Return
Allowable Offset Voltage Slew Rate
Power Dissipation(1)(2)(3)
VDD-25
V
V/ns
W
0.625
200
θJA
Thermal Resistance, Junction-to-Ambient
Junction Temperature
°C/W
°C
°C
TJ
+150
TSTG
Storage Temperature
-55
+150
Notes:
1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
2. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection;
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
3. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VB
Parameter
High-side Floating Supply Voltage
High-side Floating Supply Offset Voltage
Low-side Supply Voltage
Min.
VS+15
6-VDD
15
Max.
VS+20
600
Unit
V
VS
V
VDD
VHO
VLO
VIN
20
V
High-side (HO) Output Voltage
Low-side (LO) Output Voltage
Logic Input Voltage (HIN/LIN)
Ambient Temperature
VS
VB
V
COM
COM
-40
VDD
VDD
+125
V
V
TA
°C
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
4
Electrical Characteristics
V
(V , V )=15.0V, and T =25°C, unless otherwise specified. The V and I parameters are referenced to COM.
BIAS DD
BS A IN IN
The V and I parameters are referenced to V and COM and are applicable to the respective outputs HO and LO.
O
O
S
Symbol
Parameter
Condition
Min. Typ. Max. Unit
SUPPLY CURRENT SECTION
IQBS
IQDD
IPBS
IPDD
ILK
Quiescent VBS Supply Current
VIN=0V or 5V
35
80
100
200
750
750
10
µA
µA
µA
µA
µA
Quiescent VDD Supply Current
Operating VBS Supply Current
Operating VDD Supply Current
Offset Supply Leakage Current
VIN=0V or 5V
fIN=20kHz, rms Value
fIN=20kHz, rms Value
VB=VS=600V
420
420
POWER SUPPLY SECTION
VDDUV+ VDD and VBS Supply Under-Voltage
VBSUV+ Positive-going Threshold
8.2
7.2
9.2
8.3
0.9
10.1
9.3
V
V
V
VDDUV-
VBSUV-
VDD and VBS Supply Under-Voltage
Negative-going Threshold
VDDUVH VDD and VBS Supply Under-Voltage
VBSUVH Lockout Hysteresis
GATE DRIVER OUTPUT SECTION
VOH
VOL
High-level Output Voltage, VBIAS-VO
Low-level Output Voltage, VO
IO=20mA
1.0
0.6
V
V
Output High Short-Circuit Pulse
Current(4)
IO+
IO-
VS
VO=0V, VIN=5V with PW<10µs
250
350
650
-9.8
mA
mA
V
Output Low Short-Circuit Pulse
Current(4)
VO=15V, VIN=0V with PW<10µs 500
Allowable Negative VS Pin Voltage for
IN Signal Propagation to HO
-7.0
LOGIC INPUT SECTION
VIH
VIL
Logic "1" Input Voltage
2.5
V
V
Logic "0" Input Voltage
1.0
100
2.0
IIN+
IIN-
Logic "1" Input Bias Current
Logic "0" Input Bias Current
Input Pull-down Resistance
VIN=5V
VIN=0V
50
µA
µA
KΩ
RPD
100
Note:
4. This parameter is guaranteed by design.
Dynamic Electrical Characteristics
VBIAS (VDD, VBS)=15.0V, VS=COM, CL=1000pF, and TA = 25°C, unless otherwise specified.
Symbol
tON
Parameter
Turn-on Propagation Delay Time
Turn-off Propagation Delay Time
Turn-on Rising Time
Conditions
Min. Typ. Max. Unit
VS=0V
VS=0V
150
140
50
270
250
100
80
ns
ns
ns
ns
ns
tOFF
tR
tF
Turn-off Falling Time
30
DT
Dead Time
330
450
580
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
5
Typical Characteristics
300
250
200
150
100
50
300
250
200
150
100
50
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 4. Turn-on Propagation Delay vs. Temp.
Figure 5. Turn-off Propagation Delay vs. Temp.
120
100
80
60
40
20
0
80
60
40
20
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 6. Turn-on Rise Time vs. Temp.
Figure 7. Turn-off Fall Time vs. Temp.
700
100
600
500
400
300
200
80
60
40
20
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 8. Dead Time vs. Temp.
Figure 9. Logic Input High Bias Current vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
6
Typical Characteristics (Continued)
200
160
120
80
100
80
60
40
20
0
40
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 10. Quiescent VDD Supply Current
vs. Temp.
Figure 11. Quiescent VBS Supply Current
vs. Temp.
750
600
450
300
150
0
750
600
450
300
150
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 12. Operating VDD Supply Current vs. Temp.
Figure 13. Operating VBS Supply Current vs. Temp.
9.2
8.8
8.4
8.0
7.6
7.2
10.0
9.6
9.2
8.8
8.4
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 14. VDD UVLO+ vs. Temp.
Figure 15. VDD UVLO- vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
7
Typical Characteristics (Continued)
10.0
9.6
9.2
8.8
8.4
9.2
8.8
8.4
8.0
7.6
7.2
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 16. VBS UVLO+ vs. Temp.
Figure 17. VBS UVLO- vs. Temp.
1.0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.8
0.6
0.4
0.2
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 18. High-Level Output Voltage vs. Temp.
Figure 19. Low-Level Output Voltage vs. Temp.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 20. Logic High Input Voltage vs. Temp.
Figure 21. Logic Low Input Voltage vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
www.fairchildsemi.com
8
Typical Characteristics (Continued)
0
-2
-4
-6
-8
-10
-12
-14
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 22. Allowable Negative VS Voltage vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
www.fairchildsemi.com
9
Application Information
1. Protection Function
2. Switching Time Diagram
1.1 Under-Voltage Lockout (UVLO)
The high- and low-side drivers include under-voltage
lockout (UVLO) protection circuitry for each channel that
monitors the supply voltage (VDD) and bootstrap capaci-
tor voltage (VBS) independently. It can be designed to
prevent malfunction when VDD and VBS are lower than
the specified threshold voltage. The UVLO hysteresis
prevent chattering during power supply transitions.
50%
50%
50%
LIN
More than
dead time
More than
dead time
50%
50%
HIN
tOFF
tOFF
90%
90%
tON
LO
HO
10%
1.2 Shoot-Through Prevention Function
tOFF
The shoot-through prevention circuitry monitors the high-
and low-side control inputs. It can be designed to prevent
outputs of high and low side from turning on at same
time, as shown Figure 23 and 24.
90%
tON
10%
Figure 25. Switching Time Definition
HIN
LIN
Shoot-Through Prevent
HO
After DT
LO
After DT
Figure 23. Waveforms for Shoot-Through Prevention
HIN
LIN
Shoot-Through Prevent
HO
After DT
LO
Figure 24. Waveforms for Shoot-Through Prevention
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
www.fairchildsemi.com
10
Physical Dimensions
.
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
8ꢀ
0ꢀ
0.90
SEATING PLANE
(1.04)
0.406
DETAIL A
SCALE: 2:1
Figure 26. 8-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev.1.0.0
www.fairchildsemi.com
11
© 2008 Fairchild Semiconductor Corporation
FAN73833 • Rev. 1.0.0
www.fairchildsemi.com
12
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