FM75 [FAIRCHILD]
Low Voltage 2-Wire Digital Temperature Sensor with Thermal Alarm; 低压2线数字温度传感器，温度报警
| 型号： | FM75 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 2-Wire Digital Temperature Sensor with Thermal Alarm |
| 文件： | 总15页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FM75
Low Voltage 2-Wire Digital Temperature Sensor
with Thermal Alarm
Features
Description
• User Configurable to 9, 10, 11 or 12-bit Resolution
• Precision Calibrated to 1ꢀC ꢁroꢂ 0ꢀC to 100ꢀC Typical
• Teꢂperature Range: –40ꢀC to 125ꢀC
• Low Operating Current (less than 250µA)
• Low Selꢁ Heating (0.2ꢀC ꢂax in still air)
• Operating Voltage Range: 2.7V to 5.5V
Within the FM75 are: a high-precision CMOS teꢂperature
sensor, a Delta-Sigꢂa analog-to-digital converter and a
SMBus coꢂpatible serial digital interꢁace. Typical accuracy
is 2ꢀC over the ꢁull teꢂperature range oꢁ –40ꢀC to 125ꢀC
and to 1ꢀC over the range oꢁ 0ꢀC to 100ꢀC, with 9- to 12-bit
resolution. Deꢁault resolution is 9 bits.
Therꢂal Alarꢂ output, OS (Over-liꢂit Signal) supports
Interrupt and Coꢂparator ꢂodes. OS is active, iꢁ the
user-prograꢂꢂable trip-teꢂperature is exceeded. When
the teꢂperature ꢁalls below the trip-teꢂperature plus the
user-prograꢂꢂable hysteresis liꢂit, OS is disabled.
Applications
• Battery Manageꢂent
• FAX Manageꢂent
• Printers
• Portable Medical Instruꢂents
• HVAC
• Power Supply Modules
• Disk Drives
Available packages are surꢁace ꢂount SOIC-8 (SOP-8) and
MSOP-8.
• Coꢂputers
• Autoꢂotive
Application Diagram
2.7 to 5.5V
8
7
A0
User
Programmable
Address
6
A1
5
A2
FM75
3
O.S.
8 Pin
1
SMBus
Interface
Configuration
SDA
2
SCL
4
REV. 1.0.5 10/2/03
FM75
PRODUCT SPECIFICATION
Pin Assignments
1
2
3
4
8
7
6
5
SDA
SCL
O.S.
GND
V
DD
A0
A1
A2
FM75
Pin Descriptions
Pin #
Name
SDA
SCL
Direction
Description
1
2
3
Input/Output Serial Data. Open drain to I/O-data pin for two-wire interface.
Input
Serial Clock. Clock for 2-wire serial interface.
O.S.
Output
Over-Limit Signal. Open drain thermostat output that indicates if the
temperature has exceeded user-programmable limits. Default is
active low.
4
GND
Supply
Input
Ground
5, 6, 7
A0, A1, A2
Address LSBs. User selectable address pins for the 3 LSBs of the
serial interface address.
8
VDD
Supply
Supply Voltage
2
REV. 1.0.5 10/2/03
PRODUCT SPECIFICATION
FM75
Absolute Maximum Ratings1
Parameter
Supply Voltage
Min.
Typ.
Max.
+7
Units
V
V
Output Voltage
VCC + 0.5
10
Output Current
mA
°C
°C
Storage Temperature Range
-60
+150
220
Lead Soldering Temperature
ESD2
Human Body Model
Machine Model
2000
250
V
V
Notes:
1. Absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. These are stress
ratings only; functional operation at or above these limits is not implied.
2. Human Body Model: 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Machine Model: 200pF capacitor
discharged directly into each pin.
Electrical Characteristics3
(-40°C ≤ TA ≤ +125°C, VCC = 5.0V unless otherwise noted. Specifications subject to change without notice.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
°C
Specified Temperature Range
Temperature Conversion Time4
Accuracy5
TMIN, TMAX
-40
+125
90
ms
TA = +25°C
TA = +100°C
-2
-3
-4
-4
+2
+3
+4
+4
°C
TA = –40°C (TMIN
)
TA = +125°C (TMAX
)
Notes:
3. These specifications are guaranteed only for the test conditions listed.
4. This specification only indicates how often temperature information is updated to the Temperature Register. The FM75 can
be read at any time without interrupting the temperature conversion process.
5. Accuracy (expressed in °C) = Difference between the FM75 output temperature and the measured temperature.
Logic Electrical Characteristics
Parameter
Symbol
VIH
Conditions
Min
VDD x 0.7
-0.3
Typ
Max
Units
Min. Input Voltage Logic High
Max. Input Voltage Logic Low
VDD + 0.5
VDD x 0.3
V
V
VIL
Max. Output Voltage Logic
Low
VOL
VDD = 5V, IOL = -3mA
VDD = 3V, IOL = -1.5mA
0.36
0.36
V
V
Quiescent Supply Current
IDD
IDD-SD
IIN
Interface inactive R/W
Activity on SDA
250
350
500
700
µA
µA
µA
Shutdown Current
Interface inactive R/W
Activity on SDA
0.15
83
1
150
Input Leakage Current
VIN = 0V or 5V, TA = 25°C
-40°C < TA < 125°C
0.1
1.0
Output Sink Current
Output Leakage Current
Output Transition Time
Input Capacitance
IOL
ILEAK
tF
TA = 25°C, VOL = 0.4V
VOH = 5V, VDD = 0V
CL = 400pF, IOL = -3mA
All Digital Inputs
3
5
mA
µA
ns
0.001
250
20
CIN
pF
REV. 1.0.5 10/2/03
3
FM75
PRODUCT SPECIFICATION
Serial Port Timing
Parameter
Symbol
tSCL
Conditions
Min.
Typ.
Max.
100
Units
µs
SCL Clock Period
1.0
SCL Clock Transition Time
SCL Clock Low Period
SCL Clock High Period
tT:LH, tT:HL
tLOW
300
ns
0.470
0.400
1.0
µs
tHIGH
50
µs
Bus free time between a Stop and
a new Start Condition
tBUF
µs
Data in Set-up to SCL High
tSU:DAT
tHD:DAT
tSU:STA
100
0
ns
ns
ns
Data Out Stable after SCL Low
SCL Low Set-up to SDA Low
(Repeated Start Condition)
100
SCL High Hold after SDA Low
(Start Condition)
tHD:STA
tSU:STO
tPOR
100
100
ns
ns
SDA High after SCL High
(Stop Condition
Time in which a FM75 must be
500
ms
operational after a power-on reset
tSCL
SCL
tSU:STA
tHD:STA
tSU:DAT
tSU:STO
SDA
Data In
tBUF
tT:HL
tT:LH
tLOW
tHIGH
90% 90%
10% 10%
SCL
SDA
Data Out
tHD:DAT
4
REV. 1.0.5 10/2/03
PRODUCT SPECIFICATION
FM75
Table 1. Relationship Between Temperature and
Digital Output
Basic Operation
The FM75 teꢂperature sensing circuitry continuously
produces an analog voltage that is proportional to the device
teꢂperature. At regular intervals the FM75 converts the
analog voltage to a two’s coꢂpleꢂent digital value, which is
placed into the teꢂperature register.
Temperature
Digital Output
Number of
bits used
by
conversion bit bit bit bit
resolution 10 11 12
Always
zero
Sig
9
The FM75 has an SMBus coꢂpatible digital serial interꢁace
which allows the user to access the data in the teꢂperature
register at any tiꢂe. In addition, the serial interꢁace gives the
user easy access to all other FM75 registers to custoꢂize
operation oꢁ the device.
12-Bit Resolution
11-Bit Resolution
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0
0
0
0
1
0
0
0
0
0
1
0
All
Temperatures
10-Bit Resolution
0
0
0
0
1
0
0
0
0
1
0
The FM75 teꢂperature-to-digital conversion can have 9,
10, 11, or 12-bit resolution as selected by the user, providing
0.5ꢀC, 0.25ꢀC, 0.125ꢀC, and 0.0625ꢀC teꢂperature
resolution, respectively. At power-up the deꢁault conversion
resolution is 9-bits. The conversion resolution is controlled
by the R0 and R1 bits in the Configuration Register.
9-Bit Resolution
111 1101
110 0100
011 0010
000 1100
000 0000
110 1011
101 1110
101 0010
100 1001
0
0
0
0
1
0
0
1
1
0
+125°C
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
+100.0625°C
+50.125°C
+12.25°C
0°C
Table 1 gives exaꢂples oꢁ the relationship between the
output digital data and the external teꢂperature. The 9-bit,
10-bit, 11-bit and 12-bit coluꢂns in Table 1 indicate the
right-ꢂost bit in the output data streaꢂ that can contain
teꢂperature inꢁorꢂation ꢁor each conversion accuracy.
Since the output digital data is in two’s-coꢂpleꢂent ꢁorꢂat,
the ꢂost significant bit oꢁ the teꢂperature is the “sign” bit.
Iꢁ the sign bit is a zero, the teꢂperature is positive and iꢁ the
sign bit is a one, the teꢂperature is negative.
-20.5°C
-33.25°C
-45.0625°C
-55°C
The FM75 has a Shutdown Mode that reduces the operating
current oꢁ the FM75 to 150nA. This ꢂode is controlled by
the SD bit in the configuration register.
The O.S. polarity is controlled by the POL bit in the
Configuration Register. The user-prograꢂꢂable upper
trip-point teꢂperature ꢁor the therꢂal alarꢂ is stored in
the TOS Register, and the user-prograꢂꢂable hysteresis teꢂ-
perature (i.e., the lower trip point) is stored in the THYST
Register.
Power Up Default Conditions
The FM75 always powers up in the ꢁollowing deꢁault state:
• Therꢂostat ꢂode: Coꢂparator Mode
• O.S. polarity: active low
• Fault tolerance: 1 ꢁault (i.e., F0 = 0 and F1 = 0 in the
Configuration Register)
The therꢂal alarꢂ has two ꢂodes oꢁ operation: Coꢂparator
Mode and Interrupt Mode. At power-up the deꢁault is
Coꢂparator Mode. The alarꢂ ꢂode is controlled by the
CMP/INTR bit in the Configuration Register.
• TOS = 80ꢀC
• THYST = 75ꢀC
Fault Tolerance
• Register pointer: 00 (Teꢂperature Register)
• Conversion resolution: 9 bits (i.e., R0 = 0 and R1 = 0 in
the Configuration Register)
For both Coꢂparator and Interrupt ꢂodes, the alarꢂ “ꢁault
tolerance” setting plays a role in deterꢂining when the O.S.
output will be activated. Fault tolerance reꢁers to the nuꢂber
oꢁ consecutive tiꢂes an error condition ꢂust be detected
beꢁore the user is notified. Higher ꢁault tolerance settings can
help eliꢂinate ꢁalse alarꢂs caused by noise in the systeꢂ.
The alarꢂ ꢁault tolerance is controlled by bits F0 and F1 in
the Configuration Register. These bits can be used to set
the ꢁault tolerance to 1, 2, 4 or 6 as shown in Table 4. At
power-up, these bits both deꢁault to 0 (ꢁault tolerance = 1).
Aꢁter power up these conditions can be reprograꢂꢂed via
the serial interꢁace. Reꢁer to the Serial Data Bus Operation
section ꢁor FM75 prograꢂꢂing instructions.
Thermal Alarm Function
The FM75 therꢂal alarꢂ ꢁunction provides user prograꢂ-
ꢂable therꢂostat capability and allows the FM75 to ꢁunction
as a stand alone therꢂostat without using the serial interꢁace.
The Over-Liꢂit Signal (O.S.) output is the alarꢂ output. This
signal is an open drain output, and at power-up this pin is
configured with active-low polarity.
REV. 1.0.5 10/2/03
5
FM75
PRODUCT SPECIFICATION
Comparator Mode
Interrupt Mode
In Coꢂparator Mode, each tiꢂe a teꢂperature-to-digital
(T-to-D) teꢂperature conversion occurs, the new digital teꢂ-
perature is coꢂpared to the value stored in the TOS and
THYST registers. Iꢁ a ꢁault tolerance nuꢂber oꢁ consecutive
teꢂperature ꢂeasureꢂents are greater than the value stored
in the TOS register, the O.S. output will be activated.
For exaꢂple, iꢁ bits F1 and F0 are equal to “10” (ꢁault
tolerance = 4), ꢁour consecutive teꢂperature ꢂeasureꢂents
ꢂust exceed TOS to activate the O.S. output. Once the O.S
output is active, it will reꢂain active until the first tiꢂe the
ꢂeasured teꢂperature drops below the teꢂperature stored in
the THYST register. The operation oꢁ the alarꢂ in Coꢂparator
Mode with ꢁault tolerance=2 is illustrated in Figure 1.
In Interrupt Mode the O.S. output will first becoꢂe active
aꢁter a ꢁault tolerance nuꢂber oꢁ consecutive teꢂperature
ꢂeasureꢂents exceed the value stored in the TOS register
(siꢂilar to Coꢂparator Mode). Once O.S. is active, it can
only be cleared by a user read ꢁroꢂ any oꢁ the FM75
registers (Teꢂperature, Configuration, TOS, or THYST) or by
putting the FM75 into Shutdown Mode (i.e., by setting the
shutdown bit in the Configuration Register to “1”). Once
cleared, the O.S. output can only be activated the next tiꢂe
by a ꢁault tolerance nuꢂber oꢁ consecutive teꢂperature
ꢂeasureꢂents that are lower than the value stored in THYST
.
Again, once it is activated the O.S. output can only be
deactivated by a user read or shutdown. Thus, in Interrupt
Mode the activate/clear cycle ꢁor O.S. has the ꢁollowing
pattern: teꢂperature > TOS, clear, teꢂperature < THYST
,
clear, teꢂperature > TOS, clear, etc. The operation oꢁ the
alarꢂ in Interrupt Mode with ꢁault tolerance=2 is also
illustrated in Figure 1.
Temperature-to-Digital
Conversion
TOS
THYST
O.S. (Comparator Mode)
O.S. (Interrupt Mode)
For this example:
Fault Tolerance = 2
Output Polarity = Active Low
Read (or Shutdown)
Figure 1. Thermal Alarm Operation in Comparator and Interrupt Modes
6
REV. 1.0.5 10/2/03
PRODUCT SPECIFICATION
FM75
Registers
Command Register
The FM75 contains the ꢁollowing five registers:
The Coꢂꢂand Register is a one-byte (8-bit) write-only
register. The data stored in the Coꢂꢂand Register indicates
which oꢁ the other ꢁour registers (Teꢂperature, Configura-
tion, TOS, or THYST) the user intends to read ꢁroꢂ or
write to during an upcoꢂing operation. In other words the
Coꢂꢂand Register “points” to the selected register as shown
in Figure 2.
1. Coꢂꢂand Register
2. Teꢂperature Register
3. Configuration Register
4. Over-Liꢂit-Signal Teꢂperature Register (TOS
)
The Coꢂꢂand Register is illustrated in Figure 3. The P1 and
P0 bits oꢁ the Coꢂꢂand Register deterꢂine which register is
to be accessed as shown in Table 2. The six MSBs oꢁ the
Coꢂꢂand Register ꢂust always be zero. Writing a 1 into
any oꢁ these bits will cause the current operation to be
terꢂinated.
5. Hysteresis Teꢂperature Register (THYST
)
All oꢁ these registers can be accessed by the user via the
digital serial interꢁace at any tiꢂe (see Serial Interꢁace
Operation ꢁor instructions). A detailed description oꢁ these
registers and their ꢁunctions is provided in the ꢁollowing
paragraphs. A diagraꢂ oꢁ the register hierarchy is shown in
Figure 2.
The Coꢂꢂand Register retains pointer inꢁorꢂation between
operations. Thereꢁore, this register only needs to be updated
once ꢁor consecutive read operations ꢁroꢂ the saꢂe register.
All bits in the Coꢂꢂand Register deꢁault to zero at
power-up.
SCL
SDA
Temperature Register
2-byte Read Only
Command Reg. = 00000000
Serial Interface
Read/Write
Data
Configuration Register
1-byte Read/Write
Command Reg. = 00000001
Command
(‘Pointer’)
Data
T
Register
HYST
2-byte Read/Write
Command Reg. = 00000010
Command Register
1-byte Write Only
T
Register
OS
2-byte Read/Write
Command Reg. = 00000011
Figure 2. FM75 Register Hierarchy
Table 2. Register Assignments for Command
Bits P1 and P2
MSB
LSB
0
P1
P0
0
0
0
0
0
Register
P1
0
P0
0
Figure 3. Command Register Format
Temperature Register
Configuration Register
THYST Register
TOS Register
0
1
1
0
1
1
REV. 1.0.5 10/2/03
7
FM75
PRODUCT SPECIFICATION
Temperature Register
Configuration Register
The Teꢂperature Register is a two-byte (16-bit) read-only
register. Digital teꢂperatures ꢁroꢂ the T-to-D converter are
stored in the Teꢂperature Register in two’s coꢂpleꢂent
ꢁorꢂat, and the contents oꢁ this register are updated at regular
intervals—i.e., each tiꢂe the T-to-D conversion is finished.
The Configuration Register is a one-byte (8-bit) read/write
register (see Figure 5). This register allows the user to control
the FM75 Shutdown Mode as well as the ꢁollowing therꢂal
alarꢂ ꢁeatures: polarity, operating ꢂode, and ꢁault tolerance.
The Configuration Register contains two bits that set the ꢁault
tolerance trip point. The ꢁault tolerance trip point is the nuꢂ-
ber oꢁ consecutive tiꢂes the internal circuit reads the teꢂper-
ature and finds the teꢂperature outside the liꢂits
prograꢂꢂed. The prograꢂꢂed liꢂits are defined by the TOS
Register ꢁor the upper liꢂit, and by the THYST Register ꢁor
the lower liꢂit. Table 4 shows the relationship between F1
and F0 and the nuꢂber oꢁ consecutive errors or “trips”
needed to activate the alarꢂ. The Configuration Register also
contains the two bits that set the T-to-D conversion resolution
to 9, 10, 11, or 12 bits. Table 3 shows the relationship
between R1 and T0 and the conversion resolution. All bits in
the configuration register deꢁault to zero at power-up.
The user can read data ꢁroꢂ the Teꢂperature Register at any
tiꢂe. When a T-to-D conversion is coꢂpleted, the new data is
loaded into a coꢂparator buꢁꢁer to evaluate ꢁault conditions,
and will update the Teꢂperature Register iꢁ a read cycle is
not ongoing. The FM75 is continuously evaluating ꢁault
conditions regardless oꢁ read or write activity on the bus. Iꢁ a
read is ongoing, the previous teꢂperature will be read. The
readable teꢂperature will be updated upon the coꢂpletion oꢁ
the next T-to-D conversion that is not ꢂasked by a read
cycle.
The Teꢂperature Register is illustrated in Figure 4. Depend-
ing on the resolution oꢁ the T-to-D conversion, the 9, 10,
11 or 12 MSBs oꢁ the register will contain teꢂperature data.
All unused bits ꢁollowing the digital teꢂperature will be
zero. The MSB position oꢁ the Teꢂperature Register always
contains the sign bit ꢁor the digital teꢂperature and bit 14
contains the teꢂperature MSB. All bits in the Teꢂperature
Register deꢁault to zero at power-up.
5
4
3
MSB
6
2
1
LSB
POL CMP/
X R1
SD
R0 F1 F0
INT
R1 = Resolution bit 1. (See Table 3)
R0 = Resolution bit 0. (See Table 3)
F1 = Fault tolerance bit 1. (See Table 4)
F0 = Fault tolerance bit 0. (See Table 4)
POL = O.S. output polarity. 0 = active low, 1 = active high.
CMP/INT = Thermostat mode. 0 = comparator mode,
1 = interrupt mode.
13 12 11
MSB 14
10
9
8
TMSB
T
T
SB
T
T
T
T
SD = Shutdown. 0 = normal operation, 1 = shutdown
mode.
6
4
2
7
5
3
1
LSB
Figure 5. Configuration Register Format
9-bit 10-bit
LSB LSB
12-bit
LSB
11-bit
LSB
0
0
0
0
Table 3. Conversion Resolution Settings
A-to-D Conversion Resolution
R1
0
R0
0
SB = Two’s complement sign bit
TMSB = Temperature MSB
T = Temperature data
9 Bits
10 Bits
11 Bits
12 Bits
0
1
9-bit LSB = Temperature LSB for 9-bit conversions
1
0
10-bit LSB = Temperature LSB for 10-bit conversions
11-bit LSB = Temperature LSB for 11-bit conversions
12-bit LSB = Temperature LSB for 12-bit conversions
1
1
Table 4. Fault Tolerance Settings
Figure 4. Temperature Register Format
Fault Tolerance
R1
0
R0
0
1
2
4
6
0
1
1
0
1
1
8
REV. 1.0.5 10/2/03
PRODUCT SPECIFICATION
FM75
Over-Limit-Signal Temperature Register (T
)
OS
Hysteresis Temperature Register (T
)
HYST
The TOS Register is a two-byte (16-bit) read/write register
that stores the user-prograꢂꢂable upper trip-point
teꢂperature ꢁor the therꢂal alarꢂ in two’s-coꢂpleꢂent
ꢁorꢂat. At power-up this register deꢁaults to 80ꢀC
(i.e., 0101 0000 0000 0000).
The THYST Register is a two-byte (16-bit) read/write
register that stores the user prograꢂꢂable lower trip-point
teꢂperature ꢁor the therꢂal alarꢂ in two’s-coꢂpleꢂent
ꢁorꢂat. At power-up this register deꢁaults to 75ꢀC (i.e., 0100
1011 0000 0000).
The ꢁorꢂat oꢁ the TOS register is identical to that oꢁ the
The THYST register is illustrated in Figure 6. The ꢁorꢂat oꢁ
this register is the saꢂe as that oꢁ the Teꢂperature Register.
The 4 LSBs oꢁ the THYST register are hardwired to zero, so
data written to these bits is ignored.
Teꢂperature Register (see Figure 6). The 4 LSBs oꢁ the TOS
Register are hardwired to zero, so data written to these
register bits will be ignored. The MSB position oꢁ the TOS
Register contains the sign bit ꢁor the digital teꢂperature and
bit 14 contains the teꢂperature MSB.
The resolution setting ꢁor the T-to-D conversion deterꢂines
how ꢂany bits oꢁ the THYST Register are used by the therꢂal
alarꢂ. For exaꢂple, ꢁor 9-bit conversions the hysteresis
teꢂperature is defined by the 9 MSBs oꢁ the THYST Register,
and all reꢂaining bits are “don’t cares.”
The resolution setting ꢁor the T-to-D conversion deterꢂines
how ꢂany bits oꢁ the TOS Register are used by the therꢂal
alarꢂ. For exaꢂple, ꢁor 9-bit conversions the trip-point
teꢂperature is defined by the 9 MSBs oꢁ the TOS register,
and all reꢂaining bits are “don’t cares.”
.
13 12 11
MSB 14
10
9
8
TMSB
T
T
SB
T
T
T
T
6
4
2
7
5
3
1
LSB
9-bit 10-bit
LSB LSB
12-bit
LSB
11-bit
LSB
0
0
0
0
SB = Two’s complement sign bit
TMSB = Temperature MSB
T = Temperature data
9-bit LSB = Temperature LSB for 9-bit conversions
10-bit LSB = Temperature LSB for 10-bit conversions
11-bit LSB = Temperature LSB for 11-bit conversions
12-bit LSB = Temperature LSB for 12-bit conversions
Figure 6. T
Register and T Register Format
OS
HYST
REV. 1.0.5 10/2/03
9
FM75
PRODUCT SPECIFICATION
Slave Address
Serial Data Bus Operation
Each slave device on the bus has a unique 7-bit address so
the ꢂaster can identiꢁy which device is being read ꢁroꢂ or
written to.
General Operation
Writing to and reading ꢁroꢂ the FM75 registers is accoꢂ-
plished via the SMBus-coꢂpatible two-wire serial interꢁace.
SMBus protocol requires that one device on the bus initiates
and controls all read and write operations. This device is
called the “ꢂaster” device. The ꢂaster device also generates
the SCL signal which is the clock signal ꢁor all other devices
on the bus. All other devices on the bus are called “slave”
devices. The FM75 is a slave device. Both the ꢂaster and
slave devices can send and receive data on the bus.
The FM75 address is as ꢁollows:
0
A0
1 A2 A1
1
0
The ꢁour MSBs oꢁ the FM75 address are hardwired to 1001.
The three LSBs are user configurable by tying the A0, A1
and A2 pins to either VDD or ground. This provides eight
diꢁꢁerent FM75 addresses, which allows up to eight FM75s
to be connected to the saꢂe bus.
During SMBus operations, one data bit is transꢂitted per
clock cycle. All SMBus operations ꢁollow a repeating nine
clock-cycle pattern that consists oꢁ eight bits (one byte) oꢁ
transꢂitted data ꢁollowed by an acknowledge (ACK) or not
acknowledge (NACK) ꢁroꢂ the receiving device. Note that
there are no unused clock cycles during any operation—
thereꢁore there ꢂust be no breaks in the streaꢂ oꢁ data and
ACKs/NACKs during data transꢁers. Conversely having too
ꢁew clock cycles can lead to incorrect operation iꢁ an
inadvertent 8-bit read ꢁroꢂ a 16-bit register occurs.
Writing To and Reading From the FM75
All read and write operations ꢂust begin with a start signal
generated by the ꢂaster device. Aꢁter the start condition, the
ꢂaster device ꢂust iꢂꢂediately send a slave address (7 bits)
ꢁollowed by a read/write bit. Iꢁ the slave address ꢂatches the
address oꢁ the FM75, the FM75 sends an ACK aꢁter
receiving the read/write bit by pulling the SDA line low
ꢁor one clock. See Figure 8 through Figure 13 ꢁor tiꢂing
diagraꢂs ꢁor all FM75 operations.
For ꢂost operations, SMBus protocol requires the SDA line
to reꢂain stable (unꢂoving) whenever SCL is high—i.e.,
transitions on the SDA line can only occur when SCL is low.
The exceptions to this rule are when the ꢂaster device issues
a start or stop signal. Note that the slave device cannot issue
a start or stop condition.
Setting the Pointer
For all operations the pointer stored in the Coꢂꢂand
Register ꢂust be pointing to the register (Teꢂperature,
Configuration, TOS or THYST) that is going to be written to
or read ꢁroꢂ. To change the pointer value in the Coꢂꢂand
Register, the read/write bit ꢁollowing the address ꢂust be 0.
This indicates that the ꢂaster will now write new inꢁorꢂa-
tion into the Coꢂꢂand Register.
The ꢁollowing are definitions ꢁor soꢂe general SMBus
terꢂs:
Start Condition: This condition occurs when the SDA line
transitions ꢁroꢂ high to low while SCL is high. The ꢂaster
device uses this condition to indicate that a data transꢁer is
about to begin.
Aꢁter the FM75 sends an ACK in response to receiving the
address and read/write bit, the ꢂaster device ꢂust transꢂit
an appropriate 8-bit pointer value as explained in the
Registers section oꢁ this data sheet. The FM75 will send an
ACK aꢁter receiving the new pointer data.
Stop Condition: This condition occurs when the SDA line
transitions ꢁroꢂ low to high while SCL is high. The ꢂaster
device uses this condition to signal the end oꢁ a data transꢁer.
The pointer set operation is illustrated in Figure 8. Anytiꢂe a
pointer set is perꢁorꢂed, it ꢂust be iꢂꢂediately ꢁollowed by
a read or write operation. Note that the 6 MSBs oꢁ the
pointer value ꢂust be zero. Iꢁ the 6 MSBs are not zero, the
FM75 will not send an ACK and will internally terꢂinate the
operation. Also recall that the Coꢂꢂand Register retains the
current pointer value between operations. Thereꢁore, once a
register is being pointed to, subsequent read operations do
not require a pointer set cycle. Write operations always
require the pointer be reset.
Acknowledge and Not Acknowledge: When data is trans-
ꢁerred to the slave device it sends an acknowledge (ACK)
aꢁter receiving every byte oꢁ data. A ꢂaster device sends an
acknowledge (ACK) ꢁollowing only the first byte read ꢁroꢂ a
2-byte register. The receiving device sends an ACK by
pulling SDA low ꢁor one clock. Following the last byte,
a ꢂaster device sends a “not acknowledge” (NACK)
ꢁollowed by a stop condition. A NACK is indicated by
leaving SDA high during the clock aꢁter the last byte.
10
REV. 1.0.5 10/2/03
PRODUCT SPECIFICATION
FM75
Reading
Writing
Iꢁ the pointer is already pointing to the desired register, the
ꢂaster can read ꢁroꢂ that register by setting the read/write
bit (ꢁollowing the slave address) to a 1. Aꢁter sending an
ACK, the FM75 will begin transꢂitting data during the
ꢁollowing clock cycle. Iꢁ the Configuration Register is
being read, the FM75 will transꢂit one byte oꢁ data (see
Figure 10). The ꢂaster device should respond with a NACK
ꢁollowed by a stop condition. Iꢁ the Teꢂperature, TOS or
THYST Register is being read, the FM75 will transꢂit two
bytes oꢁ data (see Figure 9). The ꢂaster ꢂust respond to the
first byte oꢁ data with an ACK and to the second byte oꢁ data
with a NACK ꢁollowed by a stop condition.
All writes ꢂust be proceeded by a pointer set as described
previously, even iꢁ the pointer is already pointing to the
desired register.
Iꢂꢂediately ꢁollowing the pointer set, the ꢂaster ꢂust
begin transꢂitting the data to be written. Iꢁ the ꢂaster is
writing to the Configuration Register, one byte oꢁ data ꢂust
be sent (see Figure 13). Iꢁ the TOS or THYST Register is
being written to, the ꢂaster ꢂust send two bytes oꢁ data
(see Figure 11). Aꢁter transꢂitting each byte oꢁ data, the
ꢂaster ꢂust release the SDA line ꢁor one clock to allow the
FM75 to acknowledge receiving the byte. The write
operation should be terꢂinated by a stop signal ꢁroꢂ the
ꢂaster.
To read ꢁroꢂ a register other than the one currently being
pointed to by the Coꢂꢂand Register, a pointer set to the
desired register ꢂust be done as described previously.
Iꢂꢂediately ꢁollowing the pointer set, the ꢂaster ꢂust
perꢁorꢂ a repeat start condition (see Figures 8 and 12) which
indicates to the FM75 that a new operation is about to occur.
It is iꢂportant to note that iꢁ the repeat start condition does
not occur, the FM75 will assuꢂe that a write is taking place,
and the selected register will be overwritten by the upcoꢂing
data on the data bus. Aꢁter the start condition, the ꢂaster
ꢂust again send the device address and read/write bit. This
tiꢂe the read/write bit ꢂust be set to 1 to indicate a read. The
rest oꢁ the read cycle is the saꢂe as described in the previous
paragraph ꢁor reading ꢁroꢂ a preset pointer location.
Inadvertent 8-Bit Read from a 16-Bit
Register: A Caution
An inadvertent 8-bit read ꢁroꢂ a 16-bit register, with the
D7 bit low, can cause the FM75 to pause in a state where the
SDA line is pulled low by the output data and is incapable oꢁ
receiving either a stop or a start condition ꢁroꢂ the ꢂaster.
The only way to reꢂove the FM75 ꢁroꢂ this state is to
continue clocking ꢁor 9 cycles until SDA goes high, at which
tiꢂe issuing a stop condition will reset the FM75. This
sequence can be seen in Figure 7 below.
Nine additional clock cycles to reset the FM75
SCL
1
0
0
1
A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
N
D7
D6 D5 D4 D3 D2 D1 D0
N
A
SDA
R/W
No Ack Stop
from Condition
No Ack
from
Master
Ack
from
FM75
Start
from
Master
Most Significant
Data Byte
(from FM75)
Address Byte
Master
from
Master
Master must
detect error
condition on
FM75
Stop intended by
Master, but FM75
SDA line locked
low
Figure 7. Inadvertent 8-Bit Read from 16-Bit Register Where D7 = 0 and Forces Output Low
REV. 1.0.5 10/2/03
11
FM75
PRODUCT SPECIFICATION
Note: This segment of this timing diagram is a generic
pointer set cycle which must be followed by either an
immediate read cycle or write cycle as shown in this
figure and in figures 10, 11, and 12.
SCL
SDA
. . . .
A
0
0
0
R/W
0
0
0
P1 P0
A
S
A2 A1 A0
. . . .
1
0
0
1
Ack
from
aTS75
Ack
from
FM75
Address Byte
Pointer Byte
SCL
. . .
SDA
. . .
A2 A1
R/W
A
D3 D2 D1 D0
A
0
0
0
P
D4
S
1
0
1
A0
D7 D6 D5 D4
D7 D6 D5
0
N
0
No Ack
from
Master
Ack
from
Master
Ack
from
FM75
Repeat
Start
from
Most Significant Data
Least Significant Data Byte
(from FM75)
Address Byte
Byte
(from FM75)
Master
Figure 8. Pointer Set Followed by Immediate Read from A 2-byte Register (Temperature, T or T
Register)
OS
HYST
SCL
SDA
S
A2 A1 A0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4
0
0
0
0
N
P
1
0
0
1
R/W
No Ack
from
Master
Ack
from
Master
Ack
from
FM75
Most Significant Data
Byte
Least Significant Data
Byte
Address
Byte
(from FM75)
(from FM75)
Figure 9. Two-byte Read from Preset Pointer Location (Temperature, T or T
Register)
OS
HYST
SCL
S
A2
A1 A0
A
X
D6 D5
D4
D3 D2
D1 D0
N
P
1
0
0
1
R/W
SDA
No Ack
from
Master
Ack
from
FM75
Data Byte
Address Byte
(from FM75)
Figure 10. One-byte Read from Configuration Register with Preset Pointer
12
REV. 1.0.5 10/2/03
PRODUCT SPECIFICATION
FM75
. . . .
. . . .
SCL
0
0
0
A2
A1
A0 R/W
A
0
0
0
P1
P0
A
1
0
0
1
S
SDA
Ack
from
FM75
Ack
from
FM75
Pointer Byte
Address Byte
. . . .
. . . .
A
D7
D6 D5
D4
D3 D2
D1
D0
A
D7 D6
D5 D4
0
0
0
0
P
A
Ack
from
FM75
Ack
from
FM75
Most Significant Data Byte
(from Master)
Least Significant Data Byte
(from Master)
Figure 11. Pointer Set Followed by Immediate Write to A 2-byte Register (T or T
Register)
OS
HYST
SCL
SDA
S
A2
A1
A0
A
0
0
0
0
0
0
P1
A
1
0
0
1
R/W
P0
S
A2
A1
A0
1
0
0
1
R/W
Ack
from
FM75
Ack
from
FM75
Repeat Start
from
Master
Address Byte
Pointer Byte
Address Byte
. . . .
. . . .
A
D4 D3
D2
D1
P
A2
A1 A0
X
D6
D5
D0
0
1
R/W
N
1
0
No Ack
from
Master
Ack
from
FM75
Address Byte
(repeated here for
clarity, transmitted only
Data Byte
(from FM75)
once in the actual sequence)
Figure 12. Pointer Set Followed by Immediate Read from Configuration Register
SCL
SDA
0
0
0
P1
S
A2 A1 A0 R/W
A
0
0
0
A
X
P
1
0
0
1
D6 D5 D4 D3 D2 D1 D0
A
P0
Ack
from
FM75
Ack
from
FM75
Ack
from
FM75
Address Byte
Pointer Byte
Data Byte
(from Master)
Figure 13. Pointer Set Followed by Immediate Write to the Configuration Register
REV. 1.0.5 10/2/03
13
FM75
PRODUCT SPECIFICATION
Mechanical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
5
0.228 - 0.244
(5.791 - 6.198)
1
2
3
4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45°
8° Max, Typ.
All leads
Seating
Plane
0.004
(0.102)
All lead tips
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
FS Package Number M08A
0.118 - 0.004
[3 0.1]
SYMM
C
–A–
8
5
(0.189)
[4.8]
0.118 0.004
[3 0.1]
0.193 0.004
[4.9 0.1]
–B–
(0.040)
[1.02]
TYP
PIN 1
IDENT
(0.016)
[0.41]
TYP
(0.0256)
[0.65]
TYP
1
4
LAND PATTERN RECOMMENDATION
TYP
(0.0256)
[0.65]
TYP
0.005
[0.13]
R
GAGE
PLANE
0.030 - 0.037
[0.78 - 0.94]
0.005
TYP
R
[0.13]
(0.010)
[0.23]
–C–
0.002 [0.05]
C
0.021 0.005
[0.53 0.12]
0.012 0.002
[0.3 0.05]
(0.033)
[0.84]
TYP
0°–6° TYP
SEATING PLANE
0.002 - 0.006
TYP
0.0375
[0.953]
[0.06 - 0.15]
0.002 [0.05] M
A
S
B S
0.007 0.002
[0.18 0.05]
TYP
8-Lead Molded Mini Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
FS Package Number MA08D
14
REV. 1.0.5 10/2/03
FM75
PRODUCT SPECIFICATION
Ordering Information
Part Number
Package
Temperature Range
-40°C to +125°C
-40°C to +125°C
Shipping
FM75M8x
8-Lead SOIC
8-Lead MSOP
2500 Units, Tape and Reel
3000 Units, Tape and Reel
FM75MM8x
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
10/2/03 0.0m 003
Stock#DS30000075
2002 Fairchild Semiconductor Corporation
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