FM75MM8 [ETC]
DIGITAL THERMOMETER|CMOS|TSSOP|8PIN ; 数字温度计| CMOS | TSSOP | 8PIN\n
| 型号： | FM75MM8 |
| 厂家： | 
ETC |
| 描述： | DIGITAL THERMOMETER|CMOS|TSSOP|8PIN
|
| 文件： | 总14页 (文件大小：2069K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
July 2001
FM75
Low Voltage 2-Wire Digital Temperature
Sensor with Thermal Alarm
General Description
Features
The FM75 is a high-precision CMOS temperature sensor with a
Delta-Sigma analog-to-digital converter and a SMBus compatible
serialdigitalinterface. TheFM75istypicallyaccurateto 2°Cover
the full temperature range of -40°C to 125°C and to 1°C over the
range of 0°C to 100°C. The FM75 provides digital temperature
data with 9 to 12-bit resolution. The default resolution is 9 bits, but
for applications requiring higher resolution, the user can program
the FM75 to provide 10, 11, or 12 bit data.
I User Configurable to 9, 10, 11 or 12-bit Resolution
I Precision Calibrated to 1°C from 0°C to 100°C Typical
I Temperature Range: -40°C to 125°C
I Low Operating Current (less than 250µA)
I Low Self Heating (0.2°C max in still air)
I Operating Voltage Range: 2.7V to 5.5V
Applications
The FM75 features a thermal alarm function with a user-program-
mable trip temperature and turn-off temperature. This alarm can
operate in two modes — interrupt mode and comparator mode —
which allows flexibility for many types of applications.
I Battery Management
I FAX Management
I Printers
The FM75 is available in SOP-8 and MSOP-8 surface mount
packages.
I Portable Medical Instruments
I HVAC
I Power Supply Modules
I Disk Drives
I Computers
I Automotive
Pin Configuration
Application Diagram
2.7 to 5.5V
1
2
3
4
8
7
6
5
SDA
SCL
O.S.
GND
V
DD
8
7
A0
A0
A1
A2
User
Programmable
Address
6
5
A1
FM75
A2
FM75
8 Pin
3
O.S.
1
2
SMBus
Interface
Configuration
SDA
SCL
4
1
© 2001 Fairchild Semiconductor Corporation
FM75 Rev. A.4
www.fairchildsemi.com
Absolute Maximum Ratings (Note 1)
Storage Temperature Range
Lead Soldering Temperature
-60°C to +150°C
220°C
Parameter
Rating
Supply Voltage
+7V
ESD2
Output Voltage
Output Current
V
CC + 0.5V
10mA
Human Body Model
Machine Model
2000V
250V
Notes:
1. Absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. These are stress ratings only; functional operation at or above
these limits is not implied.
2. Human Body Model: 100pF capacitor discharged through a 1.5kOhm resistor into each pin. Machine Model: 200pF capacitor discharged directly into each pin.
Electrical Characteristics3
(-40°C ≤ TA ≤ +125°C, VCC = 5.0V unless otherwise noted. Specifications subject to change
without notice.)
Parameter
Specified Temperature Range
Temperature Conversion Time4
Accuracy5
Symbol
Conditions
Min
Typ
Max
Units
°C
TMIN, TMAX
-40
+125
90
ms
TA = 0°C
TA = +25°C
A = +100°C
TA = -40°C (TMIN
TA = +125°C (TMAX
-1
-1
-1
-3
-3
+1
+1
+1
+3
+3
°C
°C
°C
°C
°C
T
)
)
Notes:
3. These specifications are guaranteed only for the test conditions listed.
4. This specification only indicates how often temperature information is updated to the Temperature Register. The FM75 can be read at any time without interrupting the
temperature conversion process.
5. Accuracy (expressed in °C) = Difference between the FM75 output temperature and the measured temperature.
Logic Electrical Characteristics
Parameter
Symbol
VIH
Conditions
Min
VDD x 0.7
-0.3
Typ
Max
Units
Min. Input Voltage Logic High
Max. Input Voltage Logic Low
Max. Output Voltage Logic Low
VDD + 0.5
VDD x 0.3
V
V
VIL
VOL
VDD = 5V, IOL = -3mA
VDD = 3V, IOL = -1.5mA
0.36
0.36
V
V
Quiescent Supply Current
Shutdown Current
IDD
IDD-SD
IIN
Interface inactive
R/W Activity on SDA
220
350
250
500
µA
µA
Interface inactive
R/W Activity on SDA
0.15
83
1
150
µA
µA
Input Leakage Current
VIN = 0V or 5V, TA = 25°C
-40°C < TA < 125°C
0.1
1.0
µA
µA
Output Sink Current
Output Leakage Current
Output Transition Time
Input Capacitance
IOL
ILEAK
tF
TA = 25°C, VOL = 0.4V
VOH = 5V, VDD = 0V
CL = 400pF, IOL = -3mA
All Digital Inputs
3
5
mA
µA
ns
0.001
250
20
CIN
pF
2
www.fairchildsemi.com
FM75 Rev. A.4
Serial Port Timing
Parameter
SCL Clock Period
Symbol
tSCL
Conditions
Min
Typ
Max
300
50
Units
ms
ns
2.5
SCL Clock Transition Time
SCL Clock Low Period
SCL Clock High Period
tT:LH, tT:HL
tLOW
0.470
0.400
1.0
µs
tHIGH
µs
Bus free time between a Stop and
a new Start Condition
tBUF
µs
Data in Set-up to SCL High
tSU:DAT
tHD:DAT
tSU:STA
100
0
ns
ns
ns
Data Out Stable after SCL Low
SCL Low Set-up to SDA Low
(Repeated Start Condition)
100
SCL High Hold after SDA Low
(Start Condition)
tHD:STA
tSU:STO
tPOR
100
100
ns
ns
SDA High after SCL High
(Stop Condition)
Time in which a FM75 must be
500
ms
operational after a power-on reset
tSCL
SCL
tSU:STA
tHD:STA
tSU:DAT
tSU:STO
SDA
Data In
tBUF
tT:HL
tT:LH
tLOW
tHIGH
90% 90%
10% 10%
SCL
SDA
Data Out
tHD:DAT
Pin Descriptions
Pin #
Name
SDA
Direction
Description
1
2
3
Input/Output
Input
Serial Data-Open drain to I/O-data pin for two-wire interface.
Serial Clock-Clock for 2-wire serial interface.
SCL
O.S.
Output
Over-Limit Signal-Open drain thermostat output that indicates if the
temperature has exceeded user-programmable limits.
4
GND
Supply
Input
Ground
5, 6, 7
A0, A1, A2
Address LSBs-User selectable address pins for the 3 LSBs of the
serial interface address.
8
VDD
Supply
Supply Voltage
3
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FM75 Rev. A.4
Table 1. Relationship Between Temperature
and Digital Output
Basic Operation
The FM75 temperature sensing circuitry continuously produces
an analog voltage that is proporational to the device temperature.
At regular intervals the FM75 converts the analog voltage to a
two’s complement digital value, which is placed into the tempera-
ture register.
Temperature
Digital Output
Number of
bits used
by
conversion bit bit bit bit
resolution 10 11 12
Always
zero
Sig
The FM75 has an SMBus compatible digital serial interface which
allows the user to access the data in the temperature register at
any time. In addition, the serial interface gives the user easy
access to all other FM75 registers to customize operation of the
device.
9
12-Bit Resolution
11-Bit Resolution
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0
0
0
0
1
0
0
0
0
0
1
0
All
The FM75 temperature-to-digital conversion can have 9, 10, 11,
or 12-bit resolution as selected by the user, providing 0.5°C,
0.25°C, 0.125°C, and 0.0625°C temperature resolution, respec-
tively. At power-up the default conversion resolution is 9-bits. The
conversion resolution is controlled by the R0 and R1 bits in the
Configuration Register.
Temperatures
10-Bit Resolution
0
0
0
0
1
0
0
0
0
1
0
9-Bit Resolution
111 1101
110 0100
011 0010
000 1100
000 0000
110 1011
101 1110
101 0010
100 1001
0
0
0
0
1
0
0
1
1
0
+125° C
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
+100.0625° C
+50.125° C
+12.25° C
0° C
Table 1 gives examples of the relationship between the output
digital data and the external temperature. The 9-bit, 10-bit, 11-bit
and 12-bit columns in Table 1 indicate the right-most bit in the
output data stream that can contain temperature information for
eachconversionaccuracy.Sincetheoutputdigitaldataisintwo’s-
complement format, the most significant bit of the temperature is
the“sign”bit.Ifthesignbitisazero,thetemperatureispositiveand
if the sign bit is a one, the temperature is negative.
-20.5° C
-33.25° C
-45.0625° C
-55° C
The FM75 has a Shutdown Mode that reduces the operating
current of the FM75 to 150nA. This mode is controlled by the SD
bit in the configuration register.
Power Up Default Conditions
The FM75 always powers up in the following default state:
The O.S. polarity is controlled by the POL bit in the Configuration
Register. The user-programmable upper trip-point temperature
for the thermal alarm is stored in the TOS Register, and the user-
programmable hysteresis temperature (i.e., the lower trip point) is
stored in the THYST Register.
I Thermostat mode: Comparator Mode
I O.S. polarity: active low
I Fault tolerance: 1 fault (i.e., F0 = 0 and F1 = 0 in the
Configuration Register)
Thethermalalarmhastwomodesofoperation:ComparatorMode
and Interrupt Mode. At power-up the default is Comparator Mode.
The alarm mode is controlled by the CMP/INTR bit in the Configu-
ration Register.
I TOS = 80°C
I THYST = 75°C
I Register pointer: 00 (Temperature Register)
I Conversion resolution: 9 bits (i.e., R0 = 0 and R1 = 0 in the
Fault Tolerance
Configuration Register)
In both modes the alarm “fault tolerance” setting plays a role in
determining when the O.S. output will be activated. Fault toler-
ance refers to the number of consecutive times an error condition
mustbedetectedbeforetheuserisnotified. Higherfaulttolerance
settings can help eliminate false alarms caused by noise in the
system. The alarm fault tolerance is controlled by bits F0 and F1
in the Configuration Register. These bits can be used to set the
fault tolerance to 1, 2, 4 or 6 as shown in Table 4. At power-up,
these bits both default to 0 (fault tolerance = 1).
After power up these conditions can be reprogrammed via the
serial interface. Refer to the Serial Data Bus Operation section
for FM75 programming instructions.
Thermal Alarm Function
The FM75 thermal alarm function provides user programmable
thermostat capability and allows the FM75 to function as a stand
alonethermostatwithoutusingtheserialinterface.TheOver-Limit
Signal (O.S.) output is the alarm output. This signal is an open
drainoutput, andatpower-upthispinisconfiguredwithactive-low
polarity.
4
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FM75 Rev. A.4
Comparator Mode
Interrupt Mode
In Comparator Mode, each time a temperature-to-digital (T-to-D)
temperature conversion occurs, the new digital temperature is
compared to the value stored in the TOS and THYST registers. If a
fault tolerance number of consecutive temperature measure-
ments are greater than the value stored in the TOS register, the
O.S. output will be activated. For example, if bits F1 and F0 are
equal to “10” (fault tolerance = 4), four consecutive temperature
measurementsmustexceedTOS toactivatetheO.S. output. Once
the O.S output is active, it will remain active until the first time the
measured temperature drops below the temperature stored in the
In Interrupt Mode the O.S. output will first become active after a
fault tolerance number of consecutive temperature measure-
ments exceed the value stored in the TOS register (similar to
Comparator Mode). Once O.S. is active, it can only be cleared by
a user read from any of the FM75 registers (Temperature, Con-
figuration, TOS, or THYST) or by putting the FM75 into Shutdown
Mode (i.e., by setting the shutdown bit in the Configuration
Register to “1”). Once cleared, the O.S. output can only be
activated the next time by a fault tolerance number of consecutive
temperature measurements that are lower than the value stored
in THYST. Again, once it is activated the O.S. output can only be
deactivated by a user read or shutdown. Thus, in Interrupt Mode
the activate/clear cycle for O.S. has the following pattern: tem-
perature > TOS, clear, temperature < THYST, clear, temperature >
TOS, clear, etc. The operation of the alarm in Interrupt Mode with
fault tolerance=2 is also illustrated in Figure 1.
T
HYST register. The operation of the alarm in Comparator Mode
with fault tolerance=2 is illustrated in Figure 1.
Temperature-to-Digital
Conversion
TOS
THYST
O.S. (Comparator Mode)
O.S. (Interrupt Mode)
For this example:
Fault Tolerance = 2
Output Polarity = Active Low
Read (or Shutdown
Figure 1. Thermal Alarm Operation in Comparator and Interrupt Modes
5
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FM75 Rev. A.4
Command Register
Registers
The Command Register is a one-byte (8-bit) write-only register.
The data stored in the Command Register indicates which of the
The FM75 contains the following five registers:
1) Command Register
other four registers (Temperature, Configuration, TOS, or THYST
)
2) Temperature Register
the user intends to read from or write to during an upcoming
operation. In other words the Command Register “points” to the
selected register as shown in Figure 2
3) Configuration Register
4) Over-Limit-Signal Temperature Register (TOS
)
The Command Register is illustrated in Figure 3. The P1 and P0
bits of the Command Register determine which register is to be
accessed as shown in Table 2. The six MSBs of the Command
Register must always be zero. Writing a 1 into any of these bits will
cause the current operation to be terminated.
5) Hysteresis Temperature Register (THYST
)
All of these registers can be accessed by the user via the digital
serial interface at any time (see Serial Interface Operation for
instructions). A detailed description of these registers and their
functionsisprovidedinthefollowingparagraphs. Adiagramofthe
register hierarchy is shown in Figure 2
The Command Register retains pointer information between
operations. Therefore, thisregisteronlyneedstobeupdatedonce
for consecutive read operations from the same register. All bits in
the Command Register default to zero at power-up.
SCL
SDA
Temperature Register
2-byte Read Only
Command Reg. = 00000000
Serial Interface
Read/Write
Data
Configuration Register
1-byte Read/Write
Command Reg. = 00000001
Command
('Pointer')
Data
T
Register
HYST
2-byte Read/Write
Command Reg. = 00000010
Command Register
1-byte Write Only
T
Register
OS
2-byte Read/Write
Command Reg. = 00000011
Figure 2. FM75 Register Hierarchy
Table 2. Register Assignments for
Command Bits P1 and P2
MSB
LSB
0
P1
P0
0
0
0
0
0
Register
Temperature Register
Configuration Register
THYST Register
P1
0
P0
0
Figure 3. Command Register Format
0
1
1
0
TOS Register
1
1
6
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FM75 Rev. A.4
Temperature Register
Configuration Register
The Temperature Register is a two-byte (16-bit) read-only regis-
ter. Digital temperatures from the T-to-D converter are stored in
the Temperature Register in two’s complement format, and the
contents of this register are updated at regular intervals—i.e.,
each time the T-to-D conversion is finished.
TheConfigurationRegisterisaone-byte(8-bit)read/writeregister
(see Figure 5). This register allows the user to control the FM75
Shutdown Mode as well as the following thermal alarm features:
polarity, operating mode, and fault tolerance. The Configuration
Registercontainstwobitsthatsetthefaulttolerancetrippoint.The
fault tolerance trip point is the number of consecutive times the
internal circuit reads the temperature and finds the tempterature
outside the limits programmed. The programmed limited are
defined by the TOS Register for the upper limit, and by the THYST
Register for the lower limit. Table 4 shows the relationship
betweenF1andF0andthenumberofconsecutiveerrorsor"trips"
needed to activate the alarm. The Configuration Register also
contains the two bits that set the T-to-D conversion resolution to
9, 10, 11, or 12 bits. Table 3 shows the relationship between R1
and T0 and the conversion resolution. All bits in the configuration
register default to zero at power-up.
The user can read data from the Temperature Register at any
time. When a T-to-D conversion is completed, the new data is
loaded into a comparator buffer to evaluate fault conditions, and
will update the Temperature Register is a read cycle is not
ongoing. The FM75 is continuously evaulating fault conditions
regardless of read or write activity on the bus. If a read is ongoing,
the previous temperature will be read. The readable temperature
will be updated upon the completion of the next T-to-D conversion
that is not masked by a read cycle.
The Temperature Register is illustrated in Figure 4. Depending on
the resolution of the T-to-D conversion, the 9, 10, 11 or 12 MSBs
of the register will contain temperature data. All unused bits
following the digital temperature will be zero. The MSB position of
the Temperature Register always contains the sign bit for the
digital temperature and bit 14 contains the temperature MSB. All
bits in the Temperature Register default to zero at power-up.
5
4
3
MSB
6
2
1
LSB
POL CMP/
X R1
SD
R0 F1 F0
INT
R1 = Resolution bit 1. (See Table 3)
R0 = Resolution bit 0. (See Table 3)
F1 = Fault tolerance bit 1. (See Table 4)
F0 = Fault tolerance bit 0. (See Table 4)
13 12 11
MSB 14
10
9
8
POL = O.S. output polarity. 0 = active low, 1 = active high.
CMP/INT = Thermostat mode. 0 = comparator mode, 1 = interrupt mode.
SD = Shutdown. 0 = normal operation, 1 = shutdown mode.
TMSB
T
T
SB
T
T
T
T
Figure 5. Configuration Register Format
Table 3. Conversion Resolution Settings
6
4
2
7
5
3
1
LSB
9-bit 10-bit
LSB LSB
12-bit
LSB
11-bit
LSB
0
0
0
0
A-to-D Conversion
Resolution
9 Bits
R1
R0
SB = Two's complement sign bit
TMSB = Temperature MSB
T = Temperature data
0
0
1
1
0
1
0
1
10 Bits
9-bit LSB = Temperature LSB for 9-bit conversions
10-bit LSB = Temperature LSB for 10-bit conversions
11-bit LSB = Temperature LSB for 11-bit conversions
12-bit LSB = Temperature LSB for 12-bit conversions
11 Bits
12 Bits
Figure 4. Temperature Register Format
Table 4. Fault Tolerance Settings
Fault Tolerance
F1
0
F0
0
1
2
4
6
0
1
1
0
1
1
7
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FM75 Rev. A.4
Over-Limit-Signal Temperature Register (TOS
)
Hysteresis Temperature Register (THYST
)
The TOS Register is a two-byte (16-bit) read/write register that
stores the user-programmable upper trip-point temperature for
the thermal alarm in two’s-complement format. At power-up this
register defaults to 80°C (i.e., 0101 0000 0000 0000).
The THYST Register is a two-byte (16-bit) read/write register that
stores the user programmable lower trip-point temperature for the
thermal alarm in two’s-complement format. At power-up this
register defaults to 75°C (i.e., 0100 1011 0000 0000).
The format of the TOS register is identical to that of the Tempera-
ture Register (see Figure 6). The 4 LSBs of the TOS Register are
hardwired to zero, so data written to these register bits will be
ignored. The MSB position of the TOS Register contains the sign
bit for the digital temperature and bit 14 contains the temperature
MSB.
The THYST register is illustrated in Figure 6. The format of this
register is the same as that of the Temperature Register. The 4
LSBs of the THYST register are hardwired to zero, so data written
to these bits is ignored.
The resolution setting for the T-to-D conversion determines how
many bits of the THYST Register are used by the thermal alarm. For
example, for 9-bit conversions the hysteresis temperature is
definedbythe9MSBsoftheTHYST Register, andallremainingbits
are "don't cares."
The resolution setting for the T-to-D conversion determines how
many bits of the TOS Register are used by the thermal alarm. For
example, for 9-bit conversions the trip-point temperature is de-
fined by the 9 MSBs of the TOS register, and all remaining bits are
“don’t cares.”
13 12 11
MSB 14
10
9
8
TMSB
T
T
SB
T
T
T
T
6
4
2
7
5
3
1
LSB
9-bit 10-bit
LSB LSB
12-bit
LSB
11-bit
LSB
0
0
0
0
SB = Two's complement sign bit
TMSB = Hysteresis temperature MSB
T = Temperature data
9-bit LSB = Hysteresis temperature LSB for 9-bit conversions
10-bit LSB = Hysteresis temperature LSB for 10-bit conversions
11-bit LSB = Hysteresis temperature LSB for 11-bit conversions
12-bit LSB = Hysteresis temperature LSB for 12-bit conversions
Figure 6. THYST Register and TOS Register Format
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FM75 Rev. A.4
Serial Data Bus Operation
Slave Address
Each slave device on the bus has a unique 7-bit address so the
master can identify which device is being read from or written to.
General Operation
Writing to and reading from the FM75 registers is accomplished
via the SMBus-compatible two-wire serial interface. SMBus pro-
tocol requires that one device on the bus initiates and controls all
read and write operations. This device is called the “master”
device. The master device also generates the SCL signal which is
the clock signal for all other devices on the bus. All other devices
on the bus are called “slave” devices. The FM75 is a slave device.
Both the master and slave devices can send and receive data on
the bus.
The FM75 address is as follows:
0
A0
1 A2 A1
1
0
The four MSBs of the FM75 address are hardwired to 1001. The
three LSBs are user configurable by tying the A0, A1 and A2 pins
to either VDD or ground. This provides eight different FM75
addresses, which allows up to eight FM75s to be connected to the
same bus.
During SMBus operations, one data bit is transmitted per clock
cycle. All SMBus operations follow a repeating nine clock-cycle
pattern that consists of eight bits (one byte) of transmitted data
followed by an acknowledge (ACK) or not acknowledge (NACK)
from the receiving device. Note that there are no unused clock
cycles during any operation—therefore there must be no breaks
in the stream of data and ACKs/NACKs during data transfers.
Conversely having too few clock cycles can lead to incorrect
operationifaninadverstne8-bitreadfroma16-bitregisteroccurs.
Writing To and Reading From the FM75
All read and write operations must begin with a start signal
generated by the master device. After the start condition, the
master device must immediately send a slave address (7 bits)
followed by a read/write bit. If the slave address matches the
address of the FM75, the FM75 sends an ACK after receiving the
read/write bit by pulling the SDA line low for one clock. See Figure
8 – Figure 13 for timing diagrams for all FM75 operations.
For most operations, SMBus protocol requires the SDA line to
remain stable (unmoving) whenever SCL is high—i.e., transitions
on the SDA line can only occur when SCL is low. The exceptions
tothisrulearewhenthemasterdeviceissuesastartorstopsignal.
Note that the slave device cannot issue a start or stop condition.
Setting the Pointer
For all operations the pointer stored in the Command Register
must be pointing to the register (Temperature, Configuration, TOS
or THYST) that is going to be written to or read from. To change the
pointer value in the Command Register, the read/write bit follow-
ing the address must be 0. This indicates that the master will now
write new information into the Command Register.
The following are definitions for some general SMBus terms:
Start Condition: This condition occurs when the SDA line transi-
tions from high to low while SCL is high. The master device uses
this condition to indicate that a data transfer is about to begin.
AftertheFM75sendsanACKinresponsetoreceivingtheaddress
and read/write bit, the master device must transmit an appropriate
8-bit pointer value as explained in the Registers section of this
data sheet. The FM75 will send an ACK after receiving the new
pointer data.
Stop Condition: This condition occurs when the SDA line transi-
tions from low to high while SCL is high. The master device uses
this condition to signal the end of a data transfer.
Acknowledge and Not Acknowledge: When data is transferred
to the slave device it sends an acknowledge (ACK) after receiving
every byte of data. A master device sends an acknowledge (ACK)
following only the first byte read from a 2-byte register. The
receiving device sends an ACK by pulling SDA low for one clock.
Following the last byte, a master device sends a “not acknowl-
edge” (NACK) followed by a stop condition. A NACK is indicated
by leaving SDA high during the clock after the last byte.
The pointer set operation is illustrated in Figure 8. Anytime a
pointersetisperformed, itmustbeimmediatelyfollowedbyaread
or write operation. Note that the 6 MSBs of the pointer value must
be zero. Ifthe 6 MSBsare notzero, theFM75 will notsendan ACK
and will internally terminate the operation. Also recall that the
Command Register retains the current pointer value between
operations. Therefore, once a register is being pointed to, subse-
quent read operations do not require a pointer set cycle. Write
operations always require the pointer be reset.
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FM75 Rev. A.4
Reading
Writing
If the pointer is already pointing to the desired register, the master
can read from that register by setting the read/write bit (following
the slave address) to a 1. After sending an ACK, the FM75 will
begin transmitting data during the following clock cycle. If the
Configuration Register is being read, the FM75 will transmit one
byte of data (see Figure 10). The master device should respond
with a NACK followed by a stop condition. If the Temperature, TOS
or THYST Register is being read, the FM75 will transmit two bytes
of data (see Figure 9). The master must respond to the first byte
of data with an ACK and to the second byte of data with a NACK
followed by a stop condition.
All writes must be proceeded by a pointer set as described
previously, even if the pointer is already pointing to the desired
register.
Immediately following the pointer set, the master must begin
transmitting the data to be written. If the master is writing to the
Configuration Register, one byte of data must be sent (see Figure
13).IftheTOS orTHYST Registerisbeingwrittento,themastermust
send two bytes of data (see Figure 11). After transmitting each
byte of data, the master must release the SDA line for one clock
to allow the FM75 to acknowledge receiving the byte. The write
operation should be terminated by a stop signal from the master.
To read from a register other than the one currently being pointed
to by the Command Register, a pointer set to the desired register
must be done as described previously. Immediately following the
pointer set, the master must perform a repeat start condition (see
Figures 8 and 12) which indicates to the FM75 that a new
operation is about to occur. It is important to note that if the repeat
start condition does not occur, the FM75 will assume that a write
is taking place, and the selected register will be overwritten by the
upcoming data on the data bus. After the start condition, the
master must again send the device address and read/write bit.
This time the read/write bit must be set to 1 to indicate a read. The
rest of the read cycle is the same as described in the previous
paragraph for reading from a preset pointer location.
Inadvertent 8-Bit Read from a 16-Bit
Register: A Caution
An inadvertent 8-bit read from a 16-bit register, with the D7 bit low,
can cause the FM75 to pause in a state where the SDA line is
pulled low by the output data and is incapable of receiving either
astoporastartconditionfromthemaster. Theonlywaytoremove
the FM75 from this state is to continue clocking for 9 cycles until
SDAgoeshigh, atwhichtimeissuingastopconditionwillresetthe
FM75. This sequence can be seen in Figure 7 below.
Nine additional clock cycles to reset the FM75
SCL
1
0
0
1
A2 A1 A0
R/W
D7 D6 D5 D4 D3 D2 D1 D0
N
D7
D6 D5 D4 D3 D2 D1 D0
N
A
SDA
No Ack Stop
from Condition
No Ack
from
Master
Ack
from
FM75
Start
from
Master
Most Significant
Data Byte
(from FM75)
Address Byte
Master
from
Master
Master must
detect error
condition on
FM75
Stop intended by
Master, but FM75
SDA line locked
low
Figure 7. Inadvertent 8-Bit Read from 16-Bit Register Where D7 = 0 and Forces Output Low
10
www.fairchildsemi.com
FM75 Rev. A.4
Note: This segment of this timing diagram is a generic
pointer set cycle which must be followed by either an
immediate read cycle or write cycle as shown in this
figure and in figures 10, 11, and 12.
SCL
SDA
. . . .
A
0
0
0
R/W
0
0
0
P1 P0
A
S
A2 A1 A0
. . . .
1
0
0
1
Ack
from
aTS75
Ack
from
FM75
Address Byte
Pointer Byte
SCL
. . .
SDA
. . .
A2 A1
R/W
A
D3 D2 D1 D0
A
0
0
0
P
D4
S
1
0
1
A0
D7 D6 D5 D4
D7 D6 D5
0
N
0
No Ack
from
Master
Ack
from
Master
Ack
from
FM75
Repeat
Start
from
Most Significant Data
Least Significant Data Byte
(from FM75)
Address Byte
Byte
(from FM75)
Master
Figure 8. Pointer set followed by immediate read from a 2-byte register
(Temperature, TOS or THYST Register)
SCL
SDA
S
A2 A1 A0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4
0
0
0
0
N
P
1
0
0
1
R/W
No Ack
from
Master
Ack
from
Master
Ack
from
FM75
Most Significant Data
Byte
Least Significant Data
Byte
Address
Byte
(from FM75)
(from FM75)
Figure 9. Two-byte read from preset pointer location (Temperature, TOS or THYST Register)
SCL
S
A2
A1 A0
A
X
D6 D5
D4
D3 D2
D1 D0
N
P
1
0
0
1
R/W
SDA
No Ack
from
Master
Ack
from
FM75
Data Byte
Address Byte
(from FM75)
Figure 10. One-byte read from Configuration Register with preset pointer
11
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FM75 Rev. A.4
. . . .
. . . .
SCL
SDA
0
0
0
A2
A1
A0 R/W
A
0
0
0
P1
P0
A
1
0
0
1
S
Ack
from
FM75
Ack
from
FM75
Pointer Byte
Address Byte
. . . .
. . . .
A
D7
D6 D5
D4
D3 D2
D1
D0
A
D7 D6
D5 D4
0
0
0
0
P
A
Ack
from
FM75
Ack
from
FM75
Most Significant Data Byte
(from Master)
Least Significant Data Byte
(from Master)
Figure 11. Pointer set followed by immediate write to a 2-byte register (TOS or THYST Register)
SCL
SDA
S
A2
A1
A0
A
0
0
0
0
0
0
P1
A
1
0
0
1
R/W
P0
S
A2
A1
A0
1
0
0
1
R/W
Ack
from
FM75
Ack
from
FM75
Repeat Start
from
Master
Address Byte
Pointer Byte
Address Byte
. . . .
. . . .
A
D4 D3
D2
D1
P
A2
A1 A0
X
D6
D5
D0
0
1
R/W
N
1
0
No Ack
from
Master
Ack
from
FM75
Address Byte
(repeated here for
clarity, transmitted only
once in the actual sequence)
Data Byte
(from FM75)
Figure 12. Pointer set followed by immediate read from Configuration Register
SCL
0
0
0
P1
S
A2 A1 A0 R/W
A
0
0
0
A
X
P
1
0
0
1
D6 D5 D4 D3 D2 D1 D0
A
P0
SDA
Ack
from
FM75
Ack
from
FM75
Ack
from
FM75
Address Byte
Pointer Byte
Data Byte
(from Master)
Figure 13. Pointer set followed by immediate write to the Configuration Register
12
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FM75 Rev. A.4
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
5
0.228 - 0.244
(5.791 - 6.198)
1
2
3
4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45¡
8¡ Max, Typ.
All leads
Seating
Plane
0.004
(0.102)
All lead tips
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
FS Package Number M08A
8-Lead Molded Mini Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
FS Package Number MA08D
13
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FM75 Rev. A.4
Ordering Information
Part Number
FM75M8
Package
8-Lead SOP
8-Lead SOP
8-Lead MSOP
8-Lead MSOP
Temperature Range
-40°C to 125°C
How Supplied
95 units in Tube
1000 units on T&R
95 units in Tube
1000 units on T&R
FM75M8x
-40°C to 125°C
FM75MM8
FM75MM8x
-40°C to 125°C
-40°C to 125°C
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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14
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FM75 Rev. A.4
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