FM75_06 [FAIRCHILD]
Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm; 低电压双单线数字温度传感器，温度报警
| 型号： | FM75_06 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm |
| 文件： | 总16页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2006
FM75
tm
Low-Voltage Two-Wire Digital Temperature Sensor with
Thermal Alarm
Features
Description
■ User Configurable to 9, 10, 11 or 12-bit Resolution
The FM75 contains a high-precision CMOS temperature
sensor, a Delta-Sigma analog-to-digital converter, and a
SMBus-compatible serial digital interface. Typical accu-
racy is ±2°C over the full temperature range of 40°C to
125°C and to ±1°C over the range of 0°C to 100°C, with
9- to 12-bit resolution (default is 9).
■ Precision Calibrated to ±1°C, 0°C to 100°C
Typical
■ Temperature Range: -40°C to 125°C
■ Low Operating Current (less than 250µA)
■ Low Self Heating (0.2°C max. in still air)
■ Operating Voltage Range: 2.7V to 5.5V
Thermal alarm output, over-limit signal (OS) supports
interrupt and comparator modes. OS is active if the user-
programmable trip-temperature is exceeded. When the
temperature falls below the trip temperature, plus the
user-programmable hysteresis limit, the OS is disabled.
Applications
■ Battery Management
■ FAX Management
■ Printers
Available in a surface mount SOIC-8 (SOP-8) package.
■ Portable Medical Instruments
■ HVAC Systems
■ Power Supply Modules
■ Disk Drives
■ Computers
■ Automotive Components
Application Diagram
2.7 to 5.5V
8
7
6
5
A0
User
Programmable
A1
Address
A2
FM75
3
OS
8-Pin
1
2
SMBus
Interface
Configuration
SDA
SCL
4
Figure 1. Typical Application Diagram
Ordering Information
Part Number
Package
8-Lead SOIC
Temperature Range
Packing Method
FM75M8x
-40°C to +125°C
2500 Units, Tape and Reel
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
Pin Assignments
1
2
3
4
8
7
6
5
SDA
SCL
OS
V
DD
A0
A1
A2
FM75
GND
Figure 2. Pin Assignments
Pin Descriptions
Pin #
Name
Direction
Input/Output
Input
Description
1
2
3
SDA
SCL
OS
Serial Data. Open drain to I/O-data pin for two-wire interface.
Serial Clock. Clock for two-wire serial interface.
Output
Over-Limit Signal. Open drain thermostat output that indicates if
the temperature exceeds user-programmable limits. Default is
active LOW.
4
GND
Supply
Input
Ground
5, 6, 7
A0, A1, A2
Address Least Significant Bits (LSBs). User selectable address
pins for the three LSBs of the serial interface address.
8
VDD
Supply
Supply Voltage
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
2
Absolute Maximum Ratings
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed.
The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics
tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines
the conditions for actual device operation.
Parameter
Min.
Typ.
Max.
+7
Units
V
Supply Voltage
Output Voltage
Output Current
VCC + 0.5
10
V
mA
°C
Storage Temperature Range
-60
+150
220
Lead Soldering Temperature
°C
ESD(1)
Human Body Model
Machine Model
2000
250
V
V
Note:
1. Human Body Model: 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Machine Model: 200pF
capacitor discharged directly into each pin.
(2)
Electrical Characteristics
-40°C ð TA ð +125°C, VCC = 5.0V unless otherwise noted. Specifications are subject to change without notice.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
°C
TMIN, TMAX
Specified Temperature Range
Temperature Conversion Time(3)
Accuracy(4)
-40
+125
90
ms
TA = +25°C
-2
-3
-4
-4
+2
+3
+4
+4
TA = +100°C
°C
TA = -40°C (TMIN
)
TA = +125°C (TMAX
)
Notes:
2. These specifications are guaranteed only for the test conditions listed.
3. This specification only indicates how often temperature information is updated to the temperature register.
The FM75 can be read at any time without interrupting the temperature conversion process.
4. Accuracy (expressed in °C) = the difference between the FM75 output temperature and the measured temperature.
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
3
Logic Electrical Characteristics
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
VIH
Minimum Input Voltage
Logic HIGH
VDD x 0.7
VDD + 0.5
V
VIL
Maximum Input Voltage
Logic LOW
-0.3
VDD x 0.3
V
VOL
IDD
IDD-SD
IIN
Maximum Output Voltage
Logic LOW
VDD = 5V, IOL = -3mA
VDD = 3V, IOL = -1.5mA
0.36
0.36
V
V
Quiescent Supply Current
Interface Inactive R/W
Activity on SDA
250
350
500
700
µA
µA
µA
Shutdown Current
Interface Inactive R/W
Activity on SDA
0.15
83
1
150
Input Leakage Current
VIN = 0V or 5V, TA = 25°C
-40°C < TA < 125°C
±0.1
±1.0
IOL
ILEAK
tF
Output Sink Current
Output Leakage Current
Output Transition Time
Input Capacitance
TA = 25°C, VOL = 0.4V
VOH = 5V, VDD = 0V
CL = 400pF, IOL = -3mA
All Digital Inputs
3
5
mA
µA
ns
0.001
250
20
CIN
pF
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
4
Serial Port Timing
Symbol
tSCL
Parameter
Conditions
Min.
Typ.
Max.
100
Units
µs
SCL Clock Period
1.0
tT:LH, tT:HL
tLOW
SCL Clock Transition Time
SCL Clock LOW Period
SCL Clock HIGH Period
300
ns
0.470
0.400
1.0
µs
tHIGH
50
µs
tBUF
Bus free time between a Stop and
a new Start Condition
µs
tSU:DAT
tHD:DAT
tHD
Data In Set-up to SCL HIGH
Data In Hold Time
100
100
0
ns
ns
ns
ns
Data Out Stable after SCL LOW
tSU:STA
SCL LOW Set-up to SDA LOW
(Repeated Start Condition)
100
tHD:STA
tSU:STO
tPOR
SCL HIGH Hold after SDA LOW
(Start Condition)
100
100
ns
ns
SDA HIGH after SCL HIGH
(Stop Condition)
Time in which a FM75 must be
500
ms
operational after a power-on reset
tSCL
SCL
tSU:STA
tHD:STA
tSU:DAT
tSU:STO
SDA
Data In
tHD:DAT
tBUF
tT:HL
tT:LH
tLOW
tHIGH
90% 90%
10% 10%
SCL
SDA
Data Out
tHD
Figure 3. Serial Port Timing Diagram
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
5
Basic Operation
The FM75 temperature sensing circuitry continuously
produces analog voltage proportional to the device tem-
perature. At regular intervals, the FM75 converts the
analog voltage to a two’s complement digital value,
which is placed into the temperature register.
Table 1. Relationship Between Temperature
and Digital Output
Temperature
Digital Output
Number of
The FM75 has an SMBus-compatible digital serial inter-
face that allows access to the data in the temperature
register at any time. In addition, the serial interface pro-
vides access to all other FM75 registers to customize
operation of the device.
bits used
Always
zero
Sig
by
conversion bit bit bit bit
resolution
9
10 11 12
12-Bit Resolution
11-Bit Resolution
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
The FM75 temperature-to-digital conversion can have 9,
10, 11, or 12-bit resolution selected, providing 0.5°C,
0.25°C, 0.125°C, and 0.0625°C temperature resolution,
respectively. At power-up, the default conversion resolu-
tion is 9-bits. The conversion resolution is controlled by
the R0 and R1 bits in the configuration register.
0
0
0
0
1
0
0
0
0
0
1
0
All
Temperatures
10-Bit Resolution
0
0
0
0
1
0
0
0
0
1
0
9-Bit Resolution
111 1101
110 0100
011 0010
000 1100
000 0000
110 1011
101 1110
101 0010
100 1001
0
0
0
0
1
0
0
1
1
0
+125 C
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
Table 1 gives examples of the relationship between the
output digital data and the external temperature. The
9-bit, 10-bit, 11-bit, and 12-bit columns in Table 1 indicate
the right-most bit in the output data stream that can con-
tain temperature information for each conversion accu-
racy. Since the output digital data is in two’s-complement
format, the most significant bit of the temperature is the
“sign” bit. If the sign bit is zero, the temperature is posi-
tive; if the sign bit is one, the temperature is negative.
+100.0625 C
+50.125 C
+12.25 C
0 C
-20.5 C
-33.25C
-45.0625 C
-55C
The FM75 has a shutdown mode that reduces the oper-
ating current to 150nA. This mode is controlled by the
SD bit in the configuration register.
Power-Up Default Conditions
The FM75 powers up in the following default state:
The OS polarity is controlled by the POL bit in the config-
uration register. The programmable upper trip-point tem-
perature for the thermal alarm is stored in the TOS
register. The programmable hysteresis temperature (i.e.,
the lower trip point) is stored in the THYST register.
• Thermostat mode: comparator mode
• OS polarity: active LOW
• Fault tolerance: 1 fault (i.e., F0 = 0 and F1 = 0 in the
configuration register)
The thermal alarm has two modes of operation: compar-
ator mode and interrupt mode. At power-up, the default
is comparator mode. The alarm mode is controlled by the
CMP/INTR bit in the configuration register.
• TOS: 80°C
• THYST: 75°C
• Register pointer: 00 (temperature register)
• Conversion resolution: 9 bits (i.e., R0 = 0 and R1 = 0
in the configuration register)
Fault Tolerance
For both comparator and Interrupt modes, the alarm
“fault tolerance” setting plays a role in determining when
the OS output is activated. Fault tolerance refers to the
number of consecutive times an error condition must be
detected before the user is notified. Higher fault toler-
ance settings can help eliminate false alarms caused by
noise in the system. The alarm fault tolerance is con-
trolled by bits F0 and F1 in the configuration register.
These bits can be used to set the fault tolerance to 1, 2,
4, or 6, as shown in Table 4. At power-up, these bits both
default to 0 (fault tolerance = 1).
After power-up, these conditions can be reprogrammed
via the serial interface. Refer to the Serial Data Bus
Operation section for FM75 programming instructions.
Thermal Alarm Function
The FM75 thermal alarm function provides programma-
ble thermostat capability and allows the FM75 to function
as a stand-alone thermostat without using the serial
interface. The Over-Limit Signal (OS) output is the alarm
output. This signal is an open-drain output and, at
power-up, this pin is configured with active-low polarity.
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
6
Comparator Mode
Interrupt Mode
In comparator mode, each time a temperature-to-digital
(T-to-D) temperature conversion occurs, the new digital
temperature is compared to the value stored in the TOS
and THYST registers. If a fault tolerance number of con-
secutive temperature measurements are greater than
the value stored in the TOS register, the OS output is acti-
vated. For example, if bits F1 and F0 are equal to “10”
(fault tolerance = 4), four consecutive temperature mea-
surements must exceed TOS to activate the OS output.
Once the OS output is active, it remains active until the
first time the measured temperature drops below the
temperature stored in the THYST register. The operation
of the alarm in comparator mode with fault tolerance = 2
is illustrated in Figure 4.
In interrupt mode, the OS output first becomes active
after a fault tolerance number of consecutive tempera-
ture measurements exceed the value stored in the TOS
register (similar to comparator mode). Once OS is active,
it can only be cleared by a user read from any of the
FM75 registers (temperature, configuration, TOS, or
T
HYST) or by putting the FM75 into shutdown mode (i.e.,
by setting the shutdown bit in the configuration register to
“1”). Once cleared, the OS output can only be activated
the next time by a fault tolerance number of consecutive
temperature measurements lower than the value stored
in THYST. Once it is activated, the OS output can only be
deactivated by a user read or shutdown. In interrupt
mode, the activate/clear cycle for OS has the following
pattern: temperature > TOS, clear, temperature < THYST
,
clear, temperature > TOS, clear, etc. The operation of the
alarm in interrupt mode with fault tolerance = 2 is illus-
trated in Figure 4.
Temperature-to-Digital
Conversion
TOS
THYST
OS (Comparator Mode)
OS (Interrupt Mode)
For this example:
Fault Tolerance = 2
Output Polarity = Active Low
Read (or Shutdown)
Figure 4. Thermal Alarm Operation in Comparator and Interrupt Modes
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
7
Registers
The FM75 contains the following five registers:
All of these registers can be accessed by the user via the
digital serial interface at any time (see Serial Interface
Operation for instructions). A detailed description of
these registers and their functions is provided in the fol-
lowing sections. A diagram of the register hierarchy is
shown in Figure 5.
■ Command Register
■ Temperature Register
■ Configuration Register
■ Over-Limit-Signal Temperature Register (TOS
)
■ Hysteresis Temperature Register (THYST
)
SCL
SDA
Temperature Register
2-byte Read Only
Command Reg. = 00000000
Serial Interface
Read/Write
Data
Configuration Register
1-byte Read/Write
Command Reg. = 00000001
Command
(
Pointer
Data
)
T
Register
HYST
2-byte Read/Write
Command Reg. = 00000010
Command Register
1-byte Write Only
T
Register
OS
2-byte Read/Write
Command Reg. = 00000011
Figure 5. Register Hierarchy
Command Register
The command register is a one-byte (8-bit) write-only
register. The data stored in the command register indi-
cates which of the other registers (temperature, configu-
ration, TOS, or THYST) to read from or write to during an
upcoming operation. The command register “points” to
the selected register, as shown in Figure 11.
MSB
LSB
0
P1
0
0
0
0
0
P0
Figure 6. Command Register Format
The command register is illustrated in Figure 9. The P1
and P0 bits of the command register determine which
register is accessed, as shown in Table 2. The six Most
Significant Bits (MSBs) of the command register must
always be zero. Writing a one into any of these bits
causes the current operation to be terminated.
Table 2. Register Assignments for Command
Bits P1 and P2
Register
P1
0
P0
0
Temperature Register
Configuration Register
THYST Register
TOS Register
0
1
The command register retains pointer information
between operations; therefore, this register only needs
to be updated once for consecutive read operations from
the same register. All bits in the command register
default to zero at power-up.
1
0
1
1
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
8
Temperature Register
Configuration Register
The temperature register is a two-byte (16-bit) read-only
register. Digital temperatures from the T-to-D converter
are stored in the temperature register in two’s comple-
ment format and the contents of this register are updated
at regular intervals, each time the T-to-D conversion is
finished.
The configuration register is a one-byte (8-bit) read/write
register (see Figure 8). This register allows the user to
control the FM75 shutdown mode as well as the follow-
ing thermal alarm features: polarity, operating mode, and
fault tolerance. The configuration register contains two
bits that set the fault tolerance trip point. The fault toler-
ance trip point is the number of consecutive times the
internal circuit reads the temperature and finds the tem-
perature outside the limits programmed. The pro-
grammed limits are defined by the TOS register for the
upper limit and by the THYST register for the lower limit.
Table 4 shows the relationship between F1 and F0 and
the number of consecutive errors or “trips” needed to
activate the alarm. The configuration register also con-
tains the two bits that set the T-to-D conversion resolu-
tion to 9, 10, 11, or 12 bits. Table 3 shows the
relationship between R1 and T0 and the conversion res-
olution. All bits in the configuration register default to
zero at power-up.
The user can read data from the temperature register at
any time. When a T-to-D conversion is completed, the
new data is loaded into a comparator buffer to evaluate
fault conditions and updates the temperature register if a
read cycle is not ongoing. The FM75 is continuously
evaluating fault conditions regardless of read or write
activity on the bus. If a read is ongoing, the previous
temperature is read. The readable temperature is
updated upon the completion of the next T-to-D conver-
sion not masked by a read cycle.
The temperature register is illustrated in Figure 7.
Depending on the resolution of the T-to-D conversion,
the 9, 10, 11, or 12 MSBs of the register contain temper-
ature data. All unused bits following the digital tempera-
ture are zero. The MSB position of the temperature
register always contains the sign bit for the digital tem-
perature and bit 14 contains the temperature MSB. Bits
in the temperature register default to zero at power-up.
5
4
3
MSB
6
2
1
LSB
CMP/
INT
POL
X R1
SD
R0 F1 F0
R1 = Resolution bit 1 (see Table 3).
R0 = Resolution bit 0 (see Table 3).
F1 = Fault tolerance bit 1 (see Table 4).
F0 = Fault tolerance bit 0 (see Table 4).
POL = OS output polarity: 0 = active low, 1 = active
high.
13 12 11
MSB 14
10
9
8
TMSB
T
T
SB
T
T
T
T
CMP/INT = thermostat mode: 0 = comparator mode,
1 = inerrupt mode.
6
4
2
7
5
3
1
LSB
SD = shutdown: 0 = normal operation, 1 = shutdown
mode.
9-bit 10-bit
LSB LSB
12-bit
LSB
11-bit
LSB
0
0
0
0
Figure 8. Configuration Register Format
SB = Two’s complement sign bit
TMSB = Temperature MSB
T = Temperature data
Table 3. Conversion Resolution Settings
A-to-D
9-bit LSB = Temperature LSB for 9-bit conversions
10-bit LSB = Temperature LSB for 10-bit conversions
11-bit LSB = Temperature LSB for 11-bit conversions
12-bit LSB = Temperature LSB for 12-bit conversions
Conversion Resolution
R1
R0
0
9 Bits
10 Bits
11 Bits
12 Bits
0
0
1
1
0
Figure 7. Temperature Register Format
1
1
Table 4. Fault Tolerance Settings
Fault Tolerance
R1
0
R0
0
1
2
4
6
0
1
1
0
1
1
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
9
Over-Limit Signal Temperature Register (T
)
Hysteresis Temperature Register (T
)
HYST
OS
The TOS register is a two-byte (16-bit) read/write register
that stores the user-programmable upper trip-point tem-
perature for the thermal alarm in two’s-complement for-
mat. At power-up, this register defaults to 80°C (i.e. 0101
0000 0000 0000).
The THYST register is a two-byte (16-bit) read/write regis-
ter that stores the programmable lower trip-point temper-
ature for the thermal alarm in two’s-complement format.
At power-up, this register defaults to 75°C (i.e. 0100
1011 0000 0000).
The format of the TOS register is identical to that of the
temperature register (see Figure 9). The four LSBs of the
TOS register are hardwired to zero, so data written to
these register bits is ignored. The MSB position of the
TOS register contains the sign bit for the digital tempera-
ture and bit 14 contains the temperature MSB.
The THYST register is illustrated in Figure 9. The format
of this register is the same as that of the temperature
register. The four LSBs of the THYST register are hard-
wired to zero, so data written to these bits is ignored.
The resolution setting for the T-to-D conversion deter-
mines how many bits of the THYST register are used by
the thermal alarm. For example, for 9-bit conversions,
the hysteresis temperature is defined by the nine MSBs
of the THYST register and all remaining bits are ignored.
The resolution setting for the T-to-D conversion deter-
mines how many bits of the TOS register are used by the
thermal alarm. For example, for 9-bit conversions, the
trip-point temperature is defined by the nine MSBs of the
TOS register and all remaining bits are ignored.
.
13 12 11
MSB 14
10
9
8
TMSB
T
T
SB
T
T
T
T
6
4
2
7
5
3
1
LSB
9-bit 10-bit
LSB LSB
12-bit
LSB
11-bit
LSB
0
0
0
0
SB = Two’s complement sign bit
TMSB = Temperature MSB
T = Temperature data
9-bit LSB = Temperature LSB for 9-bit conversions
10-bit LSB = Temperature LSB for 10-bit conversions
11-bit LSB = Temperature LSB for 11-bit conversions
12-bit LSB = Temperature LSB for 12-bit conversions
Figure 9. THYST Register and TOS Register Format
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
10
Serial Data Bus Operation
General Operation
Slave Address
Writing to and reading from the FM75 registers is accom-
plished via the SMBus-compatible two-wire serial inter-
face. SMBus protocol requires that one device on the
bus initiates and controls all read and write operations.
This device is called the “master” device. The master
device also generates the SCL signal, which is the clock
signal for all other devices on the bus. All other devices
on the bus are called “slave” devices. The FM75 is a
slave device. Both the master and slave devices can
send and receive data on the bus.
Each slave device on the bus has a unique 7-bit address
so the master can identify which device is sending or
receiving data.
The FM75 address is as follows:
0
A0
1 A2 A1
1
0
The four MSBs of the FM75 address are hardwired to
1001. The three LSBs are user configurable by tying the
A0, A1, and A2 pins to either VDD or ground. This pro-
vides eight different FM75 addresses, which allows up to
eight FM75s to be connected to the same bus.
During SMBus operations, one data bit is transmitted per
clock cycle. All SMBus operations follow a repeating nine
clock-cycle pattern that consists of eight bits (one byte)
of transmitted data followed by an acknowledge (ACK) or
not acknowledge (NACK) from the receiving device.
Note that there are no unused clock cycles during any
operation—therefore there must be no breaks in the
stream of data and ACKs/NACKs during data transfers.
Conversely, too few clock cycles can lead to incorrect
operation if an inadvertent 8-bit read from a 16-bit regis-
ter occurs.
Writing to and Reading from the FM75
All read and write operations must begin with a start sig-
nal generated by the master device. After the start condi-
tion, the master device must immediately send a slave
address (7 bits), followed by a read/write bit. If the slave
address matches the address of the FM75, the FM75
sends an ACK after receiving the read/write bit by pulling
the SDA line LOW for one clock cycle. Figures 11 -16
provide timing diagrams for all FM75 operations.
For most operations, SMBus protocol requires the SDA
line to remain stable (unmoving) whenever SCL is HIGH—
i.e., transitions on the SDA line can only occur when SCL
is LOW. The exceptions to this rule are when the master
device issues a start or stop signal. The slave device
cannot issue a start or stop signal.
Setting the Pointer
For all operations, the pointer stored in the command
register must be pointing to the register (temperature,
configuration, TOS or THYST) that is going to be written to
or read from. To change the pointer value in the com-
mand register, the read/write bit following the address
must be 0. This indicates that the master will write new
information into the command register.
Start Condition: This condition occurs when the SDA
line transitions from HIGH to LOW while SCL is HIGH.
The master device uses this condition to indicate that a
data transfer is about to begin.
After the FM75 sends an ACK in response to receiving
the address and read/write bit, the master device must
transmit an appropriate 8-bit pointer value, as explained
in the Registers section. The FM75 sends an ACK after
receiving the new pointer data.
Stop Condition: This condition occurs when the SDA
line transitions from LOW to HIGH while SCL is HIGH.
The master device uses this condition to signal the end
of a data transfer.
Acknowledge and Not Acknowledge: When data is
transferred to the slave device, it sends an acknowledge
(ACK) after receiving every byte of data. A master device
sends an acknowledge (ACK) following only the first byte
read from a two-byte register. The receiving device
sends an ACK by pulling SDA LOW for one clock cycle.
Following the last byte, a master device sends a “not
acknowledge” (NACK) followed by a stop condition. A
NACK is indicated by leaving SDA HIGH during the clock
after the last byte.
The pointer set operation is illustrated in Figure 11. Any-
time a pointer set is performed, it must be immediately
followed by a read or write operation. Note that the six
MSBs of the pointer value must be zero. If the six MSBs
are not zero, the FM75 does not send an ACK and inter-
nally terminates the operation. The command register
retains the current pointer value between operations;
therefore, once a register is indicated, subsequent read
operations do not require a pointer set cycle. Write oper-
ations always require the pointer be reset.
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
11
Reading
Writing
If the pointer is already pointing to the desired register,
the master can read from that register by setting the
read/write bit (following the slave address) to a one. After
sending an ACK, the FM75 begins transmitting data dur-
ing the following clock cycle. If the configuration register
is being read, the FM75 transmits one byte of data (see
Figure 13). The master should respond with a NACK, fol-
lowed by a stop condition. If the temperature, TOS, or
THYST register is being read, the FM75 transmits two
bytes of data (see Figure 12). The master must respond
to the first byte of data with an ACK and to the second
byte of data with a NACK followed by a stop condition.
All writes must be proceeded by a pointer set, even if the
pointer is already pointing to the desired register.
Immediately following the pointer set, the master must
begin transmitting the data to be written. If the master is
writing to the configuration register, one byte of data
must be sent (see Figure 16). If the TOS or THYST regis-
ter is being written, the master must send two bytes of
data (see Figure 14). After transmitting each byte of
data, the master must release the Serial Data (SDA) line
for one clock cycle to allow the FM75 to acknowledge
receiving the byte. The write operation should be termi-
nated by a stop signal from the master.
To read from a register other than the one currently indi-
cated by the command register, a pointer to the desired
register must be set. Immediately following the pointer
set, the master must perform a repeat start condition
(see Figure 11 and Figure 15), which indicates to the
FM75 that a new operation is about to occur. If the
repeat start condition does not occur, the FM75 assumes
that a write is taking place and the selected register is
overwritten by the upcoming data on the data bus. After
the start condition, the master must again send the
device address and read/write bit. This time, the read/
write bit must be set to one to indicate a read. The rest of
the read cycle is the same as described in the previous
paragraph for reading from a preset pointer location.
Caution: Inadvertent 8-Bit Read from a
16-Bit Register
An inadvertent 8-bit read from a 16-bit register, with the
D7 bit LOW, can cause the FM75 to pause in a state
where the SDA line is pulled LOW by the output data and
is incapable of receiving either a stop or a start condition
from the master. The only way to remove the FM75 from
this state is to continue clocking for nine cycles until SDA
goes HIGH, at which time issuing a stop condition resets
the FM75, shown in Figure 10.
Nine additional clock cycles to reset the FM75
SCL
1
0
0
1
A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
N
D7
D6 D5 D4 D3 D2 D1 D0
N
A
SDA
R/W
No Ack Stop
from Condition
No Ack
from
Master
Ack
from
FM75
Start
from
Master
Most Significant
Data Byte
(from FM75)
Address Byte
Master
from
Master
Master must
detect error
condition on
FM75
Stop intended by
Master, but FM75
SDA line locked
low
Figure 10. Inadvertent 8-Bit Read from 16-Bit Register Where D7 = 0 and Forces Output LOW
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
12
Timing Diagrams
Note: This segment of this timing diagram is a generic
pointer set cycle that must be followed by either an
immediate read cycle or write cycle, as shown in this
figure and in figures 10, 11, and 12.
SCL
. . . .
A
0
0
0
SDA
S
R/W
0
0
0
P1 P0
A
A2 A1 A0
. . . .
1
0
0
1
Ack
from
aTS75
Ack
from
FM75
Address Byte
Pointer Byte
SCL
. . .
SDA
. . .
A2 A1
R/W
A
D3 D2 D1 D0
A
0
0
0
P
D4
S
1
0
1
A0
D7 D6 D5 D4
D7 D6 D5
0
N
0
No Ack
from
Master
Ack
from
Master
Ack
from
FM75
Repeat
Start
from
Most Significant Data
Least Significant Data Byte
(from FM75)
Address Byte
Byte
(from FM75)
Master
Figure 11. Pointer Set Followed by Immediate Read from a Two-byte Register
(Temperature, TOS, or THYST Register)
SCL
SDA
S
A2 A1 A0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4
0
0
0
0
N
P
1
0
0
1
R/W
No Ack
from
Master
Ack
from
Master
Ack
from
FM75
Most Significant Data
Byte
Least Significant Data
Byte
Address
Byte
(from FM75)
(from FM75)
Figure 12. Two-byte Read from Preset Pointer Location (Temperature, TOS, or THYST Register)
SCL
S
A2
A1 A0
A
X
D6 D5
D4
D3 D2
D1 D0
N
P
1
0
0
1
R/W
SDA
No Ack
from
Master
Ack
from
FM75
Data Byte
Address Byte
(from FM75)
Figure 13. One-byte Read from Configuration Register with Preset Pointer
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
13
Timing Diagrams (Continued)
. . . .
. . . .
SCL
0
0
0
A2
A1
A0 R/W
A
0
0
0
P1
P0
A
1
0
0
1
S
SDA
Ack
from
FM75
Ack
from
FM75
Pointer Byte
Address Byte
. . . .
. . . .
A
D7
D6 D5
D4
D3 D2
D1
D0
A
D7 D6
D5 D4
0
0
0
0
P
A
Ack
from
FM75
Ack
from
FM75
Most Significant Data Byte
(from Master)
Least Significant Data Byte
(from Master)
Figure 14. Pointer Set Followed by Immediate Write to A 2-byte Register (TOS or THYST Register)
SCL
S
A2
A1
A0
A
0
0
0
0
0
0
P1
A
1
0
0
1
R/W
P0
S
A2
A1
A0
SDA
1
0
0
1
R/W
Ack
from
FM75
Ack
from
FM75
Repeat Start
from
Master
Address Byte
Pointer Byte
Address Byte
. . . .
. . . .
A
D4 D3
D2
D1
P
A2
A1 A0
X
D6
D5
D0
0
1
R/W
N
1
0
No Ack
from
Master
Ack
from
FM75
Address Byte
(repeated here for
clarity, transmitted only
once in the actual sequence)
Data Byte
(from FM75)
Figure 15. Pointer Set Followed by Immediate Read from Configuration Register
SCL
SDA
0
0
0
P1
S
A2 A1 A0 R/W
A
0
0
0
A
X
P
1
0
0
1
D6 D5 D4 D3 D2 D1 D0
A
P0
Ack
from
FM75
Ack
from
FM75
Ack
from
FM75
Address Byte
Pointer Byte
Data Byte
(from Master)
Figure 16. Pointer Set Followed by Immediate Write to the Configuration Register
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
14
Mechanical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 17. Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
15
© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
www.fairchildsemi.com
16
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