FAN53541UCX [FAIRCHILD]
Switching Regulator, Voltage-mode, 5A, 3000kHz Switching Freq-Max, PBGA20, WLCSP-20;
| 型号： | FAN53541UCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Switching Regulator, Voltage-mode, 5A, 3000kHz Switching Freq-Max, PBGA20, WLCSP-20 开关 |
| 文件： | 总15页 (文件大小：1477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2014
FAN53541
2.4 MHz, 5 A TinyBuck™ Synchronous Buck Regulator
Description
Features
The FAN53541 is a step-down switching voltage regulator
that delivers an adjustable output from an input voltage
supply of 2.7 V to 5.5 V. Using a proprietary architecture with
synchronous rectification, the FAN53541 is capable of
delivering 5 A at over 90% efficiency, while maintaining a
very high efficiency of over 80% at load currents as low as
2 mA. The regulator operates at a nominal fixed frequency of
2.4 MHz, which reduces the value of the external
components to 470 nH for the output inductor and 20 µF for
the output capacitor. Additional output capacitance can be
added to improve regulation during load transients without
affecting stability and inductance up to 1.2 µH may be used
with additional output capacitance.
.
.
.
.
.
.
2.4 MHz Fixed-Frequency Operation
Best-in-Class Load Transient Response
5 A Output Current Capability
2.7 V to 5.5 V Input Voltage Range
Adjustable Output Voltage: 0.8 V to 90% of VIN
PFM Mode for High Efficiency in Light Load
(Forced PWM Available on MODE Pin)
.
.
.
50 µA Typical Quiescent Current in PFM Mode
External Frequency Synchronization
Low Ripple Light-Load PFM Mode with Forced
PWM Control
At moderate and light loads, pulse frequency modulation
(PFM) is used to operate the device in power-save mode
with a typical quiescent current of 50 µA. Even with such a
low quiescent current, the part exhibits excellent transient
response during large load swings. At higher loads, the
system automatically switches to fixed-frequency control,
operating at 2.4 MHz. In shutdown mode, the supply current
drops below 1 µA, reducing power consumption. PFM mode
can be disabled if constant frequency is desired. The
FAN53541 is available in a 20-bump 1.96 mm x 1.56 mm
Wafer-Level Chip-Scale Package (WLCSP).
.
.
.
.
.
.
Power Good Output
Internal Soft-Start
Input Under-Voltage Lockout (UVLO)
Thermal Shutdown and Overload Protection
No External Compensation Required
20-Bump WLCSP
Applications
.
.
.
.
Set-Top Box
PGOOD
Hard Disk Drive
Communications Cards
DSP Power
VIN
L1
SW
CIN
CIN1
0.47H
COUT
10µF
COUT
10µF
10nF
10µF
GND
FAN53541
VOUT
FB
EN
R1
MODE
Figure 1. Typical Application
Ordering Information
Part Number
Temperature Range
Package
Packing Method
20-Ball Wafer-Level, Chip-Scale Package (WLCSP),
4x5 Array, 0.4 mm Pitch, 250 µm Ball
FAN53541UCX
-40 to 85°C
Tape and Reel
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
Recommended External Components
Table 1. Recommended External Components for 5 A Maximum Load Current
Component
Description
Vendor
Parameter Typical Unit
0.47
20
L1
COUT
CIN
470 nH Nominal
10 F, 6.3V, X5R, 0805, 2 Pieces
10 F, 6.3 V, X5R, 0805
10 nF, 25 V, X7R, 0402
See Table 2
L
H
F
F
nF
C
C
C
GRM21BR60J106M (Murata)
C2012X5R0J106M (TDK)
10
CIN1
Any
10
Table 2. Recommended Inductors
Component Dimensions
(1)
Manufacturer
Part#
L (nH) DCR (mΩ) IMAXDC
L
W
H
Bourns
Bourns
SRP5012-R47M
SRP4012-R47M
XPL4020-471ML
SC2511-R47M
470
470
470
470
470
470
19
20
19
2.6
15
20
6.0
5.5
7.2
16.0
5.4
5.0
5.1
4.6
4.2
6.5
5.0
4.5
4.5
4.0
4.2
6.5
5.0
4.1
1.2
1.2
2.0
3.0
2.0
1.2
Coilcraft
Inter-Technical(2)
TDK
VLC5020T-R47M
IHLP1616ABERR47M01
Vishay
Notes:
1. IMAXDC is the lesser current to produce 40°C temperature rise or 30% inductance roll-off.
2. Inductor used for efficiency and temperature rise measurements.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
2
Pin Configuration
PGOOD EN
FB
A3
VOUT
A4
A4
B4
C4
D4
E4
A3
B3
C3
D3
E3
A2
B2
C2
D2
E2
A1
B1
C1
D1
E1
A1
A2
B2
C2
D2
E2
MODE
B1
GND
B3
B4
C4
C1
C3
D3
E3
VIN
SW
D1
E1
D4
E4
Figure 2. Top View
Figure 3. Top View Bottom View
Pin Definitions
Bump #
A1
Name
Description
PGOOD Power Good. This open-drain pin pulls LOW if the output falls out of regulation or is in soft-start.
A2
EN
FB
Enable. The device is in Shutdown Mode when this pin is LOW. Do not leave this pin floating.
FB. Connect to resistor divider. The IC regulates this pin to 0.8 V.
A3
A4
VOUT
VOUT. Sense pin for VOUT. Connect directly to COUT
.
MODE / SYNC. A logic 0 allows the IC to automatically switch to PFM during light loads. When held
B1
MODE HIGH, the IC to stays in PWM Mode. The regulator also synchronizes its switching frequency to four
times (4X) the frequency provided on this pin (fMODE). Do not leave this pin floating.
B2, B3,
C1 – C4
Ground. Low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal
path to these pins.
GND
Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through
this pin.
B4
AGND
D1, D2,
E1, E2
VIN
SW
Power Input Voltage. Connect to input power source. Connect to CIN with minimal path.
Switching Node. Connect to inductor.
D3, D4,
E3, E4
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum
ratings are stress ratings only.
Symbol
Parameter
Min.
-0.3
-0.3
-0.3
Max.
7.0(3)
4.5
Unit
SW, VIN Pins
Other Pins
Tied without Series Impedance
VIN
V
VIN⁽4⁾
Tied through Series Resistance ≥100
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
2250
1500
Electrostatic Discharge
Protection Level
ESD
V
TJ
TSTG
TL
Junction Temperature
Storage Temperature
–40
–65
+150
+150
+260
°C
°C
°C
Lead Soldering Temperature, 10 Seconds
Note:
3. VIN slew rate is limited to 1 V/µs.
4. Lesser of 7 V or VIN+0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
VIN
Supply Voltage Range
Output Voltage Range
2.7
5.5
V
90% Duty
Cycle
VOUT
0.8
0
V
IOUT
L
Output Current
Inductor
5
A
0.47
10
1.20
µH
µF
µF
°C
°C
CIN
COUT
TA
Input Capacitor
Output Capacitor
20
Operating Ambient Temperature
Operating Junction Temperature
-40
-40
+85
TJ
+125
Thermal Properties
Symbol
Parameter
Typical
Unit
Junction-to-Ambient Thermal Resistance
38(5)
°C/W
JA
Note:
5. See Thermal Considerations in the Applications section.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
4
Electrical Characteristics
Minimum and maximum values are at VIN=2.7 V to 5.5 V, and TA=-40°C to +85°C, unless otherwise noted. Typical values are
at TA=25°C, VIN=5 V, and VOUT=1.2 V.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Power Supplies
ILOAD=0, MODE=0 (AUTO PFM/PWM)
ILOAD=0, MODE=1 (Forced PWM)
EN=GND
50
30
µA
mA
µA
V
IQ
Quiescent Current
I SD
Shutdown Supply Current
0.1
2.67
2.3
365
10
VIN Rising
2.80
VUVLO Under-Voltage Lockout Threshold
VIN Falling
2.1
V
VUVHYST Under-Voltage Lockout Hysteresis
mV
Logic Pins
VIH
VIL
High-Level Input Voltage
Low-Level Input Voltage
1.05
V
0.4
V
VLHYST Logic Input Hysteresis Voltage
140
mV
µA
mA
µA
IIN
Input Bias Current
Input Tied to GND or 1 kΩ Resistor to VIN
VPGOOD=0.4 V
0.01
1.00
1.00
IOUTL
IOUTH
PGOOD Pull-Down Current
PGOOD HIGH Leakage Current
1
VPGOOD=VIN
0.01
VOUT Regulation
TA=25°C, Forced PWM
TA=-40°C to 85°C, Forced PWM
AUTO PFM/PWM
0.792 0.800 0.808
0.787 0.800 0.813
0.784 0.800 0.824
V
V
V
Output Reference DC Accuracy,
Measured at FB Pin
VREF
VOUT
ILOAD
Load Regulation
Line Regulation
MODE=VIN (Forced PWM)
–0.02
%/A
%/V
VOUT
2.7 V ≤ VIN ≤ 5.5 V, IOUT(DC)=1.5 A
-0.16
V
IN
IREF
FB Pin Leakage Current
Transient Response
FB=0.8 V
1
nA
ILOAD Step 0.1 A to 1.5 A, tR=100 ns
-30
mV
VOUT
Power Switch and Protection
RDS(ON)P P-Channel MOSFET On Resistance
RDS(ON)N N-Channel MOSFET On Resistance
33
28
mΩ
mΩ
A
Open Loop
5.8
5.5
7.5
8
8.8
ILIMPK
P-MOS Peak Current Limit
Closed Loop
A
TLIMIT
THYST
Thermal Shutdown
155
20
°C
°C
V
Thermal Shutdown Hysteresis
Rising Threshold
Falling Threshold
6.1
5.8
VSDWN Input OVP Shutdown
V
Frequency Control
fSW
Oscillator Frequency
2.1
2.4
3.0 MHz
700 kHz
External Square-Wave, 30% to 70% Duty
Cycle
fMODE
MODE Pin Synchronization Range
525
600
Soft-Start and Output Discharge
Regulator Enable to Regulated VOUT
(Rising PGOOD)
tSS
1.2
ms
RDIS
Output Discharge Resistance
EN=0 V
175
Ω
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
5
Typical Characteristics
Unless otherwise specified; VIN=5 V, VOUT=1.2 V, VMODE=0 V, TA=25°C, circuit in Figure 1, and components per Table 1.
95%
90%
85%
80%
75%
70%
95%
90%
85%
80%
75%
70%
2.7 VIN
3.3 VIN
5.0 VIN
5.5 VIN
-40C
+25C
+85C
0
0
0
1000
2000
3000
4000
5000
0
0
0
1000
2000
3000
4000
5000
5000
5000
Load Current (mA)
Load Current (mA)
Figure 4. Efficiency vs. ILOAD, 1.2 VOUT
Figure 5. Efficiency vs. ILOAD, 1.2 VOUT
95%
90%
85%
80%
75%
70%
95%
90%
85%
80%
75%
70%
2.7 VIN
3.3 VIN
5.0 VIN
5.5 VIN
-40C
+25C
+85C
1000
2000
3000
4000
5000
1000
2000
3000
4000
Load Current (mA)
Load Current (mA)
Figure 6. Efficiency vs. ILOAD, 1.8 VOUT
Figure 7. Efficiency vs. ILOAD, 1.8 VOUT
100%
95%
90%
85%
80%
75%
100%
95%
90%
85%
80%
75%
4.2 VIN
5.0 VIN
5.5 VIN
-40C
+25C
+85C
1000
2000
3000
4000
5000
1000
2000
3000
4000
Load Current (mA)
Load Current (mA)
Figure 8. Efficiency vs. ILOAD, 3.3 VOUT
Figure 9. Efficiency vs. ILOAD, 3.3 VOUT
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
6
Typical Characteristics
Unless otherwise specified; VIN=5 V, VOUT=1.2 V, VMODE=0 V, TA=25°C, circuit in Figure 1, and components per Table 1.
70
65
60
55
50
45
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
4.2 VIN
5.0 VIN
5.5 VIN
2.7 VIN
3.3 VIN
5.0 VIN
5.5 VIN
0
0
-5
-5
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
Load Current (mA)
Load Current (mA)
Figure 10. Regulation, 1.2 VOUT
Figure 11. Regulation, 3.3 VOUT
1,400
1,400
1,200
1,000
800
600
400
200
0
1,200
1,000
800
600
400
200
0
PFM Exit
PFM Enter
5.0
PFM Exit
PFM Enter
2.5
3.0
3.5
4.0
4.5
5.5
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Input Voltage (V)
Figure 12. PFM / PWM Boundaries, 1.2 VOUT
Figure 13. PFM / PWM Boundaries, 3.3 VOUT
30
25
20
15
10
5
3,000
2,500
2,000
1,500
1,000
500
3.6VIN, Auto
3.6VIN, PWM
5.0VIN, Auto
5.0VIN, PWM
3.6VIN, Auto
5.0VIN, Auto
0
0
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
Load Current (mA)
Load Current (mA)
Figure 14. Output Voltage Ripple
Figure 15. Switching Frequency
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
7
Typical Characteristics
Unless otherwise specified; VIN=5 V, VOUT=1.2 V, VMODE=0 V, TA=25°C, circuit in Figure 1, and components per Table 1.
60
50
40
30
20
10
50
40
30
20
10
0
-40C
+25C
+85C
-40C
+25C
+85C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Input Voltage (V)
Figure 16. Quiescent Current, Auto Mode, EN=VIN
Figure 17. Quiescent Current, PMW Mode, EN=VIN
70
100%
1.2VOUT,
25mA Load
1.2VOUT,
1.0A Load
3.3VOUT,
1.0A Load
60
95%
90%
85%
80%
75%
70%
50
40
30
20
10
1.2 VOUT, L=SC2511
1.2 VOUT, L=IHLP16
1.8 VOUT, L=SC2511
1.8 VOUT, L=IHLP16
3.3 VOUT, L=SC2511
3.3 VOUT, L=IHLP16
10
100
1,000
10,000
100,000
0
1000
2000
3000
4000
5000
Frequency (Hz)
Load Current (mA)
Figure 18. Power Supply Rejection (PSRR)
Figure 19. Inductor Efficiency Comparison, 5.0 VIN
Figure 20. Line Transient, 50 Load, tR=tF=10 s
Figure 21. Line Transient, ILOAD=1.0 A, tR=tF=10 s
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
8
Typical Characteristics
Unless otherwise specified; VIN=5 V, VOUT=1.2 V, VMODE=0 V, TA=25°C, circuit in Figure 1, and components per Table 1.
Figure 22. Load Transient, 0.1-1.5 A Load,
tR=tF=100 ns
Figure 23. Load Transient, 0.1-3.0 A Load,
tR=tF=100 ns, COUT=2x22 F
Figure 24. Startup / Shutdown, No Load
Figure 25. Startup / Shutdown, 240 m Load,
COUT=2x22 F
Figure 26. Overload Protection and Recovery
Figure 27. Startup into Overload
© 2013 Fairchild Semiconductor Corporation
FAN53541 • Rev. 1.0.2
www.fairchildsemi.com
9
Operation Description
The FAN53541 is a step-down switching voltage regulator
that delivers an adjustable output from an input voltage
supply of 2.7 V to 5.5 V. Using a proprietary architecture with
synchronous rectification, the FAN53541 is capable of
delivering up to 5 A at over 90% efficiency. The regulator
operates at a nominal frequency of 2.4 MHz at full load,
which reduces the value of the external components to
470 nH for the output inductor and 20 µF for the output
capacitor. High efficiency is maintained at light load with
single-pulse PFM Mode.
limits the COUT capacitance when a heavy load ( ILOAD(SS) ) is
applied during the startup.
The maximum COUT capacitance for successful starting with
a heavy constant-current load is approximately:
800
5.8 ILOAD
C
OUT MAX
(3)
VOUT
where COUTMAX is expressed in F and ILOAD is
the load current during soft-start, expressed in A.
Control Scheme
The FAN53541 uses
frequency PWM modulator to deliver very fast load transient
response, while maintaining a constant switching frequency
over a wide range of operating conditions.
Diode Emulation Mode is employed during soft-start,
allowing the IC to start into a pre-charged output. Diode
emulation prohibits reverse inductor current from flowing
through the synchronous rectifier.
a proprietary non-linear, fixed-
When EN is LOW, a 150 resistor discharges VOUT
.
Regulator performance is independent of the output
capacitor ESR, allowing for the use of ceramic output
capacitors. Although this type of operation normally results in
a switching frequency that varies with input voltage and load
current, an internal frequency loop holds the switching
frequency constant over a large range of input voltages and
load currents.
Under-Voltage Lockout (UVLO)
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage rises high
enough to operate properly. This ensures no misbehavior of
the regulator during startup or shutdown.
Input Over-Voltage Protection (OVP)
For very light loads, the FAN53541 operates in
Discontinuous Current (DCM) single-pulse PFM Mode, which
produces low output ripple compared with other PFM
architectures. Transition between PWM and PFM is
seamless, with a glitch of less than 3% of VOUT during the
transition between DCM and CCM Modes.
When VIN exceeds VSDWN (about 6.1 V), the IC stops
switching to protect the circuitry from excessive internal
voltage spikes. An internal filter prevents the circuit from
shutting down due to VIN noise spikes.
Current Limiting
PFM Mode is disabled by holding the MODE pin HIGH. The
IC synchronizes to the MODE pin frequency. When
synchronizing to the MODE pin, PFM Mode is disabled.
A heavy load or short circuit on the output causes the current
in the inductor to increase until a maximum current threshold
is reached in the high-side switch. Upon reaching this point,
the high-side switch turns off, preventing high currents from
causing damage. 16 consecutive PWM cycles in current limit
cause the regulator to shut down and stay off for about
1.6 ms before attempting a restart.
Setting Output Voltage
The output voltage is set by the R1, R2, and VREF (0.8 V):
V
V
REF
R1
R2
OUT
(1)
In the event of a short circuit, the soft-start circuit attempts to
restart and produces an over-current fault after 16
consecutive cycles in current limit, which results in a duty
cycle of less than 5%, providing current into a short circuit.
V
REF
R1 must be set at or below 100 KΩ; therefore:
R1 0.8
R2
(2)
External Frequency Synchronization
V
0.8
OUT
Logic 1 on the MODE pin forces the IC to stay in PWM
Mode. Logic 0 allows the IC to automatically switch to PFM
during light loads. If the MODE pin is toggled, the converter
synchronizes its switching frequency to four times the
frequency on the mode pin (fMODE).
For example, for VOUT=1.2 V, R1=100 kΩ, R2=200 kΩ.
Enable and Soft-Start
When the EN pin is LOW, the IC is shut down, all internal
circuits are off, and the part draws very little current. Raising
EN above its threshold voltage activates the part and starts
the soft-start cycle. During soft-start, the modulator’s internal
reference is ramped slowly to minimize surge currents on the
input and prevents overshoot of the output voltage.
The MODE pin is internally buffered with a Schmitt trigger,
which allows the MODE pin to be driven with slow rise and
fall times. An asymmetric duty cycle for frequency
synchronization is permitted, provided it is consistent with
parametric table limits.
If large values of output capacitance are used, the regulator
may fail to start. If VOUT fails to achieve regulation within
1.2 ms from the beginning of soft-start, the regulator shuts
down and waits 1.6 ms before attempting a restart. If the
regulator is in current limit for 16 consecutive PWM cycles,
the regulator shuts down before restarting 1.6 ms later. This
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
10
PGOOD Pin
Application Information
Selecting the Inductor
The PGOOD pin is an open-drain that indicates that the IC is
in regulation when its state is open. PGOOD pulls LOW
under the following conditions:
The output inductor must meet both the required inductance
and the energy handling capability of the application. The
inductor value affects the average current limit, output
voltage ripple, transient response, and efficiency.
.
.
.
The IC has operated in cycle-by-cycle current limit for
eight consecutive PWM cycles;
The circuit is disabled, either after a fault occurs or when
EN is LOW; or
The ripple current (∆I) of the regulator is:
The IC is performing a soft-start.
VOUT
V
IN VOUT
L fSW
I
(5)
V
Thermal Shutdown
IN
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the output
switching is disabled until the temperature on the die has
fallen sufficiently. The junction temperature at which the
thermal shutdown activates is nominally 155°C with a
20°C hysteresis.
The maximum average load current, IMAX(LOAD), is related to
the peak current limit, ILIM(PK), by the ripple current as:
I
IMAX(LOAD) ILIM(PK)
(6)
2
The FAN53541 is optimized for operation with L=470 nH, but
is stable with inductances up to 1.2 H (nominal). The
inductor should be rated to maintain at least 80% of its value
at ILIM(PK). Failure to do so lowers the amount of DC current
the IC can deliver.
Minimum Off-Time Effect on Switching
Frequency
tOFF(MIN) is 45 ns, which constrains the maximum VOUT/VIN
that the FAN53541 can provide, while still maintaining a fixed
switching frequency in PWM Mode. Regulation is maintained
even though the regulator is unable to provide sufficient
duty-cycle and operate at 2.4 MHz.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since ∆I increases, the
RMS current increases, as do core and skin-effect losses.
Switching frequency is the lower of 2.4 MHz or:
I2
12
2
(7)
IRMS
IOUT(DC)
VOUT IOUT ROFF
IN IOUT (ROFF RON
(4)
fSW(MHz) 22.2 1
V
)
The increased RMS current produces higher losses through
the RDS(ON) of the IC MOSFETs as well as the inductor ESR.
where:
Increasing the inductor value produces lower RMS currents,
but degrades transient response. For a given physical
inductor size, increased inductance usually results in an
inductor with lower saturation current.
IOUT = load current, in A;
RON = RDS(ON)_P + DCRL, in Ohms; and
ROFF = RDS(ON)_N + DCRL, in Ohms.
Table 3 shows the effects on regulator performance of higher
inductance than the recommended 470 nH.
A result of <0 MHz indicates 100% duty cycle operation.
Table 3. Inductor Value and Regulator
Performance
Transient Response
IMAX(LOAD)
∆VOUT (Eq.(8))
Increase
Decrease
Degraded
Inductor Current Rating
The FAN53541’s current-limit circuit can allow a peak current
of about 8.8 A to flow through L1 under worst-case
conditions. If it is possible for the load to draw that much
continuous current, the inductor should be capable of
sustaining that current or failing in a safe manner.
For space-constrained applications, a lower current rating for
L1 can be used. The FAN53541 may still protect these
inductors in the event of a short circuit, but may not be able
to protect the inductor from failure if the load is able to draw
higher currents than the DC rating of the inductor.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
11
Output Capacitor and VOUT Ripple
Layout Recommendations
Table 1 suggests 0805 capacitors, but 0603 capacitors may
be used if space is at a premium. Due to voltage effects, the
0603 capacitors have a lower in-circuit capacitance, which
can degrade transient response and output ripple.
The layout example below illustrates the recommended
component placement and top copper (green) routing. The
inductor in this example is the TDK VLC5020T-R47N.
To minimize VIN and SW spikes and thereby reduce voltage
stress on the IC’s power switches, it is critical to minimize the
loop length for the VIN bypass capacitors.
Increasing COUT has a negligible effect on loop stability and
can be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ∆VOUT, is:
Switching current paths through CIN and COUT should be
returned directly to the GND bumps of the IC on the top
layer of the printed circuit board (PCB). VOUT and GND
connections to the system power and ground planes can
be made through multiple vias placed as close as possible
to the COUT capacitors. The regulator should be placed as
close to its load as possible to minimize trace inductance
and capacitance.
1
VOUT I
ESR
(8)
8COUT fSW
where COUT is the effective output capacitance. The
capacitance of COUT decreases at higher output voltages,
which results in higher ∆VOUT. If large values are used for
COUT, the regulator may fail to start under load. If an inductor
value greater than 1.0 H is used, at least 30 F of COUT
should be used to ensure transient response performance.
The lowest ∆VOUT is obtained when the IC is in PWM Mode
and, therefore, operating at 2.4 MHz. In PFM Mode, fSW is
reduced, causing ∆VOUT to increase.
ESL Effects
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the square-
wave component of output ripple that results from the division
ratio COUT ESL and the output inductor (LOUT). The square-
wave component due to the ESL can be estimated as:
ESLCOUT
(9)
VOUT(SQ) VIN
L1
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value. For
example, to obtain COUT=20 F, a single 22 F 0805 would
produce twice the square wave ripple of two 10 F 0805.
Figure 28. Recommended Layout
Connect the VOUT pin and R1 directly to COUT using a low
impedance path (shown in red in Figure 28. Recommended
Layout). A >0.4 mm wide trace is recommended. Avoid
routing this trace directly beneath SW unless separated by
an internal GND plane.
To minimize ESL, try to use capacitors with the lowest ratio
of length to width. 0805 s have lower ESL than 1206 s. If
very low output ripple is necessary, research vendors that
produce 0508 or 0612 capacitors with ultra-low ESL. Placing
additional small value capacitors near the load also reduces
the high-frequency ripple components.
If the MODE function is not required, extend the ground
plane through the MODE pin to reduce the loop inductance
for the VIN bypass.
Input Capacitor
The 10 F ceramic input capacitor should be placed as close
as possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or tantalum)
should be placed between CIN and the power source lead to
reduce under-damped ringing that can occur between the
inductance of the power source leads and CIN.
Thermal Considerations
Heat is removed from the IC through the solder bumps to the
PCB copper. The junction-to-ambient thermal resistance
(JA) is largely a function of the PCB layout (size, copper
weight, and trace width) and the temperature rise from
junction to ambient (T).
The JA is 38°C/W when mounted on its four-layer evaluation
board in still air, with 2 oz. outer layer copper weight and
1 oz. inner layers. Halving the copper thickness results in an
increased JA of 48°C/W.
The effective CIN capacitance value decreases as VIN
increases due to DC bias effects. This has no significant
impact on regulator performance.
To reduce ringing and overshoot on VIN and SW, an
additional bypass capacitor CIN1 is recommended. Because
this lower value capacitor has a higher resonant frequency
than CIN; CIN1 should be placed closer to the VIN and GND
pins of the IC than CIN.
For long term reliable operation, the IC’s junction
temperature (TJ) should be maintained below 125°C.
Maximum IC power loss is 2.88 W. Figure 29 shows required
power dissipation and derating for a FAN53541 mounted on
the Fairchild evaluation board in still air (38°C/W).
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
12
A different approach, shown here as an example, uses the
same equations to determine maximum inductor DCR for a
specific application:
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.88W, max.
Suppose a design requires a 5.0 VIN, 1.2 VOUT, 4 ARMS, at
75°C:
A. From Figure 4, η is ~82%.
B. From Eq. (10), PIC=1,054 mW.
C. From Eq. (13), maximum PD=1,316 mW for 50°C
rise.
D. From Eq. (12), PL=262 mW.
E. From Eq. (11), DCR<16.4 m
Due to the +0.4%/°C temperature coefficient of copper,
inductor DCR must be further reduced to accommodate the
~50°C temperature rise.
0
25
50
75
100
125
Ambient Temperature (C)
To meet the design requirements, an inductor with a room
temperature DCR of <13.6 mΩ is necessary.
Figure 29. Power Derating
Figure 30 shows the maximum ambient temperature where
FAN53541 can be used for a continuous load, at 5.0 VIN:
To calculate maximum operating temperature (<125°C) for a
specific application:
1. Use efficiency graphs to determine efficiency for the
desired VIN, VOUT, and load condition
6
1.2 VOUT
1.8 VOUT
3.3 VOUT
5
2. Calculate IC power dissipation using:
4
1
1
P
VOUT ILOAD
(10)
IC
3
2
1
0
where η is efficiency from Figure 4 through Figure 9.
3. Compute inductor copper losses using:
P ILOAD2 DCRL
(11)
L
4. Combine IC (step 2) and inductor losses (step 3) to
determine total dissipation:
25
50
75
100
125
Ambient Temperature (C)
PD P P
(12)
IC
L
Figure 30. Load Current Derating(6)
5. Determine device operating temperature:
Note:
T P RJA
T TAMB T
IC
and
(13)
D
6. The graph was empirically determined using an ultra-low
DCR (2.6 m) inductor. For physically smaller devices
with higher DCR, further derating may be necessary.
Device temperature (TIC) should not exceed 125°C.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
13
Physical Dimensions
F
BALL A1
E
A
INDEX AREA
1.20
1.20
B
Ø0.215
Cu Pad
Ø0.20
Cu Pad
0.03 C
2X
A1
A1
1.60
D
0.40
Ø0.315 Solder
Mask Opening
Ø0.30 Solder
Mask Opening
0.40
0.40
0.03 C
2X
option 1
option 2
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD TYPE)
0.06 C
0.625
0.547
0.378±0.018
0.208±0.021
E
0.05 C
C
D
SEATING PLANE
SIDE VIEWS
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
0.005
C A B
1.20
Ø0.260±0.02
20X
0.40
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
E
D
C
B
1.60
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
(Y) ±0.018
F
0.40
A
E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
2
3
4
1
(X) ±0.018
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
BOTTOM VIEW
G. DRAWING FILNAME: MKT-UC020AArev3.
Figure 31 20-Ball WLCSP, 4x5 Array, 0.4mm Pitch, 250 µm Ball
Product-Specific Dimensions
Product
D
E
X
Y
FAN53541UCX
1.96 +0.030
1.56 +0.030
0.180
0.180
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/UC/UC020AA.pdf.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
14
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN53541 • Rev. 1.0.2
15
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