FAN53555BUC05X_技术文档

FAN53555

5 A, 2.4 MHz, Digitally

Programmable TinyBuck^®

Regulator

Description

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The FAN53555 is a step−down switching voltage regulator that

delivers a digitally programmable output from an input voltage supply

of 2.5 V to 5.5 V. The output voltage is programmed through an I C

2

interface capable of operating up to 3.4 MHz.

Using a proprietary architecture with synchronous

• 2.5 V to 5.5 V Input Voltage Range

rectification, the FAN53555 is capable of delivering 5 A

continuous at over 80% efficiency, while maintaining over

80% efficiency at load currents as low as 10 mA. Pulse

currents as high as 6.5 A can be supported by the 05 option.

The regulator operates at a nominal fixed frequency of

2.4 MHz, which reduces the value of the external

components to 330 nH for the output induction and as low

as 20 mF for the output capacitor. Additional output

capacitance can be added to improve regulation during load

transients without affecting stability. Inductance up to

1.2 mH may be used with additional output capacitance.

At moderate and light loads, Pulse Frequency Modulation

(PFM) is used to operate in Power−Save Mode with a typical

quiescent current of 60 mA. Even with such a low quiescent

current, the part exhibits excellent transient response during

large load swings. At higher loads, the system automatically

switches to fixed−frequency control, operating at 2.4 MHz.

In Shutdown Mode, the supply current drops below 1 mA,

reducing power consumption. PFM Mode can be disabled if

constant frequency is desired. The FAN53555 is available in

a 20−bump, 1.6 x 2 mm, WLCSP.

• Digitally Programmable Output Voltage:

♦ 00/01/03/05/08/18 Options: 0.6−1.23 V in 10 mV

Steps

♦ 04/042/09/ Options: 0.603−1.411 V in 12.826 mV

Steps

♦ 23, 79 Option: 0.60−1.3875 V in 12.5 mV Steps

♦ 24 Option: 0.603−1.420 V in 12.967 mV Steps

♦ 13 Option: 0.8−1.43 V in 10 mV Steps

• Programmable Slew Rate for Voltage Transitions

2

• I C−Compatible Interface Up to 3.4 Mbps

• PFM Mode for High Efficiency in Light Load

• Quiescent Current in PFM Mode: 60 mA (Typical)

• Internal Soft−Start

• Input Under−Voltage Lockout (UVLO)

• Thermal Shutdown and Overload Protection

• 20−Bump Wafer−Level Chip Scale Package (WLCSP)

Applications

• Application, Graphic, and DSP Processors

ARM®, Krait, OMAP™, NovaThor™, ARMADA

Features

• Hard Disk Drives

• Fixed−Frequency Operation: 2.4 MHz

• Best−in−Class Load Transient

• Continuous Output Current Capability: 5 A

• Pulse Current Capability: 6.5 A (05 Option)

• Tablets, Netbooks, Ultra−Mobile PCs

• Smart Phones

• Gaming Devices

PVIN

C_IN1

C_IN

EN

VOUT

SW

SDA

L1

FAN53555

SCL

VDD

C_OUT

Core

Processor

VSEL

GND

(System Load)

AGND

GND

Figure 1. Typical Application

1

Publication Order Number:

March, 2018 − Rev. 3

FAN53555/D

FAN53555

Table 1. ORDERING INFORMATION

Max. R5C

Max. Pulse

Current

(50 ms)

Power−Up Defaults

2

I C Slave

A1 PIN

Function

Programmable

Output Voltage

MS Cur-

rent

VSEL0

1.05

VSEL1

1.20

Address

Part Number

FAN53555UC00X

FAN53555UC01X

FAN53555UC03X

EN Pin Low

VSEL

5 A

N/A

Registers not

reset

0.90

OFF

N/A

0.6−1.23 V in 10mV

0.90

PGOOD

0.603−1.411 V in

Registers

reset

FAN53555UC04X

FAN53555UC05X

1.10

0.90

1.02

1.20

OFF

1.15

VSEL

5 A

4 A

N/A

6.5 A

N/A

12.826mV

FAN53555BUC05X

(Note 1)

0.6−1.23 V in 10mV

FAN53555UC08X

FAN53555BUC08X

(Note 1)

N/A

FAN53555BUC09X

(Note 1)

1.10

VSEL

3 A

N/A

0.603−1.411 V in

Registers not

reset

12.826mV

C0

FAN53555UC09X

FAN53555UC13X

1.10

1.15

1.10

1.15

VSEL

3 A

5 A

N/A

0.8−1.43 V in 10mV

0.6−1.23 V in 10mV

FAN53555BUC13X

(Note 1)

1.15

1.02

1.15

VSEL

5 A

N/A

FAN53555UC18X

FAN53555BUC18X

(Note 1)

Registers

reset

FAN5355BUC79X

0.85

N/A

PGOOD

5 A

N/A

FAN53555BUC23X

(Note 1)

0.6−1.3875 V in

Registers not

reset

1.15

1.225

1.15

1.212

VSEL

5 A

4 A

N/A

12.5mV

FAN53555UC24X

0.603−1.42 V in

12.967mV

FAN53555BUC24X

(Note 1)

Registers

reset

FAN53555UC042X

(Note 2)

0.603−1.411 V in

1.10

1.20

C4

VSEL

5 A

N/A

12.826mV

1. The FAN53555BUC05X, FAN53555BUC08X, FAN53555BUC09X, FAN53555BUC13X, FAN53555BUC18X, FAN53555BUC23X, and

FAN53555BUC24X, include backside lamination.

2

2. The 042 option is the same as the 04 option, except the I C slave addresses.

3. Temperature Range −40 to 85 °C, Package WLCSP−20, Packing Method Tape & Reel

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2

FAN53555

RECOMMENDED EXTERNAL COMPONENTS

Table 2. RECOMMENDED EXTERNAL COMPONENTS FOR 5 A MAXIMUM LOAD CURRENT

Component

Description

Vendor

Parameter

Typ.

0.33

13

Unit

mH

L

See Table 3

L1

330 nH Nominal

DCR

mW

2 Pieces;

GRM21BR60J226M (Murata)

C2012X5R0J226M (TDK)

C

44

10

20

10

OUT

22 μF, 6.3 V, X5R, 0805

1 Piece;

10 μF, 10 V, X5R, 0805

LMK212BJ106KG−T (Taiyo Yuden)

mF

C2012X5R1A106M (TDK)

C

IN

2 Pieces;

10 μF, 6.3 V, X5R, 0805

GRM21BR60J106M (Murata)

C2012X5R0J106M (TDK)

GRM155R71E103K (Murata)

C1005X7R1E103K (TDK)

C

10 nF, 25 V, X7R, 0402

nF

IN1

Table 3. RECOMMENDED INDUCTORS FOR HIGH−CURRENT APPLICATIONS

Component Dimensions

I

MAXDC

(Note 4)

L

W

H

Manufacturer

Vishay

Part#

L (nH)

470

330

470

330

DCR (mW)

20.0

IHLP1616ABERR47M01

MMD−04ABNR33M−M1−RU

MMD−04ABNR47M−M1−RU

SM1608−R33M

5.0

7.5

5.0

9.0

6.7

5.0

5.4

4.5

4.7

5.0

4.1

4.2

5.0

1.2

2.0

1.2

2.0

Mag. Layers (Note 5)

Mag. Layers

Inter−Technical

Bournes

12.5

20.0

9.6

SRP4012−R33M

330

470

15.0

Bournes

SRP4012−R47M

20.0

TDK

VLC5020T−R47M

15.0

4. I

is the lesser current to produce 40°C temperature rise or 30% inductance roll−off.

MAXDC

5. Preferred inductor value is 330 nH and all dynamic characterization was performed with this coil.

FAN53555−24, −08, and −09 Reduced Output Current (4 A Max. RMS. for 08, and 24, 3 A Max. RMS for

09) Smaller Footprint Application

The FAN53555−24, −08, and −09 were developed to provide power for core processors with high−performance graphics

acceleration in Li−Ion−powered handheld devices. These applications require a very compact solution. The smaller input and

output capacitors in the table below assume that additional bypass capacitance exists across the battery in fairly close proximity

to the regulator(s). The C capacitors specified below are the capacitors that are required in very close proximity to VIN and

IN

PGND (see layout recommendations in Figure 2 below).

Table 4. RECOMMENDED EXTERNAL COMPONENTS FOR LOWER−CURRENT APPLICATIONS WITH

FAN53555−08−09−24

Component

Description

Vendor

Parameter

Typ

Unit

L1

470 or 330 nH, 2016 case size

See Table 5

−08, ,24 Option

44

22

2 Pieces 22 μF, 6.3 V, X5R, 0603

C

C1608X5R0J226M (TDK)

C

OUT

−09 Option

1 Piece 22 μF, 6.3 V, X5R, 0603

mF

1 Piece;

C

GRM155R61A106M (Murata)

C

10

IN

10 μF, 10 V, X5R, 0402

C

10 nF, 25 V, X5R, 0201

TMK063CG100DT−F (Taiyo Yuden)

nF

IN1

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FAN53555

Table 5. RECOMMENDED INDUCTORS FOR LOWER−CURRENT APPLICATIONS WITH FAN53555−08−09−24

Component Dimensions

I

MAXDC

(Note 6)

L

W

H

Manufacturer

Toko

Part#

L (nH)

330

DCR (mW Typ.)

DFE201612R-H−R33N

DFE201612C−R47N

PIFE20161B−R47MS−39

CIGT201610HMR47SCE

25

40

30

3.2

2.0

1.6

1.2

0.9

Toko

470

3.2

Cyntek

470

3.1

SEMCO

470

3.1

6. I

is the lesser current to produce 40°C temperature rise or 30% inductance roll−off.

MAXDC

LAYOUT

Figure 2. Reduced−Footprint Layout

PIN CONFIGURATION

VSEL*

A1

EN

A2

SCL

A3

VOUT

A4

B4

C4

D4

E4

A3

B3

C3

D3

E3

A2

B2

C2

D2

E2

A1

B1

C1

D1

E1

SDA

B1

AGND

B4

B2

C2

D2

E2

B3

C3

D3

E3

GND

C1

D1

E1

C4

D4

E4

VIN

SW

A1 = VSEL for 00, 01, 04, 05, 08, 09, 13, 18, 23, 24

A1 = PGOOD for 03,79

Figure 3. Top View

Table 6. PIN DEFINITIONS

Pin #

Name

Description

VSEL

(Except −03

Option)

Voltage Select. When this pin is LOW, V

set by the VSEL1 register.

is set by the VSEL0 register. When this pin is HIGH, V

is

OUT

A1

PGOOD

(03)

Power Good. This open−drain pin pulls LOW if an overload condition occurs or soft−start is in progress.

Enable. The device is in Shutdown Mode when this pin is LOW. All register values are kept during shut-

down. Options 00, 01, 03, 05, 08 09, 13, 18, and 23 do not reset register values when EN is raised. The 04,

24, 79, and 042 options reset all registers to default values when EN pin is LOW. If pulled up to a low−im-

pedance voltage source greater than 1.8 V, use at least 100 W series resistor.

A2

EN

2

A3

A4

B1

SCL

VOUT

SDA

I C Serial Clock

VOUT. Sense pin for VOUT. Connect to COUT.

2

I C Serial Data

B2, B3,

C1 – C4

GND

Ground. Low−side MOSFET is referenced to this pin. C and C

should be returned with a minimal path

IN

OUT

to these pins.

B4

AGND

Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through this pin.

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4

FAN53555

Table 6. PIN DEFINITIONS

Pin #

Name

Description

D1, D2,

E1, E2

VIN

Power Input Voltage. Connect to the input power source. Connect to C with minimal path.

IN

D3, D4,

E3, E4

SW

Switching Node. Connect to the inductor.

Table 7. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

−0.3

Max

7.0

6.5

2.0

Unit

IC Not Switching

IC Switching

Voltage on SW, VIN Pins

V

)

Tied without Series Resistance

V

IN

Voltage on EN Pin

Tied through Series Resistance of

−0.3

V

(Note 7)

IN

at Least 100 W

Voltage on All Other Pins

IC Not Switching

−0.3

(Note 7)

3.0

V

IN

V

Voltage on VOUT Pin

Maximum Slew Rate of V > 6.5 V, PWM Switching

OUT

V

100

V/ms

INOV_SLEW

IN

Human Body Model per

2000

1500

JESD22−A114

ESD

Electrostatic Discharge Protection Level

V

Charged Device Model per

JESD22−C101

T

Junction Temperature

−40

−65

+150

+260

°C

J

T

Storage Temperature

STG

T

L

Lead Soldering Temperature, 10 Seconds

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

7. Lesser of 7 V or V +0.3 V.

IN

Table 8. RECOMMENDED OPERATING CONDITIONS

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions

are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or

designing to Absolute Maximum Ratings.

Symbol

Parameter

Min

2.5

0

Typ

Max

5.5

5

Unit

V

IN

Supply Voltage Range

Output Current

I

A

OUT

L

Inductor

0.33

10

mH

mF

°C

C

Input Capacitor

IN

C

Output Capacitor

44

OUT

T

A

Operating Ambient Temperature

Operating Junction Temperature

−40

+85

T

J

+125

Table 9. THERMAL PROPERTIES

Symbol

Parameter

Min

Typ

Max

Unit

θ

JA

Junction−to−Ambient Thermal Resistance (Note 8)

38

°C/W

8. See Thermal Considerations in the Application Information section.

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5

FAN53555

Table 10. ELECTRICAL CHARACTERISTICS

Minimum and maximum values are at V = 2.5 V to 5.5 V, T = −40°C to +85°C, unless otherwise noted. Typical values are at T =

IN

A

25°C, V = 5 V, and EN = HIGH.

IN

Symbol

Parameter

Condition

Min

Typ

Max

Unit

POWER SUPPLIES

I

=0

60

43

100

mA

V

LOAD

I

Quiescent Current

Q

=0, MODE Bit=1 (Forced PWM)

LOAD

H/W Shutdown Supply Current

S/W Shutdown Supply Current

Under−Voltage Lockout Threshold

Under−Voltage Lockout Hysteresis

EN=GND

EN= V , BUCK_ENx=0

0.1

41

5.0

75

I

SD

IN

V

Rising

2.35

350

2.45

UVLO

IN

V

mV

UVHYST

EN, VSEL, SDA, SCL

V

high−Level Input Voltage

low−Level Input Voltage

Logic Input Hysteresis Voltage

Input Bias Current

1.1

V

IH

V

IL

LHYST

0.4

V

160

mV

mA

I

IN

Input Tied to GND or VIN

0.01

1.00

PGOOD (03, 79 Option)

I

PGOOD Pull−Down Current

1

mA

OUTL

OUTH

I

PGOOD HIGH Leakage Current

0.01

1.00

mA

V

OUT

REGULATION

V

REG

V

OUT

DC Accuracy

I

=0, Forced PWM, V =VSEL0

OUT

−1.5

−2.0

1.5

4.0

%

OUT(DC)

Default Value

08, 24 Op-

tions

2.5 V ≤ V ≤ 4.5 V, V

IN OUT

from Minimum to Maximum,

=0 to 4 A, Auto

I

OUT(DC)

PFM/PWM

09 Option

2.5 V ≤ V ≤ 4.5 V, V

−2.0

−3.0

4.0

5.0

%

IN

OUT

from Minimum to Maximum,

=0 to 3 A, Auto

I

OUT(DC)

PFM/PWM

13, 18, 23

Options

2.5 V ≤ V ≤ 4.5 V, V

IN

OUT

from Minimum to Maximum,

=0 to 5 A, Auto

I

OUT(DC)

PFM/PWM

All Other

Options

2.5 V ≤ V ≤ 5.5 V, V

IN

OUT

from Minimum to Maximum,

=0 to 5 A, Auto

I

OUT(DC)

PFM/PWM

DV_OUT

DI_LOAD

Load Regulation

I =1 to 5 A

OUT(DC)

−0.1

%/A

Line Regulation

2.5 V ≤ V ≤ 5.5 V, I

=1.5 A

0.01

40

%/V

mV

IN

OUT(DC)

DV_OUT

DV

IN

I

Step 0.1 A to 1.5 A, t =t =100 ns,

r f

LOAD

V

TRSP

Transient Response

V

OUT

=1.2 V

Continued on the following page

Power Switch and Protection

R

P−Channel MOSFET On Resistance

N−Channel MOSFET On Resistance

V

=5 V

28

17

mW

DS(on)P

DS(on)N

IN

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6

FAN53555

Table 10. ELECTRICAL CHARACTERISTICS

Minimum and maximum values are at V = 2.5 V to 5.5 V, T = −40°C to +85°C, unless otherwise noted. Typical values are at T =

IN

A

25°C, V = 5 V, and EN = HIGH.

IN

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Power Switch and Protection

00, 01, 03, 04, 13, 18, 23, 042, 79 Options

6.3

8.5

5.0

4.0

7.4

10.0

5.9

8.5

11.5

6.8

A

05 Option

I

P−MOS Peak Current Limit

LIMPK

08, 24 Options

09 Option

4.75

150

17

5.5

T

LIMIT

Thermal Shutdown

°C

V

T

HYST

Thermal Shutdown Hysteresis

Rising Threshold

Falling Threshold

6.15

5.85

V

SDWN

Input OVP Shutdown

5.50

2.05

V

Frequency Control

f

Oscillator Frequency

2.40

6

2.75

0.5

MHz

SW

DAC

Resolution

Bits

(

)

Differential Nonlinearity 9

LSB

Timing

2

I C

EN=HIGH to I C Start

100

ms

EN

Soft−Start

Regulator Enable to Regulated V

300

135

160

R

> 5 W; to V

=1.2 V;

t_SS

ms

OUT

LOAD

OUT

00, 01, 03, 04, 042, 05, 09, 13, 23 and 79

Options

2.5 V ≤ V ≤ 4.5 V; R

=2 W; to

175

ms

IN

LOAD

V

OUT

=1.127 V with 1.1 V Pre−Bias Volt-

age; 08 and 18 Options

R

VOUT Pull−Down Resistance, Dis-

abled

EN=0 or V <V

W

OFF

IN

UVLO

9. Monotonicity assured by design.

Table 11. I²C TIMING SPECIFICATIONS

Guaranteed by design.

Symbol

Parameter

SCL Clock Frequency

Condition

Min.

Typ.

Max.

100

Unit

f

Standard Mode

Fast Mode

kHz

SCL

400

Fast Mode Plus

1000

3400

1700

High−Speed Mode, C ≤100 pF

B

High−Speed Mode, C ≤ 400 pF

B

t

Bus−Free Time between STOP and

Standard Mode

Fast Mode

4.7

1.3

0.5

4

ms

BUF

START Conditions

Fast Mode Plus

Standard Mode

Fast Mode

t

START or REPEATED START

Hold Time

ms

ns

HD;STA

600

260

160

Fast Mode Plus

High−Speed Mode

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FAN53555

Table 11. I²C TIMING SPECIFICATIONS

Guaranteed by design.

Symbol

Parameter

SCL LOW Period

Condition

Standard Mode

Min.

Typ.

4.7

Max.

Unit

ms

ns

ms

ns

ms

ns

t

LOW

Fast Mode

1.3

Fast Mode Plus

0.5

High−Speed Mode, C ≤ 100 pF

160.0

320.0

4

B

High−Speed Mode, C ≤ 400 pF

B

t

SCL HIGH Period

Standard Mode

Fast Mode

HIGH

600

260

60

Fast Mode Plus

High−Speed Mode, C ≤ 100 pF

B

High−Speed Mode, C ≤ 400 pF

120

4.7

B

t

Repeated START Setup Time

Data Setup Time

Standard Mode

Fast Mode

SU;STA

600.0

260.0

160.0

250

100

50

Fast Mode Plus

High−Speed Mode

Standard Mode

Fast Mode

t

SU;DAT

Fast Mode Plus

High−Speed Mode

Standard Mode

Fast Mode

10

t

Data Hold Time

0

3.45

900.00

450.00

70.00

150.00

1000

300

ms

ns

HD;DAT

Fast Mode Plus

High−Speed Mode, C ≤ 100 pF

B

High−Speed Mode, C ≤ 400 pF

B

t

SCL Rise Time

SCL Fall Time

Standard Mode

Fast Mode

20+0.1C

RCL

B

20+0.1C

B

Fast Mode Plus

20+0.1C

120

B

High−Speed Mode, C ≤ 100 pF

10

80

B

High−Speed Mode, C ≤ 400 pF

20

160

B

t

Standard Mode

Fast Mode

20+0.1C

300

ns

FCL

B

300

Fast Mode Plus

120

B

High−Speed Mode, C ≤ 100 pF

10

40

B

High−Speed Mode, C ≤ 400 pF

20

10

20

80

B

t

Rise Time of SCL After a REPEATED

START Condition and After ACK Bit

High−Speed Mode, C ≤ 100 pF

80

ns

RCL1

B

High−Speed Mode, C ≤ 400 pF

160

B

t

SDA Rise Time

Standard Mode

Fast Mode

20+0.1C

1000

300

RDA

B

Fast Mode Plus

120

B

High−Speed Mode, C ≤ 100 pF

10

80

B

High−Speed Mode, C ≤ 400 pF

20

160

B

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FAN53555

Table 11. I²C TIMING SPECIFICATIONS

Guaranteed by design.

Symbol

Parameter

Condition

Standard Mode

Min.

Typ.

Max.

300

120

80

Unit

t

SDA Fall Time

20+0.1C

ns

FDA

B

Fast Mode

20+0.1C

Fast Mode Plus

B

High−Speed Mode, C ≤ 100 pF

10

B

High−Speed Mode, C ≤ 400 pF

20

4

160

B

t

Stop Condition Setup Time

Standard Mode

Fast Mode

ms

ns

pF

SU;STO

600

120

160

Fast Mode Plus

High−Speed Mode

C

Capacitive Load for SDA and SCL

400

B

TIMING DIAGRAMS

t_F

t_SU;STA

t_BUF

SDA

SCL

t_R

T_SU;DAT

t_HD;STO

t_HIGH

t_LOW

t_HD;STA

t_HD;DAT

t_HD;STA

REPEATED

START

STOP

START

Figure 4. I²C Interface Timing for Fast Plus, Fast, and Slow Modes

REPEATED

START

STOP

t_FDA

t_RDA

t_SU;DAT

SDAH

t_SU;STA

t_RCL1

t_FCL

t_HIGH

t_HD;DAT

note A

t_RCL

t_SU;STO

SCLH

t_LOW

t_HD;STA

REPEATED

START

= MCS Current Source Pull−up

= R_PResistor Pull−up

Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.

Figure 5. I²C Interface Timing for High−Speed Mode

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FAN53555

TYPICAL CHARACTERISTICS

Unless otherwise specified, Auto PFM/PWM, V = 3.6 V, V

= 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, T = 25°C; circuit and

IN

OUT

A

components according to Figure 1 and Table 1.

92%

90%

88%

86%

84%

82%

80%

78%

76%

92%

2.7 VIN

3.6 VIN

90%

5.0 VIN

88%

86%

84%

82%

80%

−40°C

+25°C

+85°C

78%

76%

0

1000

2000

3000

4000

5000

0

1000

2000

3000

4000

5000

LOAD CURRENT (mA)

Figure 6. Efficiency vs. Load Current and

Input Voltage

Figure 7. Efficiency vs. Load Current and

Temperature

90%

88%

86%

84%

82%

80%

78%

76%

74%

72%

70%

90%

88%

86%

84%

82%

80%

78%

76%

74%

72%

70%

−40°C

+25°C

+85°C

2.7 VIN

3.6 VIN

5.0 VIN

0

1000

2000

3000

4000

5000

1000

2000

3000

4000

5000

LOAD CURRENT (mA)

Figure 8. Efficiency vs. Load Current and

Input Voltage, V_OUT= 0.9 V

Figure 9. Efficiency vs. Load Current and

Temperature, V_IN= 5 V, V_OUT= 1.2 V

90%

85%

80%

75%

70%

65%

60%

90%

85%

80%

75%

70%

65%

60%

2.7 VIN

3.6 VIN

5.0 VIN

3.6VIN, 1.2VOUT, L=MMD−04ABNR33M

3.6VIN, 1.2VOUT, L=VLC5020T−R47M

5.0VIN, 1.2VOUT, L=MMD−04ABNR33M

5.0VIN, 1.2VOUT, L=VLC5020T−R47M

5.0VIN, 0.9VOUT, L=MMD−04ABNR33M

5.0VIN, 0.9VOUT, L=VLC5020T−R47M

1000 2000 3000 4000 5000 6000 7000

LOAD CURRENT (mA)

0

1000

2000

3000

4000

5000

LOAD CURRENT (mA)

Figure 10. Efficiency vs. Load Current and

Input Voltage, V_OUT= 0.6 V

Figure 11. Efficiency vs. Load Current, V_IN

3.6 V and 5 V, V_OUT= 1.2 V and 0.9 V

=

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10

FAN53555

TYPICAL CHARACTERISTICS (Continued)

Unless otherwise specified, Auto PFM/PWM, V = 3.6 V, V

= 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, T = 25°C; circuit and

IN

OUT

A

components according to Figure 1 and Table 1.

25

20

15

10

5

20

2.7 VIN

3.6 VIN

5.0 VIN

16

2.7 VIN

3.6 VIN

5.0 VIN

12

8

4

0

1000

2000

3000

4000

5000

0

1000

2000

3000

4000

5000

LOAD CURRENT (mA)

Figure 13. Output Regulation vs. Load Current

and Input Voltage, V_OUT=0.9 V

Figure 12. Output Regulation vs. Load

Current and Input Voltage, V_OUT= 1.2 V

1,000

800

600

400

200

1,000

800

600

400

200

PFM Exit

PFM Enter

PFM Exit

PFM Enter

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

INPUT VOLTAGE (V)

Figure 14. PFM Entry / Exit Level vs. Input

Voltage, V_OUT=1.2 V

Figure 15. PFM Entry / Exit Level vs. Input

Voltage, V_OUT=0.9 V

25

20

15

10

5

3,000

2,500

2,000

1,500

1,000

500

3.6VIN, 1.2VOUT, Auto

3.6VIN, 1.2VOUT, PWM

5.0VIN, 1.2VOUT, Auto

5.0VIN, 1.2VOUT, PWM

5.0VIN, 0.9VOUT, Auto

3.6VIN, 1.2VOUT, Auto

3.6VIN, 0.9VOUT, Auto

5.0VIN, 1.2VOUT, Auto

5.0VIN, 0.9VOUT, Auto

0

1000

2000

3000

4000

5000

0

1000

2000

3000

4000

5000

LOAD CURRENT (mA)

Figure 16. Output Ripple vs. Load Current,

V_IN=5 V and 3.6 V, V_OUT=1.2 V and 0.9 V, Auto

and FPWM

Figure 17. Frequency vs. Load Current,

V_IN=5 V and 3.6 V, V_OUT=1.2 V and 0.9 V, Auto

PWM

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11

FAN53555

TYPICAL CHARACTERISTICS (Continued)

Unless otherwise specified, Auto PFM/PWM, V = 3.6 V, V

= 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, T = 25°C; circuit and

IN

OUT

A

components according to Figure 1 and Table 1.

80

70

60

50

40

30

20

60

50

40

30

20

−40°C

+25°C

+85°C

−40°C

10

+25°C

+85°C

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

INPUT SUPPLY VOLTAGE (V)

INPUT VOLTAGE (V)

Figure 18. Quiescent Current vs. Input Voltage

and Temperature, Auto PWM

Figure 19. Quiescent Current vs. Input Voltage

and Temperature, FPWM

70

60

50

40

30

20

60

50

40

30

20

10

0

EN_BUCK=0, −40C

EN_BUCK=0, +25C

EN_BUCK=0, +85C

EN=0, +25C

3.6VIN, 1.2VOUT, 2A Load

3.6VIN, 0.9VOUT, 2A Load

5.0VIN, 0.9VOUT, 18mA Load, PFM

10

100

1,000

10,000

100k

2.5

3.0

3.5

4.0

4.5

5.0

5.5

INPUT VOLTAGE (V)

FREQUENCY (Hz)

Figure 20. Shutdown Current vs. Input Voltage

and Temperature

Figure 21. PSRR vs. Frequency

Figure 22. Line Transient, 3−4 V_IN, 1.2 V_OUT, 10 ms

Edge, 50 W Load

Figure 23. Line Transient, 3−4 V_IN, 1.2 V_OUT, 10 ms

Edge, 1 A Load

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12

FAN53555

TYPICAL CHARACTERISTICS (Continued)

Unless otherwise specified, Auto PFM/PWM, V = 3.6 V, V

= 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, T = 25°C; circuit and

IN

OUT

A

components according to Figure 1 and Table 1.

Figure 24. Load Transient, 5 V_IN, 0.9 V_OUT, 0.3−3 A,

Figure 25. Load Transient, 3.6 V_IN, 1.2 V_OUT, 0.3−3 A,

100 ns Edge

Figure 26. Load Transient, 3.6 V_IN, 1.2 V_OUT, 0.3−3 A,

100 ns Edge, C_OUT=4x22 mF

Figure 27. Load Transient, 3.6 V_IN, 1.2 V_OUT, 1.5−6 A,

100 ns Edge, C_OUT=4x22 mF

Figure 28. Input Over−Voltage Protection

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13

FAN53555

TYPICAL CHARACTERISTICS (Continued)

Unless otherwise specified, Auto PFM/PWM, V = 3.6 V, V

= 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, T = 25°C; circuit and

IN

OUT

A

components according to Figure 1 and Table 1.

Figure 29. Startup / Shutdown, No Load, V_OUT=0.9 V

Figure 30. Startup / Shutdown, 180 mW Load,

V_OUT=0.9 V

Figure 31. Overload Protection and Recovery

Figure 32. Startup into Faulted Load, V_OUT=0.9 V

OPERATION DESCRIPTION

The FAN53555 is a step−down switching voltage

regulator that delivers a programmable output voltage from

an input voltage supply of 2.5 V to 5.5 V. Using a proprietary

architecture with synchronous rectification, the FAN53555

is capable of delivering 5 A at over 80% efficiency. Pulse

currents as high as 6.5 A can be supported by the 05 option.

The regulator operates at a nominal frequency of 2.4 MHz

at full load, which reduces the value of the external

components to 330 nH for the output inductor and 22 mF for

the output capacitor. High efficiency is maintained at light

load with single−pulse PFM.

The FAN53555 integrates an I C−compatible interface,

allowing transfers up to 3.4 Mbps. This communication

interface can be used to:

• Dynamically re−program the output voltage in 10 mV,

12.826 mV increments (option 04, 09, and 042),

12.5 mV increments (option 23), or 12.967 mV

increments (option 24);

• Reprogram the mode to enable or disable PFM;

• Control voltage transition slew rate; or

• Enable / disable the regulator.

Control Scheme

The FAN53555 uses

a

proprietary non−linear,

fixed−frequency PWM modulator to deliver a fast load

transient response, while maintaining a constant switching

frequency over a wide range of operating conditions. The

regulator performance is independent of the output

capacitor ESR, allowing for the use of ceramic output

capacitors. Although this type of operation normally results

in a switching frequency that varies with input voltage and

load current, an internal frequency loop holds the switching

frequency constant over a large range of input voltages and

load currents.

2

For very light loads, the FAN53555 operates in

Discontinuous Current Diode (DCM) single−pulse PFM,

www.onsemi.com

14

FAN53555

which produces low output ripple compared with other PFM

limits the duty cycle of full output current during soft−start

to prevent excessive heating.

architectures. Transition between PWM and PFM is

relatively seamless, providing a smooth transition between

DCM and CCM Modes.

PFM can be disabled by programming the MODE bit

HIGH in the VSEL registers.

The IC allows for software enable of the regulator, when

EN is HIGH, through the BUCK_EN bits. BUCK_EN0 and

BUCK_EN1 are both initialized HIGH in the 00, 04, 08, 09,

23, 24, 42 and 79 options. These options start after a POR

regardless of the state of the VSEL pin.

Enable and Soft−Start

In the 01 and 05 options, BUCK_EN0 and BUCK_EN1

are initialized to 10. Using these options, VSEL must be

LOW after a POR if the IC is powering the processor used

When the EN pin is LOW; the IC is shut down, all internal

circuits are off, and the part draws very little current. In this

2

state, I C cannot be written to or read from. For all options

2

to communicate through I C. The 03 option has the VSEL

except the 04, 24, and 042 options, all register values are

kept while EN pin is LOW. For the 04, 24 042 and 79

options; registers are reset to default values when EN pin is

LOW. For all options, registers are reset to default values

during a Power On Reset (POR).

When the OUTPUT_DISCHARGE bit in the CONTROL

register is enabled (logic HIGH) and the EN pin is LOW or

the BUCK_ENx bit is LOW, a load is connected from

VOUT to GND to discharge the output capacitors.

Raising EN while the BUCK_ENx bit is HIGH activates

the part and begins the soft−start cycle. During soft−start, the

modulator’s internal reference is ramped slowly to minimize

surge currents on the input and prevent overshoot of the

output voltage. Synchronous rectification is inhibited

during soft−start, allowing the IC to start into a pre−charged

capacitive load.

input to the modulator logic internally tied LOW.

Table 12. HARDWARE AND SOFTWARE ENABLE

Pins

VSEL

BITS

EN

0

BUCK_EN0

BUCK_EN1

Output

OFF

ON

X

0

1

X

0

X

0

1

X

OFF

ON

1

VSEL Pin and I²C Programming Output Voltage

The output voltage is set by the NSELx control bits in

VSEL0 and VSEL1 registers. The output voltage for options

00, 01, 03, 05, 08, 18 and 79 is given as:

If large output capacitance values are used, the regulator

may fail to start. Maximum C

capacitance for

OUT

V

_OUT+ 0.60 V ) NSELx @ 10 mV

(eq. 2)

successfully starting with a heavy constant−current load is

approximately:

For example, when NSEL = 011111 (31 decimal), then

= 0.60 + 0.310 = 0.91 V.

320m

V

OUT

ǒ Ǔ _@

_OUTMAX+ I_LIMPK* I_LOAD

(eq. 1)

C

V_OUT

V

_OUT+ 0.603 ) NSELx @ 12.826 mV

(eq. 3)

where C

is expressed in μF and I

is the load

OUTMAX

LOAD

For the 04, 042, and 09 options; the output voltage is given

as:

current during soft−start, expressed in A.

If the regulator is at its current limit for 16 consecutive

current limit cycles, the regulator shuts down and enters

3−state before reattempting soft−start 1700 ms later. This

For the 13 option, the output voltage is given as:

V

_OUT+ 0.80 ) NSELx @ 10 mV

(eq. 4)

www.onsemi.com

15

FAN53555

2

• Regulator is disabled (EN pin LOW, disabled by I C,

fault time−out, UVLO, OVP, over−temperature);

• Regulator is performing a soft−start.

2

For the 23 option, the output voltage is given as:

V

_OUT+ 0.60 V ) NSELx @ 12.5 mV

(eq. 5)

(eq. 6)

PGOOD remains HIGH during I C initiated V

transitions.

OUT

For the 24 option, the output voltage is given as:

V

_OUT+ 0.603 V ) NSELx 12.967 mV

Current Limiting

Output voltage can also be controlled by toggling the

VSEL pin LOW or HIGH. VSEL LOW corresponds to

VSEL0 and VSEL HIGH corresponds to VSEL1. Upon

POR, VSEL0 and VSEL1 are reset to their default voltages,

shown in Table 9.

A heavy load or short circuit on the output causes the

current in the inductor to increase until a maximum current

threshold is reached in the high−side switch. Upon reaching

this point, the high−side switch turns off, preventing high

currents from causing damage. Sixteen consecutive current

limit cycles in current limit cause the regulator to shut down

and stay off for about 1700 μs before attempting a restart.

Transition Slew Rate Limiting

When transitioning from a low to high voltage, the IC can

be programmed for one of eight possible slew rates using the

SLEW bits in the CONTROL register.

Thermal Shutdown

When the die temperature increases, due to a high load

condition and/or high ambient temperature, the output

switching is disabled until the die temperature falls

sufficiently. The junction temperature at which the thermal

shutdown activates is nominally 150°C with a 17°C

hysteresis.

Table 13. TRANSITION SLEW RATE

Decimal

Bin

000

001

010

011

100

101

110

111

Slew Rate

64.00

0

1

2

3

4

5

6

7

mV / ms

32.00

16.00

8.00

4.00

2.00

1.00

0.50

Monitor Register (Reg05)

The Monitor register indicates of the regulation state of

the IC. If the IC is enabled and is regulating, its value is

(1000 0000).

I²C Interface

The FAN53555’s serial interface is compatible with

2

Standard, Fast, Fast Plus, and HS Mode I C−Bus

specifications. The FAN53555’s SCL line is an input and its

SDA line is a bi−directional open−drain output; it can only

pull down the bus when active. The SDA line only pulls

LOW during data reads and when signaling ACK. All data

is shifted in MSB (bit 7) first.

Transitions from high to low voltage rely on the output

load to discharge V to the new set point. Once the

OUT

high−to−low transition begins, the IC stops switching until

has reached the new set point.

V

OUT

For options 04, 042, 09, 23, and 24 where the Dynamic

I²C Slave Address

Voltage Scaling (DVS) step is not 10 mV; the actual slew

rate is the corresponding number shown in Table 6 scaled by

the ratio of the DVS step to 10 mV. For example, the slew

rate of option 13 for Bin=011 is 8.00 mV / ms X 12.5 mV /

10 mV = 10.00 mV / ms.

In hex notation, the slave address assumes a 0 LS Bit. The

hex slave address is C0 for all options except −42, which has

a hex slave address of C4.

Table 14. I²C SLAVE ADDRESS

Bits

Under−Voltage Lockout

When EN is HIGH, the under−voltage lockout keeps the

part from operating until the input supply voltage rises

HIGH enough to properly operate. This ensures proper

operation of the regulator during startup or shutdown.

7

6

5

4

3

2

1

0

Option

Hex

00 to 24,

79

C0

1

0

R/W

Input Over−Voltage Protection (OVP)

42

C4

1

0

1

0

R/W

When V exceeds V

(about 6.2 V) the IC stops

IN

SDWN

switching to protect the circuitry from internal spikes above

6.5 V. An internal filter prevents the circuit from shutting

down due to noise spikes.

Other slave addresses can be assigned. Contact a ON

Semiconductor representative.

Power Good (03 & 79 Option)

Bus Timing

The PGOOD pin is an open−drain output indicating that

the regulator is enabled when its state is HIGH. PGOOD

pulls LOW under the following conditions:

As shown in , data is normally transferred when SCL is

LOW. Data is clocked in on the rising edge of SCL.

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16

FAN53555

Slave Releases

t_SU;STA

t_HD;STA

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

ACK(0) or

NACK(1)

SLADDR

MS Bit

SDA

SCL

Data change allowed

Figure 36. REPEATED START Timing

SDA

t_H

High−Speed (HS) Mode

t_SU

SCL

The protocols for High−Speed (HS), Low−Speed (LS),

and Fast−Speed (FS) Modes are identical, except the bus

speed for HS mode is 3.4 MHz. HS Mode is entered when

the bus master sends the HS master code 00001XXX after

a START condition. The master code is sent in Fast or

Fast−Plus Mode (less than 1 MHz clock); slaves do not ACK

this transmission.

Figure 33. Data Transfer Timing

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which

is defined as SDA transitioning from 1 to 0 with SCL HIGH,

as shown in .

The master generates a REPEATED START condition ()

that causes all slaves on the bus to switch to HS Mode. The

t_HD;STA

2

Slave Address

master then sends I C packets, as described above, using the

SDA

MS Bit

HS Mode clock rate and timing.

The bus remains in HS Mode until a STOP bit () is sent by

the master. While in HS Mode, packets are separated by

REPEATED START conditions ().

SCL

Figure 34. START Bit

Read and Write Transactions

The following figures outline the sequences for data read

and write. Bus control is signified by the shading of the

packet, defined as Master Drives Bus and Slave Drives Buss.

All addresses and data are MSB first.

A transaction ends with a STOP condition, which is

defined as SDA transitioning from 0 to 1 with SCL HIGH,

as shown in .

Slave Releases

Master Drives

t_HD;STO

Table 15. I²C BIT DEFINITIONS FOR FIGURE 38 AND

FIGURE 39

ACK(0) or

NACK(1)

SDA

SCL

Symbol

Definition

REPEATED START, see Figure 37

R

STOP, see Figure 36

START, see Figure 35

P

S

A

Figure 35. STOP Bit

During a read from the FAN53555, the master issues a

REPEATED START after sending the register address, and

before resending the slave address. The REPEATED

START is a 1 to 0 transition on SDA while SCL is HIGH, as

shown in .

ACK. The slave drives SDA to 0 to acknowledge

the preceding packet.

NACK. The slave sends a 1 to NACK the pre-

ceding packet.

A

Repeated START, see Figure 37.

STOP, see Figure 36.

R

P

0

7 bits

8 bits

Data

S

Slave Address

0

A

Reg Addr

A

P

Figure 37. Write Transaction

0

1

7 bits

Slave Address

8 bits

7 bits

8 bits

Data

S

0

A

Reg Addr

A

R

Slave Address

1

A

P

Figure 38. Read Transaction

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17

FAN53555

REGISTER DESCRIPTION

Table 16. REGISTER MAP

Hex

POR Default

Binary

Address

Option

00

V

OUT

Hex

AD

AA

9E

A7

B0

A3

AC

A7

99

Name

Function

settings when VSEL pin = 0

00

VSEL0

Controls V

10101101

10101010

10011110

10100111

10110000

10100011

10101100

10100111

10011001

11111100

01101000

11101111

10101111

10110111

10100011

10101100

11100111

10000000

1.050

1.020

0.900

1.100

1.225

1.150

1.100

0.85

OUT

08, 18

01, 03, 05

04,

24

13

23

09

79

01

VSEL1

Controls V

settings when VSEL pin = 1

00

FC

68

1.200

1.000

1.200

1.212

1.150

1.100

OUT

01, 05

04,

EF

AF

B7

A3

AC

E7

80

24

08, 18

13

23

09

02

03

CONTROL

Determines whether V

output discharge is en-

00, 01, 03, 04,

05, 24

OUT

abled and also the slew rate of positive transitions

08, 09, 18

00000000

10110000

10000000

10000001

10000011

10000100

10000101

10001000

10001100

0000XXXX

X0000000

00

B0

80

81

83

84

85

88

8C

0X

X0

13, 23

ID1

Read−only register identifies vendor and chip type

00, 13, 23, 24

01

03

04

05

08, 18

09

04

05

ID2

Read−only register identifies die revision

All

MONITOR

Indicates device status

All

Table 17. BIT DEFINITIONS

The following table defines the operation of each register bit. Bold indicates power−on default values.

Bit

Name

Value

Description

VSEL0 R/W

Register Address: 00

7

BUCK_EN0

1

Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is

HIGH, BUCK_EN bit takes precedent.

6

MODE0

0

1

Allow Auto−PFM Mode during light load.

Forced PWM Mode.

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18

FAN53555

Table 17. BIT DEFINITIONS

The following table defines the operation of each register bit. Bold indicates power−on default values.

Bit

Name

Value

Description

VSEL0 R/W

Register Address: 00

5:0

NSEL0

00 Option

101101

Sets V

value from 0.6 to 1.23 V in 10 mV steps (see Eq. (2)).

OUT

08, 18 Options

101010

01, 03, 05 Options

011110

79 Option 011001

04 Option

100111

Sets V

value from 0.603 to 1.411 V in 12.826 mV steps (see Eq. (3)).

OUT

09 Option

100111

13 Option

100011

Sets V

value from 0.8 to 1.43 V in 10 mV steps (see Eq. (4)).

value from 0.6 to 1.3875 V in 12.5 mV steps (see Eq. (5)).

value from 0.603 to 1.42 V in 12.967 mV steps (see Eq. (6)).

OUT

23 Option

101100

24 Option

110000

VSEL1 R/W

Register Address: 01

7

BUCK_EN1

Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is

HIGH, BUCK_EN bit takes precedent.

00, 04, 08, 09,13,

18, 23, 24 Options

1

01, 05 Options

0

6

MODE1

NSEL1

08, 13, 18, 23, 24

Options

Allow AUTO−PFM Mode during light load.

0

00, 01, 04, 05, 09

Options

Forced PWM Mode.

1

5:0

00 Option

111100

Sets V

value from 0.6 to 1.23 V in 10 mV steps (see Eq. (2)).

OUT

01, 05 Options

101000

08, 18 Options

110111

04 Option

101111

Sets V

value from 0.603 to 1.411 V in 12.826 mV steps (see Eq. (3)).

OUT

09 Option

100111

13 Option

100011

Sets V

value from 0.8 to 1.43 V in 10 mV steps (see Eq. (4)).

value from 0.6 to 1.3875 V in 12.5 mV steps (see Eq. (5)).

value from 0.603 to 1.42 V in 12.967 mV steps (see Eq. (6)).

OUT

23 Option

010100

24 Option

101111

CONTROL

R/W

Register Address: 02

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19

FAN53555

Table 17. BIT DEFINITIONS

The following table defines the operation of each register bit. Bold indicates power−on default values.

Bit

Name

Value

Description

CONTROL

R/W

Register Address: 02

7

OUTPUT_DISCHARGE

08, 09, 18, 79

Options

When the regulator is disabled, V

is not discharged.

OUT

0

00, 01, 03, 04,

05,13, 23, 24

Options

discharges through an internal pull−down.

1

6:4

SLEW

000 –111

Sets the slew rate for positive voltage transitions (see Table 6).

Default value for 13 and 23 options

011

0

3

2

Reserved

Always reads back 0

04, 09, 24, 79 Options

RESET

0

Setting to 1 resets all registers to default values.

All other options

Reserved

0

Always reads back 0

Always reads back 00

1:0

ID1

7:5

4

Reserved

00

R

Register Address: 03

VENDOR

Reserved

DIE_ID

100

0

Signifies ON Semiconductor as the IC vendor

Always reads back 0

3:0

0000

0001

0011

0100

0101

1000

IC Type = 00 Option (FAN53555UC00X / FAN53555BUC24X)

IC Type = 01 Option (FAN53555UC01X/ FAN5355BUC79X)

IC Type = 03 Option (FAN53555UC03X)

IC Type = 04 Option (FAN53555UC04X)

IC Type = 042 Option (FAN53555UC042X)

IC Type = 05 Option (FAN53555UC05X / FAN53555BUC05X)

IC Type = 08, 18 Options (FAN53555UC08X / FAN53555BUC08X,

FAN53555UC18X / FAN53555BUC18X)

1100

0000

IC Type = 09 Option (FAN53555UC09X / FAN53555BUC09X)

IC Type = 13 Option (FAN53555UC13X / FAN53555BUC13X)

IC Type = 23 Option (FAN53555BUC23X)

ID2

R

Register Address: 04

7:4

Reserved

0000

Always reads back 0000

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20

FAN53555

Table 17. BIT DEFINITIONS

The following table defines the operation of each register bit. Bold indicates power−on default values.

Bit

ID1

3:0

Name

Value

Description

R

Register Address: 03

DIE_REV

00 Option

0011

IC mask revision

01 Option

0011

03 Option

0011

04 Option

1111

24−Option

0100

042 Option

1111

05 Option

0011

08, 18 Options

0001

BUC08, BUC18

Options

1111

09 Option

1111

13 Option

1111

23 Option

1100

79 Option 1000

Register Address: 05

0

MONITOR

R

PGOOD

Not used

7

1: buck is enabled and soft−start is completed

6:0

000 0000

Always reads back 000 0000

APPLICATION INFORMATION

Selecting the Inductor

(nominal). The inductor should be rated to maintain at least

80% of its value at I . Failure to do so lowers the

amount of DC current the IC can deliver.

Efficiency is affected by the inductor DCR and inductance

value. Decreasing the inductor value for a given physical

size typically decreases the DCR; but since DI increases, the

RMS current increases, as do core and skin−effect losses.

The output inductor must meet both the required

inductance and the energy−handling capability of the

application. The inductor value affects the average current

limit, the output voltage ripple, and the efficiency.

The ripple current (DI) of the regulator is:

LIM(PK)

V_OUT

V_IN

V_IN* V_OUT

_@ǒ Ǔ

DI +

(eq. 7)

DI²

L @ f_sw

2

₊Ǹ

I_RMS

I_OUT(DC)

)

(eq. 9)

12

The maximum average load current, I

is

MAX(LOAD),

The increased RMS current produces higher losses

related to the peak current limit, I

current such that:

, by the ripple

LIM(PK)

through the R

inductor ESR.

of the IC MOSFETs as well as the

DS(ON)

DI

I

_MAX(LOAD)+ I_LIM(PK)

*

Increasing the inductor value produces lower RMS

currents, but degrades transient response. For a given

(eq. 8)

2

The FAN53555 is optimized for operation with

L=330 nH, but is stable with inductances up to 1.0 μH

www.onsemi.com

21

FAN53555

physical inductor size, increased inductance usually results

in an inductor with lower saturation current.

A good practice to minimize this ripple is to use multiple

output capacitors to achieve the desired C value. For

OUT

example, to obtain C =20 μF, a single 22 μF 0805 would

OUT

produce twice the square wave ripple as two x 10 μF 0805.

To minimize ESL, try to use capacitors with the lowest

ratio of length to width. 0805s have lower ESL than 1206s.

If low output ripple is a chief concern, some vendors

produce 0508 or 0612 capacitors with ultra−low ESL.

Placing additional small−value capacitors near the load also

reduces the high−frequency ripple components.

Table 18. EFFECTS OF INDUCTOR VALUE (FROM

330 nH RECOMMENDED) ON REGULATOR

PERFORMANCE

(Eq.(11))

I

DV

Transient Response

MAX(LOAD)

OUT

Increase

Decrease

Degraded

Inductor Current Rating

The current limit circuit can allow substantial peak

currents to flow through L1 under worst−case conditions. If

it is possible for the load to draw such currents, the inductor

should be capable of sustaining the current or failing in a safe

manner.

Input Capacitor

The ceramic input capacitors should be placed as close as

possible between the VIN pin and PGND to minimize the

parasitic inductance. If a long wire is used to bring power to

the IC, additional “bulk” capacitance (electrolytic or

tantalum) should be placed between C and the power

source lead to reduce under−damped ringing that can occur

For space−constrained applications, a lower current rating

for L1 can be used. The FAN53555 may still protect these

inductors in the event of a short circuit, but may not be able

to protect the inductor from failure if the load is able to draw

higher currents than the DC rating of the inductor.

IN

between the inductance of the power source leads and C .

IN

The effective C capacitance value decreases as V

IN

increases due to DC bias effects. This has no significant

impact on regulator performance.

Output Capacitor and V_OUTRipple

Table 1suggests 0805 capacitors, but 0603 capacitors may

be used if space is at a premium. Due to voltage effects, the

0603 capacitors have a lower in−circuit capacitance than the

0805 package, which can degrade transient response and

output ripple.

Thermal Considerations

Heat is removed from the IC through the solder bumps to

the PCB copper. The junction−to−ambient thermal

resistance ( ) is largely a function of the PCB layout (size,

JA

copper weight, and trace width) and the temperature rise

from junction to ambient (ΔT).

Increasing C

has negligible effect on loop stability

OUT

For the FAN53555UC, θ is 38°C/W when mounted on

and can be increased to reduce output voltage ripple or to

improve transient response. Output voltage ripple, DV

is calculated by:

JA

its four−layer evaluation board in still air with two−ounce

outer layer copper weight and one−ounce inner layers.

,

OUT

Halving the copper thickness results in an increased θ of

(eq. 10)

JA

48°C/W.

f

_SW@ C_OUT@ ESR ²

1

DV_OUT+ DI_L

ƪ

)

ƫ

For long−term reliable operation, the IC’s junction

(

)

2 @ D @ 1 * D

8 @ f_SW@ C_OUT

temperature (T ) should be maintained below 125°C.

J

To calculate maximum operating temperature (<125°C)

where C

is the effective output capacitance.

The capacitance of C

voltages, which results in higher DV

OUT

for a specific application:

decreases at higher output

OUT

1. Use efficiency graphs to determine efficiency for

. Equation (10) is

only valid for Continuous Current Mode (CCM) operation,

which occurs when the regulator is in PWM Mode.

OUT

the desired V , V

, and load conditions.

OUT

IN

2. Calculate total power dissipation using:

ǒ¹_* 1Ǔ

For large C

values, the regulator may fail to start under

OUT

(eq. 12)

P

_T+ V_OUT I_LOAD

h

a load. If an inductor value greater than 1.0 μH is used, at

least 30 μF of C

The lowest DV

should be used to ensure stability.

is obtained when the IC is in PWM

where h is efficiency from Figure 7 through Figure

OUT

12.

OUT

Mode and, therefore, operating at 2.4 MHz. In PFM Mode,

is reduced, causing DV to increase.

3. Estimate inductor copper losses using:

f

2

SW

OUT

(eq. 13)

P_L+ I_LOAD DCR_L

ESL Effects

4. Determine IC losses by removing inductor losses

(step 3) from total dissipation:

The Equivalent Series Inductance (ESL) of the output

capacitor network should be kept low to minimize the

square−wave component of output ripple that results from

the division ratio C

The square−wave component due to the ESL can be

(eq. 14)

(eq. 15)

(eq. 16)

P

_IC+ P_T* P_L

5. Determine device operating temperature:

ESL and the output inductor (L

).

OUT

DT + P_IC q_szie7JA

estimated as:

and

ESL_COUT

(eq. 11)

@

IN

T

_IC+ T_A) DT

DV

[ V

OUT(SQ)

L1

www.onsemi.com

22

FAN53555

It is important to note that the R

MOSFETs increases linearly with temperature at about

of the IC’s power

1.21%/°C. This causes the efficiency (h) to degrade with

increasing die temperature.

DS(ON)

LAYOUT RECOMMENDATION

Figure 39. Guidance for Layer 1

Figure 40. Guidance for Layer 2

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23

FAN53555

Figure 41. Guidance for Layer 3

1. FB trace connects to “+” side of COUT cap.

3. Do not place COUT near FAN53555, place cap near load

Length should be less than 0.5 inches

2. Max trace resistance between FAN53555 and CPU should not exceed 30m

Ω

Width (mils)

Length (mils)

Copper (Oz)

Resistance (mW)

25

500

2

1.5

1

4.2

4.9

5.8

7.6

Table provides resistance values

for given Copper Oz

.

0.5

Figure 42. Remote Sensing Schematic

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24

FAN53555

Figure 43. Remote Sensing Guidance, Top Layer

Table 19. Product−Specific Dimensions

Product

D

E

X

Y

Land Pattern

Option 1

FAN53555UC00 to FAN53555UC08X, FAN53555BUC05X

2.000 0.03

2.015 0.03

1.600 0.03

1.615 0.03

0.200

FAN53555BUC08X, FAN53555BUC09X, FAN53555UC09X,

FAN53555UC13X, FAN53555BUC13X, FAN53555UC18X,

FAN53555BUC18X, FAN53555BUC23X, FAN53555UC24X,

FAN53555BUC24X, FAN53555BUC79X

0.2075 0.2075

Option 2

OMAP is a trademark of Texas Instruments Incorporated. NOVATHOR is a trademark of ST−Ericsson SA. Arm is a registered trademark of Arm Limited (or

its subsidiaries) in the US and/or elsewhere.

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25

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP20 2.015x1.615x0.586

CASE 567QK

ISSUE O

DATE 31 OCT 2016

98AON13330G

ON SEMICONDUCTOR STANDARD

DOCUMENT NUMBER:

STATUS:

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

NEW STANDARD:

Case Outline Number:

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October, 2002 − Rev. 0

DESCRIPTION: WLCSP20 2.015x1.615x0.586

PAGE 1 OFX2XX

1

DOCUMENT NUMBER:

98AON13330G

PAGE 2 OF 2

ISSUE

REVISION

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RELEASED FOR PRODUCTION FROM FAIRCHILD UC020AA TO ON SEMICON-

DUCTOR. REQ. BY F. ESTRADA.

31 OCT 2016

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

Case Outline Number:

October, 2016 − Rev. O

567QK

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP20 2.015x1.615x0.586

CASE 567SH

ISSUE O

DATE 30 NOV 2016

98AON16602G

ON SEMICONDUCTOR STANDARD

DOCUMENT NUMBER:

STATUS:

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

NEW STANDARD:

Case Outline Number:

http://onsemi.com

October, 2002 − Rev. 0

DESCRIPTION: WLCSP20 2.015x1.615x0.586

PAGE 1 OFX2XX

1

DOCUMENT NUMBER:

98AON16602G

PAGE 2 OF 2

ISSUE

REVISION

DATE

O

RELEASED FOR PRODUCTION FROM FAIRCHILD UC020AA TO ON SEMICON-

DUCTOR. REQ. BY F. ESTRADA.

30 NOV 2016