FAN5354MPX [FAIRCHILD]
3MHz, 3A Synchronous Buck Regulator; 3MHz的，3A同步降压稳压器
| 型号： | FAN5354MPX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 3MHz, 3A Synchronous Buck Regulator |
| 文件： | 总14页 (文件大小：779K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2010
FAN5354
3MHz, 3A Synchronous Buck Regulator
Description
Features
The FAN5354 is a step-down switching voltage regulator that
delivers an adjustable output from an input voltage supply of
3MHz Fixed-Frequency Operation
Best-in-Class Load Transient
2.7V to 5.5V. Using
a proprietary architecture with
synchronous rectification, the FAN5354 is capable of
delivering 3A at over 85% efficiency, while maintaining a
very high efficiency of over 80% at load currents as low as
2mA. The regulator operates at a nominal fixed frequency of
3MHz, which reduces the value of the external components
to 470nH for the output inductor and 10µF for the output
capacitor. Additional output capacitance can be added to
improve regulation during load transients without affecting
stability and inductance up to 1.2µH may be used with
additional output capacitance.
3A Output Current Capability
2.7V to 5.5V Input Voltage Range
Adjustable Output Voltage: 0.8 to VIN•0.9
PFM Mode for High Efficiency in Light Load (Forced PWM
Available on MODE Pin)
Minimum PFM Frequency Avoids Audible Noise
270µA Typical Quiescent Current in PFM Mode
External Frequency Synchronization
At moderate and light loads, pulse frequency modulation
(PFM) is used to operate the device in power-save mode
with a typical quiescent current of 270µA. Even with such a
low quiescent current, the part exhibits excellent transient
response during large load swings. At higher loads, the
system automatically switches to fixed-frequency control,
operating at 3MHz. In shutdown mode, the supply current
drops below 1µA, reducing power consumption. PFM mode
can be disabled if constant frequency is desired. To avoid
audible noise, the regulator limits its minimum PFM
frequency. The FAN5354 is available in 12-lead 3x3.5mm
MLP package.
Low Ripple Light-Load PFM Mode with Forced
PWM Control
Power Good Output
Internal Soft-Start
Input Under-Voltage Lockout (UVLO)
Thermal Shutdown and Overload Protection
12-Lead 3x3.5mm MLP
Applications
Set-Top Box
Hard Disk Drive
Communications Cards
DSP Power
Figure 1. Typical Application
Ordering Information
Part Number
Temperature Range
Package
Packing Method
FAN5354MPX
-40 to 85°C
MLP-12, 3x3.5mm
Tape and Reel
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
Table 1. Recommended External Components for 3A Maximum Load Current
Component
Description
Vendor
Parameter
Typ.
Units
IHLP1616ABER47M01 (Vishay)
SD12-R47-R (Coiltronics)
VLC5020T-R47N (TDK)
(TDK)
L
0.47
μH
L1
470nH Nominal
DCR
20
mΩ
LQH55PNR47NT0 (Murata)
2 Pieces
10μF, 6.3V, X5R, 0805
COUT
CIN
GRM21BR60J106M (Murata)
C2012X5R0J106M (TDK)
C
C
10.0
10
μF
10μF, 6.3V, X5R, 0805
GRM155R71E103K (Murata)
C1005X7R1E103K (TDK)
CIN1
10nF, 25V, X7R, 0402
nF
GRM188R60J475K (Murata)
C1608X5R0J475K (TDK)
CVCC
C
R
4.7
1
4.7μF, 6.3V, X5R, 0603
Resistor: 1Ω 0402
μF
R3(1)
Any
Ω
Note:
1. R3 is optional and improves IC power supply noise rejection. See Layout recommendations for more information.
Pin Configuration
FB
VOUT
PGND
PGND
SW
1
2
3
4
5
6
12 MODE
11 PGOOD
10 EN
P1
(GND)
9
8
7
VCC
PVIN
PVIN
SW
Figure 2. 12-Pin, 3x3.5mm MLP (Top View)
Pin Definitions
Pin # Name
Description
FB. Connect to resistor divider. The IC regulates this pin to 0.8V.
1
2
FB
VOUT. Sense pin for VOUT. Connect to COUT.
VOUT
Power Ground. Low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a
minimal path to these pins.
3, 4
PGND
Switching Node. Connect to inductor.
5, 6
P1
SW
Ground. All signals are referenced to this pin.
GND
PVIN
Power Input Voltage. Connect to input power source. Connect to CIN with minimal path.
7, 8
IC Bias Supply. Connect to input power source. Use a separate bypass capacitor CVCC from this pin
to the P1 GND terminal between pins 1 and 12.
9
VCC
Enable. The device is in shutdown mode when this pin is LOW. Do not leave this pin floating.
Power Good. This open-drain pin pulls LOW if the output falls out of regulation or is in soft-start.
10
11
EN
PGOOD
MODE / Sync. A logic 0 allows the IC to automatically switch to PFM during light loads. When held
HIGH, the IC to stays in PWM mode. The regulator also synchronizes its switching frequency to the
frequency provided on this pin. Do not leave this pin floating.
12
MODE
Note:
2. P1 is the bottom heat-sink pad. Ground plane should flow through pins 3, 4, and P1 and can be extended through pin 11 if
PGOOD’s function is not required, and through pin 12 if MODE is to be grounded, to improve IC cooling.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum
ratings are stress ratings only.
Symbol Parameter
SW, PVIN, VCC Pins
Other Pins
Min.
-0.3
-0.3
-0.3
Max.
7.0
Units
IC Not Switching
IC Switching
V
VIN
6.5
VCC + 0.3(3)
V
VINOV_SLEW Maximum Slew Rate of VIN Above 6.5V when PWM is Switching
RPGOOD Pull-Up Resistance from PGOOD to VCC
15
V/ms
KΩ
1
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
2
Electrostatic Discharge
Protection Level
ESD
KV
2
TJ
TSTG
TL
Junction Temperature
Storage Temperature
–40
–65
+150
+150
+260
°C
°C
°C
Lead Soldering Temperature, 10 Seconds
Note:
3. Lesser of 7V or VCC+0.3V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter
Min.
2.7
0.8
0
Typ.
Max.
Units
V
VCC, VIN
VOUT
IOUT
L
Supply Voltage Range
5.5
Output Voltage Range
Output Current
90% Duty Cycle
3
V
A
Inductor
0.47
10
µH
µF
µF
°C
°C
CIN
Input Capacitor
COUT
TA
Output Capacitor
20
Operating Ambient Temperature
Operating Junction Temperature
-40
-40
+85
TJ
+125
Thermal Properties
Symbol Parameter
Min.
Typ.
Max.
Units
Junction-to-Ambient Thermal Resistance(4)
46
°C/W
θJA
Note:
4. Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer
1s2p boards in accordance to JESD51- JEDEC standard. Special attention must be paid not to exceed junction
temperature TJ(max) at a given ambient temperate TA.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
3
Electrical Characteristics
Minimum and maximum values are at VIN=2.7V to 5.5V, TA=-40°C to +85°C, unless otherwise noted. Typical values are at
TA=25°C, VIN=5V.
Symbol Parameter
Power Supplies
Conditions
Min. Typ. Max. Units
I
LOAD=0, MODE=0
270
14
μA
mA
μA
V
IQ
Quiescent Current
Shutdown Supply Current
ILOAD=0, MODE=1 (Forced PWM)
EN=GND
I SD
0.1
3.0
V
IN Rising
2.83 2.95
2.10 2.30 2.40
530
VUVLO Under-Voltage Lockout Threshold
VIN Falling
V
VUVHYST Under-Voltage Lockout Hysteresis
mV
Logic Pins
VIH
VIL
HIGH-Level Input Voltage
LOW-Level Input Voltage
1.05
V
V
0.4
100
VLHYST Logic Input Hysteresis Voltage
mV
μA
mA
μA
IIN
Input Bias Current
Input Tied to GND or VIN
VPGOOD=0.4V
0.01 1.00
1
IOUTL
IOUTH
PGOOD Pull-Down Current
PGOOD HIGH Leakage Current
VPGOOD=VIN
0.01 1.00
VOUT Regulation
TA=25°C
0.792 0.800 0.808
0.788 0.800 0.812
V
V
Output Reference DC Accuracy
VREF
VREG
Measured at FB Pin
VOUT DC Accuracy
At VOUT Pin W.R.T. Calculated Value,
ILOAD=500mA
1.6
+1.6
%
ΔVOUT
ΔILOAD
Load Regulation
I
OUT(DC)=1 to 3A
–0.03
%/A
ΔVOUT
Line Regulation
2.7V ≤ VIN ≤ 5.5V, IOUT(DC)=1.5A
0.01
+40
%/V
mV
ΔV
IN
Transient Response
ILOAD Step 0.1A to 1.5A, tr=tf=100ns, VOUT=1.2V
Power Switch and Protection
RDS(ON)P P-Channel MOSFET On Resistance
RDS(ON)N N-Channel MOSFET On Resistance
60
40
mΩ
mΩ
A
ILIMPK
TLIMIT
P-MOS Peak Current Limit
Thermal Shutdown
3.75 4.55 5.50
150
20
°C
°C
V
THYST Thermal Shutdown Hysteresis
VSDWN Input OVP Shutdown
Frequency Control
Rising Threshold
Falling Threshold
6.2
5.50 5.85
V
fSW
Oscillator Frequency
2.7
External Square-Wave, 30% to 70% Duty Cycle 2.7
3.0
3.0
26
3.3
3.3
36
MHz
MHz
kHz
fSYNC
MODE Pin Synchronization Range
fPFM(MIN) Minimum PFM Frequency
TA = 25°C, VIN = 5.0V
17
Soft-Start
210 250
340 420
10
RLOAD > 5Ω, to VOUT=1.2V
RLOAD > 5Ω, to VOUT=1.8V
μs
μs
tSS
Regulator Enable to Regulated VOUT
VSLEW Soft-Start VREF Slew Rate
V/ms
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
4
Typical Characteristics
Unless otherwise specified, VIN=5V, VOUT=1.2V, circuit of Figure 1, and components per Table 1.
100%
90%
80%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
70%
60%
50%
40%
30%
20%
10%
0%
VIN = 3.3V, Mode = 0
VIN = 3.3V, Mode = 1
VIN = 5V, Mode = 0
VIN = 5V, Mode = 1
VIN = 3.3V, Mode=0
VIN = 3.3V, Mode=1
VIN = 5V, Mode=0
VIN = 5V, Mode=1
1
10
100
1000
10000
1
10
100
1000
10000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 3. Efficiency vs. ILOAD at VOUT=1.2V
Figure 4. Efficiency vs. ILOAD at VOUT=1.8V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
VIN = 3.3V, Mode = 0
VIN = 3.3V, Mode = 1
VIN = 5V, Mode = 0
VIN = 5V, Mode = 1
VIN = 4.2V, Mode = 0
VIN = 4.2V, Mode = 1
VIN = 5V, Mode = 0
VIN = 5V, Mode = 1
1
10
100
1000
10000
1
10
100
1000
10000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 5. Efficiency vs. ILOAD at VOUT=2.5V
Figure 6. Efficiency vs. ILOAD at VOUT=3.3V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
375
350
325
300
275
250
225
200
VOUT = 3.3
85°C
VOUT = 1.2
25°C
‐40°C
85°C
25°C
–40°C
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
Input Voltage(V)
Input Voltage(V)
Figure 7. Shutdown Supply Current vs VIN, EN=0
Figure 8. Quiescent Current in PFM vs. VIN, No Load
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
5
Typical Characteristics
Unless otherwise specified, VIN=5V, VOUT=1.2V, circuit of Figure 1, and components per Table 1.
3.5
1000
1.2VOUT boundary
900
3.0
1.2VOUT boundary
Always PWM
800
700
600
500
400
300
200
100
0
3.3VOUT boundary
3.3VOUT boundary
2.5
2.0
1.5
1.0
0.5
-
Hysteresis
VIN = 4.1V
VIN = 4.0V
VIN = 3.9V
VIN = 3.8V
Always PFM
4.7
0
0.5
1
1.5
Load Current (A)
2
2.5
3
2.7
3.2
3.7
4.2
5.2
Input Voltage(V)
Figure 9. PFM/PWM Mode-Change Boundaries
Figure 10. Effect of tOFF Minimum on Reducing Switching
Frequency at Large Duty Cycles, VOUT=3.3V
PFM
PWM
16
14
12
10
8
90
80
70
60
50
6
1.2VOUT,1.5A load
5VIN, 1.2VOUT
40
30
20
3.3VOUT, 0.5A load in PFM
3.3VOUT, 1.5A load
4
3.3VIN, 1.2VOUT
5VIN,3.3VOUT
2
0
0.01
0.1
1
10
100
0.1
1
10
100
1000
10000
Load Current(mA)
Frequency (KHz)
Figure 11. Output Voltage Ripple vs. Load Current
Figure 12. Power Supply Rejection Ratio (PSRR)
(See explanation on page 12)
VOUT
IL
Figure 13. PFM-to-PWM Mode Transition, Slowly
Increasing Load Current, 2µs/div.
Figure 14 PWM-to-PFM Mode Transition, Slowly
Decreasing Load Current, 2µs/div.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
6
Typical Characteristics
Unless otherwise specified, VIN=5V, VOUT=1.2V, circuit of Figure 1, and components per Table 1.
31.0
30.0
TJ = 85°C
29.0
28.0
27.0
26.0
25.0
24.0
TJ = 25°C
TJ = –40°C
2.5
3
3.5
4
4.5
5
5.5
6
Input Voltage (V)
Figure 15. PFM frequency, ILOAD = 0
Load Transient Response (Figure 16 – Figure 19). ILOAD tR = tF = 100ns
Figure 16. MODE=0, 100mA to 1.5A to 100mA, 5µs/div.
Figure 17. 500mA to 3A to 500mA, 5µs/div.
VOUT
IL
Iload
Figure 18. MODE=1, 100mA to 1.5A to 100mA, 5µs/div.
Figure 19. 24mA to 500mA to 24mA, MODE=0, 5µs/div.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
7
Typical Characteristics
Unless otherwise specified, VIN=5V, VOUT=1.2V, circuit of Figure 1, and components per Table 1.
VEN
VIN=VEN
VOUT
VOUT
VPG
VPG
Isupply
Isupply
Figure 20. Soft-Start, EN Voltage Raised After VIN=5V,
Figure 21. Soft-Start, EN Pin Tied to VCC
ILOAD=0, 1ms/div.
ILOAD=0, 100μs/div.
Figure 22. Soft-Start, EN Pin Raised After VIN=5V
Figure 23. Soft-Start, EN Pin Tied to VCC
RLOAD=400mΩ, COUT=100μF, 100μs/div.
RLOAD=400mΩ, COUT=100μF, 1ms/div.
Figure 24. Line Transient Response in PWM Mode,
Figure 25. Line Transient Response in PFM Mode,
10μs/div.
10μs/div.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
8
Typical Characteristics
Unless otherwise specified, VIN=5V, VOUT=1.2V, circuit of Figure 1, and components per Table 1.
Circuit Protection Response
VOUT
VOUT
IL
IL
VPG
VPG
Figure 26. VOUT to GND Short Circuit, 200μs/div.
Figure 27. VOUT to GND Short Circuit, 5μs/div.
VEN
VOUT
VOUT
IL
IL
VPG
VPG
Figure 28. Over-Current at Startup, RLOAD=200mΩ,
50μs/div.
Figure 29. Progressive Overload, 200μs/div.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
9
Operation Description
The FAN5354 is a step-down switching voltage regulator that
delivers an adjustable output from an input voltage supply of
regulator shuts down before restarting 1200μs later. This
limits the COUT capacitance when a heavy load is applied
during the startup. For a typical FAN5354 starting with a
resistive load:
2.7V to 5.5V. Using
a proprietary architecture with
synchronous rectification, the FAN5354 is capable of
delivering 3A at over 80% efficiency. The regulator operates
at a nominal frequency of 3MHz at full load, which reduces
the value of the external components to 470nH for the output
inductor and 20µF for the output capacitor. High efficiency is
maintained at light load with single-pulse PFM mode.
COUTMAX(μF)≈ 400−100•ILOAD(A)
VOUT
(3)
ILOAD
=
where
RLOAD
Control Scheme
Synchronous rectification is inhibited during soft-start,
allowing the IC to start into a pre-charged load.
The FAN5354 uses a proprietary non-linear, fixed-frequency
PWM modulator to deliver a fast load transient response,
while maintaining a constant switching frequency over a wide
range of operating conditions. The regulator performance is
independent of the output capacitor ESR, allowing for the
use of ceramic output capacitors. Although this type of
operation normally results in a switching frequency that
varies with input voltage and load current, an internal
frequency loop holds the switching frequency constant over
a large range of input voltages and load currents.
MODE Pin – External Frequency
Synchronization
Logic 1 on this pin forces the IC to stay in PWM mode. A
logic 0 allows the IC to automatically switch to PFM during
light loads. If the MODE pin is toggled, the converter
synchronizes its switching frequency to four times the
frequency on the mode pin (fMODE).
The MODE pin is internally buffered with a Schmitt trigger,
which allows the MODE pin to be driven with slow rise and
fall times. An asymmetric duty cycle for frequency
synchronization is permitted as long as the minimum time
below VIL(MAX) or above VIH(MAX) is 100ns.
For very light loads, the FAN5354 operates in discontinuous
current (DCM) single-pulse PFM mode, which produces low
output ripple compared with other PFM architectures.
Transition between PWM and PFM is seamless, with a glitch
of less than 18mV at VOUT during the transition between
DCM and CCM modes. The regulator limits minimum PFM
frequency to typically26Khz.
PGOOD Pin
The PGOOD pin is an open-drain that pin indicates that the
IC is in regulation when its state is open. PGOOD pulls LOW
under the following conditions:
PFM mode can be disabled by holding the MODE pin HIGH.
In addition, the IC synchronizes to the MODE pin frequency.
When synchronizing to the MODE pin, PFM mode is
disabled.
1. The IC has operated in cycle-by-cycle current limit for
eight or more consecutive PWM cycles.
Setting the output voltage
The output voltage is set by the R1, R2, and VREF (0.8V):
2. The circuit is disabled, either after a fault occurs, or
when EN is LOW.
3. The IC is performing a soft-start.
VOUT − VREF
R1
R2
=
(1)
Under-Voltage Lockout
VREF
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage rises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdown.
R1 must be set at or below 100KΩ; therefore:
R1• 0.8
R2 =
(2)
(
VOUT − 0.8
)
Input Over-Voltage Protection (OVP)
For example, for VOUT=1.2V, R1=100KΩ, R2=200KΩ.
When VIN exceeds VSDWN (about 6.2V) the IC stops switching
to protect the circuitry from internal spikes above 6.5V. An
internal 40μs filter prevents the circuit from shutting down
due to noise spikes. For the circuit to fully protect the internal
circuitry, the VIN slew rate above 6.2V must be limited to no
more than 15V/ms when the IC is switching.
Enable and Soft Start
When the EN pin is LOW, the IC is shut down, all internal
circuits are off, and the part draws very little current. Raising
EN above its threshold voltage activates the part and starts
the soft-start cycle. During soft-start, the modulator’s internal
reference is ramped slowly to minimize any large surge
currents on the input and prevents any overshoot of the
output voltage.
The IC protects itself if VIN overshoots to 7V during initial
power-up as long as the VIN transition from 0 to 7V occurs in
less than 10μs (10% to 90%).
If large values of output capacitance are used, the regulator
may fail to start. If VOUT fails to achieve regulation within
320μs from the beginning of soft-start, the regulator shuts
down and waits 1200μs before attempting a restart. If the
regulator is at its current limit for more than about 60μs, the
Current Limiting
A heavy load or short circuit on the output causes the current
in the inductor to increase until a maximum current threshold
is reached in the high-side switch. Upon reaching this point,
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
10
the high-side switch turns off, preventing high currents from
causing damage. 16 consecutive PWM cycles in current limit
cause the regulator to shut down and stay off for about
1200μs before attempting a restart.
at ILIM(PK). Failure to do so lowers the amount of DC current
the IC can deliver.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since ∆I increases, the
RMS current increases, as do core and skin-effect losses.
In the event of a short circuit, the soft-start circuit attempts to
restart and produces an over-current fault after about 50μs,
which results in a duty cycle of less than 10%, providing
current into a short circuit.
ΔI2
12
2
(7)
IRMS
=
IOUT(DC)
+
Thermal Shutdown
The increased RMS current produces higher losses through
the RDS(ON) of the IC MOSFETs as well as the inductor ESR.
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the output
switching is disabled until the temperature on the die has
fallen sufficiently. The junction temperature at which the
thermal shutdown activates is nominally 150°C with a 20°C
hysteresis.
Increasing the inductor value produces lower
RMS currents, but degrades transient response.
For a given physical inductor size, increased
inductance usually results in an inductor with
lower saturation current.
Table 2 shows the effects of inductance higher or lower than
the recommended 470nH on regulator performance.
Minimum Off-Time Effect on Switching
Frequency
tON(MIN) and tOFF(MIN) are both 45ns. This imposes constraints
VOUT
on the maximum
that the FAN5354 can provide,
Table 2. Effects of Increasing the Inductor
Value (from 470nH Recommended) on
Regulator Performance
VIN
while still maintaining a fixed switching frequency in PWM
mode. While regulation is unaffected, the switching
frequency will drop when the regulator cannot provide
sufficient duty cycle at 3 MHz to maintain regulation.
Transient
Response
IMAX(LOAD)
∆VOUT (EQ. 8)
The calculation for switching frequency is given below
Increase
Decrease
Degraded
⎛
⎜
⎞
⎟
1
1
fSW = min
,
⎜
⎝
⎟
⎠
tSW(MAX) 333.3ns
Inductor Current Rating
where
The FAN5354’s current limit circuit can allow a peak current
of 5.5A to flow through L1 under worst-case conditions. If it is
possible for the load to draw that much continuous current,
the inductor should be capable of sustaining that current or
failing in a safe manner.
⎛
⎞
⎟
⎟
⎠
VOUT +IOUT •ROFF
IN −IOUT •RON − VOUT
⎜
(4)
tSW(MAX) = 45ns• 1+
⎜
V
⎝
R
R
OFF=R
+DCR
L
DSON_N
For space-constrained applications, a lower current rating for
L1 can be used. The FAN5354 may still protect these
inductors in the event of a short circuit, but may not be able
to protect the inductor from failure if the load is able to draw
higher currents than the DC rating of the inductor.
=R
+DCR
L
ON
DSON_P
Application Information
Selecting the Inductor
Output Capacitor and VOUT Ripple
Note:
Table 1 suggests 0805 capacitors, but 0603 capacitors may
be used if space is at a premium. Due to voltage effects, the
0603 capacitors have a lower in-circuit capacitance than the
0805 package, which can degrade transient response and
output ripple.
The output inductor must meet both the required inductance
and the energy handling capability of the application. The
inductor value affects the average current limit, the output
voltage ripple, and the efficiency.
The ripple current (∆I) of the regulator is:
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
V
IN − VOUT
L • fSW
ΔI ≈
•
(5)
Increasing COUT has no effect on loop stability and can
therefore be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ∆VOUT, is:
V
IN
The maximum average load current, IMAX(LOAD) is related to
the peak current limit, ILIM(PK), by the ripple current as:
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
1
ΔVOUT = ΔI•
+ESR
(8)
ΔI
2
8•COUT • fSW
IMAX(LOAD) = ILIM(PK)
−
(6)
where COUT is the effective output capacitance. The
capacitance of COUT decreases at higher output voltages,
The FAN5354 is optimized for operation with L=470nH, but
is stable with inductances up to 1.2μH (nominal). The
inductor should be rated to maintain at least 80% of its value
which results in higher ∆VOUT
.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
11
reduce under-damped ringing that can occur between the
inductance of the power source leads and CIN.
If COUT is greater than 100μF, the regulator may fail to start
under load.
The effective CIN capacitance value decreases as VIN
increases due to DC bias effects. This has no significant
impact on regulator performance.
If an inductor value greater than 1.0μH is used, at least 30μF
of COUT should be used to ensure stability.
As can be seen in Figure 11 the lowest ∆VOUT is obtained
when the IC is in PWM mode and, therefore, operating at
3Mhz. In PFM mode, fSW is reduced, causing ∆VOUT to
increase. At extremely light loads, the output ripple
decreases, as the minimum frequency circuit becomes active
and the effective tON (high-side on-time) decreases.
Layout Recommendations
The layout recommendations below highlight various top-
copper planes by using different colors. It includes COUT3 to
demonstrate how to add COUT capacitance to reduce ripple
and transient excursions. The inductor in this example is the
TDK VLC5020T-R47N.
ESL Effects
The ESL (Equivalent Series Inductance) of the output
capacitor network should be kept low to minimize the square
wave component of output ripple that results from the division
ratio COUT ESL and the output inductor (LOUT). The square
wave component due to the ESL can be estimated as:
VCC and VIN should be connected together by a thin trace
some distance from the IC, or through a resistor (shown as
R3 below), to isolate the switching spikes on PVIN from the
IC’s bias supply on VCC. If PCB area is at a premium, the
connection between PVIN and VCC can be made on another
PCB layer through vias. The via impedance provides some
filtering for the high-frequency spikes generated on PVIN.
ESL
COUT
(9)
ΔV
≈ V
•
OUT(SQ)
IN
L1
PGND and AGND connect through the thermal pad of the IC.
Extending the PGND and AGND planes improves IC cooling.
The IC analog ground (AGND) is bonded to P1 between pins
1 and 12. Large AC ground currents should return to pins 3
and 4 (PGND) either through the copper under P1 between
pins 6 and 7 or through a direct trace from pins 3 and 4 (as
shown for COUT1-COUT3).
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value. For
example, to obtain COUT=20μF, a single 22μF 0805 would
produce twice the square wave ripple of 2 x 10μF 0805.
To minimize ESL, try to use capacitors with the lowest ratio
of length to width. 0805s have lower ESL than 1206s. If low
output ripple is a chief concern, some vendors produce 0508
or 0612 capacitors with ultra-low ESL. Placing additional
small value capacitors near the load also reduces the high-
frequency ripple components.
EN and PGOOD connect through vias to the system control
logic.
CIN1 is an optional device used to provide a lower
impedance path for high-frequency switching edges/spikes,
which helps to reduce SW node and VIN ringing. CIN should
be placed as close as possible between PGND and VIN as
shown below.
Input Capacitor
The 10μF ceramic input capacitor should be placed as close
as possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or tantalum)
should be placed between CIN and the power source lead to
PGND connection back to inner planes should be
accomplished as series of vias distributed among the COUT
return track and CIN return plane between pins 6 and 7.
AGND
0402
VOUT
COUT1
COUT3
COUT2
1
12
11
10
9
CVCC
FAN5354
10μF
0805
10μF
0805
10μF
0805
2
3
4
5
6
P1
(GND)
PGND
R3
VCC
8
VIN
7
10μF
0805
CIN1
0402
SW
CIN
0.47μH
5 x 5 mm
PGND
Figure 30. 3A Layout Recommendation
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
12
Physical Dimensions
Figure 31. 12-lead 3 x 3.5mm MLP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which
covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
13
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
www.fairchildsemi.com
14
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