FAN5354MPX [ONSEMI]
3MHz、500mA同步降压稳压器;
| 型号： | FAN5354MPX |
| 厂家： | 
ONSEMI |
| 描述： | 3MHz、500mA同步降压稳压器 开关 光电二极管 稳压器 |
| 文件： | 总16页 (文件大小：1035K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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December 2012
FAN5354
3 MHz, 3 A Synchronous Buck Regulator
Description
Features
The FAN5354 is a step-down switching voltage regulator that
delivers an adjustable output from an input voltage supply of
. 3 MHz Fixed-Frequency Operation
. Best-in-Class Load Transient
2.7 V to 5.5 V. Using
a proprietary architecture with
synchronous rectification, the FAN5354 is capable of
delivering 3 A at over 85% efficiency, while maintaining a
very high efficiency of over 80% at load currents as low as
2 mA. The regulator operates at a nominal fixed frequency of
3 MHz, which reduces the value of the external components
to 470 nH for the output inductor and 10 µF for the output
capacitor. Additional output capacitance can be added to
improve regulation during load transients without affecting
stability and inductance up to 1.2 µH may be used with
additional output capacitance.
. 3 A Output Current Capability
. 2.7 V to 5.5 V Input Voltage Range
. Adjustable Output Voltage: 0.8 to 2.0 V
. PFM Mode for High Efficiency in Light Load (Forced PWM
Available on MODE Pin)
. Minimum PFM Frequency Avoids Audible Noise
. 270 µA Typical Quiescent Current in PFM Mode
. External Frequency Synchronization
At moderate and light loads, pulse frequency modulation
(PFM) is used to operate the device in power-save mode
with a typical quiescent current of 270 µA. Even with such a
low quiescent current, the part exhibits excellent transient
response during large load swings. At higher loads, the
system automatically switches to fixed-frequency control,
operating at 3 MHz. In shutdown mode, the supply current
drops below 1 µA, reducing power consumption. PFM mode
can be disabled if constant frequency is desired. To avoid
audible noise, the regulator limits its minimum PFM
frequency. The FAN5354 is available in 12-lead 3x3.5 mm
MLP package.
. Low Ripple Light-Load PFM Mode with Forced
PWM Control
. Power Good Output
. Internal Soft-Start
. Input Under-Voltage Lockout (UVLO)
. Thermal Shutdown and Overload Protection
. 12-Lead 3x3.5 mm MLP
Applications
. Set-Top Box
. Hard Disk Drive
. Communications Cards
. DSP Power
Figure 1. Typical Application
Ordering Information
Part Number
Temperature Range
Package
Packing Method
FAN5354MPX
-40 to 85°C
MLP-12, 3 x 3.5 mm
Tape and Reel
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
Table 1. Recommended External Components for 3 A Maximum Load Current
Component
Description
Vendor
Parameter
Typ.
Units
IHLP1616ABER47M01 (Vishay)
SD12-R47-R (Coiltronics)
VLC5020T-R47N (TDK)
(TDK)
L
0.47
H
L1
470 nH Nominal
DCR
20
m
LQH55PNR47NT0 (Murata)
2 Pieces
10 F, 6.3 V, X5R, 0805
COUT
CIN
GRM21BR60J106M (Murata)
C2012X5R0J106M (TDK)
C
C
10.0
10
F
10 F, 6.3 V, X5R, 0805
GRM155R71E103K (Murata)
C1005X7R1E103K (TDK)
CIN1
10 nF, 25 V, X7R, 0402
nF
GRM188R60J475K (Murata)
C1608X5R0J475K (TDK)
CVCC
C
R
4.7
1
4.7 F, 6.3 V, X5R, 0603
Resistor: 1 0402
F
R3(1)
Any
Note:
1. R3 is optional and improves IC power supply noise rejection. See Layout recommendations for more information.
Pin Configuration
FB
VOUT
PGND
PGND
SW
1
2
3
4
5
6
12 MODE
11 PGOOD
10 EN
P1
(GND)
9
8
7
VCC
PVIN
PVIN
SW
Figure 2. 12-Pin, 3 x 3.5 mm MLP (Top View)
Pin Definitions
Pin #
Name Description
1
2
FB
FB. Connect to resistor divider. The IC regulates this pin to 0.8 V.
VOUT. Sense pin for VOUT. Connect to COUT.
VOUT
Power Ground. Low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a
minimal path to these pins.
3, 4
PGND
5, 6
P1
SW
Switching Node. Connect to inductor.
Ground. All signals are referenced to this pin.(2)
GND
PVIN
7, 8
Power Input Voltage. Connect to input power source. Connect to CIN with minimal path.
IC Bias Supply. Connect to input power source. Use a separate bypass capacitor CVCC from this pin to
the P1 GND terminal between pins 1 and 12.
9
VCC
EN
10
11
Enable. The device is in shutdown mode when this pin is LOW. Do not leave this pin floating.
PGOOD Power Good. This open-drain pin pulls LOW if the output falls out of regulation or is in soft-start.
MODE / Sync. A logic 0 allows the IC to automatically switch to PFM during light loads. When held
12
MODE
HIGH, the IC to stays in PWM mode. The regulator also synchronizes its switching frequency to the
frequency provided on this pin. Do not leave this pin floating.
Note:
2. P1 is the bottom heat-sink pad. Ground plane should flow through pins 3, 4, and P1 and can be extended through pin 11 if
PGOOD’s function is not required, and through pin 12 if MODE is to be grounded, to improve IC cooling.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum
ratings are stress ratings only.
Symbol Parameter
Min.
-0.3
-0.3
-0.3
Max.
7.0
Units
IC Not Switching
IC Switching
SW, PVIN, VCC Pins
V
VIN
6.5
VCC + 0.3(3)
Other Pins
V
VINOV_SLEW Maximum Slew Rate of VIN Above 6.5 V, PWM Switching
RPGOOD Pull-Up Resistance from PGOOD to VCC
15
V/ms
k
1
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
2
Electrostatic Discharge
Protection Level
ESD
kV
2
TJ
TSTG
TL
Junction Temperature
Storage Temperature
–40
–65
+150
+150
+260
°C
°C
°C
Lead Soldering Temperature, 10 Seconds
Note:
3. Lesser of 7.0 V or VCC+0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter
Min.
2.7
0.8
0
Typ.
Max.
5.5
2.0
3
Units
V
VCC, VIN
VOUT
IOUT
L
Supply Voltage Range
Output Voltage Range
Output Current
V
A
Inductor
0.47
10
µH
µF
μF
°C
°C
CIN
Input Capacitor
COUT
TA
Output Capacitor
20
Operating Ambient Temperature
Operating Junction Temperature
-40
-40
+85
TJ
+125
Thermal Properties
Symbol Parameter
Typical
Units
Junction-to-Ambient Thermal Resistance(4)
46
°C/W
JA
Note:
4. Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer
1s2p boards in accordance to JESD51- JEDEC standard. Special attention must be paid not to exceed junction
temperature TJ(max) at a given ambient temperate TA.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
3
Electrical Characteristics
Minimum and maximum values are at VIN=2.7 V to 5.5 V, TA=-40°C to +85°C, unless otherwise noted. Typical values are at
TA=25°C, VIN=5 V.
Symbol Parameter
Power Supplies
Conditions
Min. Typ. Max. Units
ILOAD=0, MODE=0
270
14
A
mA
A
V
IQ
Quiescent Current
Shutdown Supply Current
ILOAD=0, MODE=1 (Forced PWM)
EN=GND
I SD
0.1
3.0
VIN Rising
2.83 2.95
2.10 2.30 2.40
530
VUVLO Under-Voltage Lockout Threshold
VIN Falling
V
VUVHYST Under-Voltage Lockout Hysteresis
mV
Logic Pins
VIH
VIL
HIGH-Level Input Voltage
LOW-Level Input Voltage
1.05
V
0.4
100
V
VLHYST Logic Input Hysteresis Voltage
mV
A
mA
A
IIN
Input Bias Current
Input Tied to GND or VIN
VPGOOD=0.4 V
0.01 1.00
1
IOUTL
IOUTH
PGOOD Pull-Down Current
PGOOD HIGH Leakage Current
VPGOOD=VIN
0.01 1.00
VOUT Regulation
TA=25°C
0.792 0.800 0.808
0.788 0.800 0.812
V
V
Output Reference DC Accuracy
VREF
VREG
Measured at FB Pin
VOUT DC Accuracy
At VOUT Pin W.R.T. Calculated Value,
1.6
+1.6
%
I
LOAD=500 mA
VOUT
ILOAD
Load Regulation
IOUT(DC)=1 to 3 A
–0.03
%/A
VOUT
Line Regulation
2.7 V ≤ VIN ≤ 5.5 V, IOUT(DC)=1.5 A
0.01
±40
%/V
mV
V
IN
ILOAD Step 0.1 A to 1.5 A, tr=tf=100 ns,
Transient Response
VOUT=1.2 V
Power Switch and Protection
RDS(ON)P P-Channel MOSFET On Resistance
RDS(ON)N N-Channel MOSFET On Resistance
60
40
mΩ
mΩ
A
ILIMPK
P-MOS Peak Current Limit
3.75 4.55 5.50
TLIMIT Thermal Shutdown
150
20
°C
°C
V
THYST Thermal Shutdown Hysteresis
Rising Threshold
Falling Threshold
6.2
VSDWN Input OVP Shutdown
5.50 5.85
V
Frequency Control
fSW
Oscillator Frequency
2.7
External Square-Wave, 30% to 70% Duty Cycle 2.7
TA = 25°C, VIN = 5.0 V 17
3.0
3.0
26
3.3
3.3
36
MHz
MHz
kHz
fSYNC
MODE Pin Synchronization Range
fPFM(MIN) Minimum PFM Frequency
Soft-Start
210 250
340 420
10
R
LOAD > 5 , to VOUT=1.2 V
s
s
tSS
Regulator Enable to Regulated VOUT
RLOAD > 5 , to VOUT=1.8 V
VSLEW Soft-Start VREF Slew Rate
V/ms
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
4
Typical Characteristics
Unless otherwise specified, VIN=5 V, VOUT=1.2 V, circuit of Figure 1, and components per Table 1.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
VIN = 3.3V, Mode = 0
VIN = 3.3V, Mode = 1
VIN = 5V, Mode = 0
VIN = 5V, Mode = 1
VIN = 3.3V, Mode=0
VIN = 3.3V, Mode=1
VIN = 5V, Mode=0
VIN = 5V, Mode=1
1
10
100
1000
10000
1
10
100
1000
10000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 3. Efficiency vs. ILOAD at VOUT=1.2 V
Figure 4. Efficiency vs. ILOAD at VOUT=1.8 V
350
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
325
300
275
250
225
200
85°C
25°C
‐40°C
85°C
25°C
–40°C
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
Input Voltage(V)
Input Voltage(V)
Figure 5. Shutdown Supply Current vs. VIN, EN=0
Figure 6. Quiescent Current in PFM vs. VIN, No Load
800
1.2VOUT boundary
700
600
500
400
300
200
100
0
Always PWM
Hysteresis
1.2VOUT boundary
Always PFM
2.7
3.2
3.7
4.2
4.7
5.2
Input Voltage(V)
Figure 7. PFM / PWM Mode-Change Boundaries
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
5
Typical Characteristics
Unless otherwise specified, VIN=5 V, VOUT=1.2 V, circuit of Figure 1, and components per Table 1.
PFM
PWM
16
14
12
10
8
90
80
70
60
50
40
30
20
6
1.2VOUT,1.5Aload
4
5VIN, 1.2VOUT
3.3VIN, 1.2VOUT
2
0
0.1
1
10
100
1000
10000
0.01
0.1
1
10
100
Load Current(mA)
Frequency (KHz)
Figure 8. Output Voltage Ripple vs. Load Current
Figure 9. Power Supply Rejection Ratio (PSRR)
(See explanation on page 12)
VOUT
IL
Figure 10. PFM-to-PWM Mode Transition, Slowly
Increasing Load Current, 2 µs/div.
Figure 11 PWM-to-PFM Mode Transition, Slowly
Decreasing Load Current, 2 µs/div.
31.0
30.0
TJ = 85°C
29.0
28.0
27.0
26.0
25.0
24.0
TJ = 25°C
TJ = –40°C
2.5
3
3.5
4
4.5
5
5.5
6
Input Voltage (V)
Figure 12. PFM frequency, ILOAD = 0
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
6
Typical Characteristics
Unless otherwise specified, VIN=5 V, VOUT=1.2 V, circuit of Figure 1, and components per Table 1.
Load Transient Response (Figure 13 – Figure 16). ILOAD tR = tF = 100 ns
Figure 13. MODE=0, 100 mA to 1.5 A to 100 mA, 5 µs/div.
Figure 14. 500 mA to 3 A to 500 mA, 5 µs/div.
VOUT
IL
Iload
Figure 15. MODE=1, 100 mA to 1.5 A to 100 mA, 5 µs/div. Figure 16. 24 mA to 500 mA to 24 mA, MODE=0, 5 µs/div.
VEN
VIN=VEN
VOUT
VOUT
VPG
VPG
Isupply
Isupply
Figure 17. Soft-Start, EN Voltage Raised After VIN=5 V,
Figure 18. Soft-Start, EN Pin Tied to VCC
ILOAD=0, 1 ms/div.
ILOAD=0, 100 s/div.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
7
Typical Characteristics
Unless otherwise specified, VIN=5 V, VOUT=1.2 V, circuit of Figure 1, and components per Table 1.
Figure 19. Soft-Start, EN Pin Raised After VIN=5 V
Figure 20. Soft-Start, EN Pin Tied to VCC
RLOAD=400 m, COUT=100 F, 100 s/div.
RLOAD=400 m, COUT=100 F, 1 ms/div.
Figure 21. Line Transient Response in PWM Mode,
Figure 22. Line Transient Response in PFM Mode,
10 s/div.
10 s/div.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
8
Typical Characteristics
Unless otherwise specified, VIN=5 V, VOUT=1.2 V, circuit of Figure 1, and components per Table 1.
Circuit Protection Response
VOUT
VOUT
IL
IL
VPG
VPG
Figure 23. VOUT to GND Short Circuit, 200 s/div.
Figure 24. VOUT to GND Short Circuit, 5 s/div.
VEN
VOUT
VOUT
IL
IL
VPG
VPG
Figure 25. Over-Current at Startup, RLOAD=200 m,
50 s/div.
Figure 26. Progressive Overload, 200 s/div.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
9
Operation Description
The FAN5354 is a step-down switching voltage regulator
that delivers an adjustable output from an input voltage
supply of 2.7 V to 5.5 V. Using a proprietary architecture
with synchronous rectification, the FAN5354 is capable of
delivering 3 A at over 80% efficiency. The regulator
operates at a nominal frequency of 3 MHz at full load,
which reduces the value of the external components to
470 nH for the output inductor and 20 µF for the output
capacitor. High efficiency is maintained at light load with
single-pulse PFM mode.
down and waits 1200 s before attempting a restart. If the
regulator is at its current limit for more than about 60 s, the
regulator shuts down before restarting 1200 s later. This
limits the COUT capacitance when a heavy load is applied
during the startup. For a typical FAN5354 starting with a
resistive load:
COUTMAX(F) 400100ILOAD(A)
VOUT
(3)
where
ILOAD
RLOAD
Control Scheme
Synchronous rectification is inhibited during soft-start,
allowing the IC to start into a pre-charged load.
The FAN5354 uses a proprietary non-linear, fixed-frequency
PWM modulator to deliver a fast load transient response,
while maintaining a constant switching frequency over a wide
range of operating conditions. The regulator performance is
independent of the output capacitor ESR, allowing for the
use of ceramic output capacitors. Although this type of
operation normally results in a switching frequency that
varies with input voltage and load current, an internal
frequency loop holds the switching frequency constant over
a large range of input voltages and load currents.
MODE Pin – External Frequency
Synchronization
Logic 1 on this pin forces the IC to stay in PWM mode. A
logic 0 allows the IC to automatically switch to PFM during
light loads. If the MODE pin is toggled, the converter
synchronizes its switching frequency to the frequency on the
mode pin (fMODE).
The MODE pin is internally buffered with a Schmitt trigger,
which allows the MODE pin to be driven with slow rise and
fall times. An asymmetric duty cycle for frequency
synchronization is permitted as long as the minimum time
below VIL(MAX) or above VIH(MAX) is 100 ns.
For very light loads, the FAN5354 operates in discontinuous
current (DCM) single-pulse PFM mode, which produces low
output ripple compared with other PFM architectures.
Transition between PWM and PFM is seamless, with a glitch
of less than 18 mV at VOUT during the transition between
DCM and CCM modes. The regulator limits minimum PFM
frequency to typically 26 kHz.
PGOOD Pin
The PGOOD pin is an open-drain that pin indicates that the
IC is in regulation when its state is open. PGOOD pulls LOW
under the following conditions:
PFM mode can be disabled by holding the MODE pin HIGH.
The IC synchronizes to the MODE pin frequency. When
synchronizing to the MODE pin, PFM mode is disabled.
1. The IC has operated in cycle-by-cycle current limit for
eight or more consecutive PWM cycles.
Setting the output voltage
The output voltage is set by the R1, R2, and VREF (0.8 V):
2. The circuit is disabled, either after a fault occurs, or
when EN is LOW.
VOUT VREF
R1
R2
(1)
3. The IC is performing a soft-start.
VREF
Under-Voltage Lockout
R1 must be set at or below 100 kΩ; therefore:
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage rises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdown.
R10.8
R2
(2)
VOUT 0.8
For example, for VOUT=1.2 V, R1=100 kΩ, R2=200 kΩ.
Input Over-Voltage Protection (OVP)
Output should not be set above 2.0 V to avoid operating the
device at above 90% duty cycle.
When VIN exceeds VSDWN (about 6.2 V), the IC stops
switching to protect the circuitry from internal spikes
above 6.5 V. An internal 40 s filter prevents the circuit
from shutting down due to noise spikes. For the circuit to
fully protect the internal circuitry, the VIN slew rate above
6.2 V must be limited to no more than 15 V / ms when the
IC is switching.
Enable and Soft Start
When the EN pin is LOW, the IC is shut down, all internal
circuits are off, and the part draws very little current. Raising
EN above its threshold voltage activates the part and starts
the soft-start cycle. During soft-start, the modulator’s internal
reference is ramped slowly to minimize any large surge
currents on the input and prevents any overshoot of the
output voltage.
The IC protects itself if VIN overshoots to 7 V during initial
power-up as long as the VIN transition from 0 to 7 V occurs in
less than 10 s (10% to 90%).
If large values of output capacitance are used, the regulator
may fail to start. If VOUT fails to achieve regulation within
320 s from the beginning of soft-start, the regulator shuts
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
10
I
2
Current Limiting
IMAX(LOAD) ILIM(PK)
(6)
A heavy load or short circuit on the output causes the current
in the inductor to increase until a maximum current threshold
is reached in the high-side switch. Upon reaching this point,
the high-side switch turns off, preventing high currents from
causing damage. 16 consecutive PWM cycles in current limit
cause the regulator to shut down and stay off for about
1200 s before attempting a restart.
The FAN5354 is optimized for operation with L=470 nH, but
is stable with inductances up to 1.2 H (nominal). The
inductor should be rated to maintain at least 80% of its value
at ILIM(PK). Failure to do so lowers the amount of DC current
the IC can deliver.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since ∆I increases, the
RMS current increases, as do core and skin-effect losses.
In the event of a short circuit, the soft-start circuit attempts to
restart and produces an over-current fault after about 50 s,
which results in a duty cycle of less than 10%, providing
current into a short circuit.
I2
2
(7)
IRMS
IOUT(DC)
Thermal Shutdown
12
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the output
switching is disabled until the temperature on the die has
fallen sufficiently. The junction temperature at which the
thermal shutdown activates is nominally 150°C with a
20°C hysteresis.
The increased RMS current produces higher losses through
the RDS(ON) of the IC MOSFETs as well as the inductor ESR.
Increasing the inductor value produces lower RMS currents,
but degrades transient response. For a given physical
inductor size, increased inductance usually results in an
inductor with lower saturation current.
Minimum Off-Time Effect on Switching
Frequency
Table 2 shows the effects of inductance higher or lower than
the recommended 470 nH on regulator performance.
tON(MIN) and tOFF(MIN) are both 45 ns. This imposes constraints
VOUT
Table 2. Effects of Increasing the Inductor
Value (from 470 nH Recommended) on
Regulator Performance
on the maximum
that the FAN5354 can provide,
VIN
while still maintaining a fixed switching frequency in PWM
mode. While regulation is unaffected, the switching
frequency will drop when the regulator cannot provide
sufficient duty cycle at 3 MHz to maintain regulation.
IMAX(LOAD)
∆VOUT (EQ. 8)
Transient Response
Increase
Decrease
Degraded
The calculation for switching frequency is given below
Inductor Current Rating
1
1
fSW min
,
The FAN5354’s current limit circuit can allow a peak current
of 5.5 A to flow through L1 under worst-case conditions. If it
is possible for the load to draw that much continuous current,
the inductor should be capable of sustaining that current or
failing in a safe manner.
tSW(MAX) 333.3ns
where
VOUT IOUT ROFF
IN IOUT RON VOUT
(4)
tSW(MAX) 45ns 1
V
For space-constrained applications, a lower current rating for
L1 can be used. The FAN5354 may still protect these
inductors in the event of a short circuit, but may not be able
to protect the inductor from failure if the load is able to draw
higher currents than the DC rating of the inductor.
ROFF
=
RDSON _N DCRL
RON
=
RDSON _P DCRL
Output Capacitor and VOUT Ripple
Application Information
Note: Table
1 suggests 0805 capacitors, but 0603
Selecting the Inductor
capacitors may be used if space is at a premium. Due to
voltage effects, the 0603 capacitors have a lower in-circuit
capacitance than the 0805 package, which can degrade
transient response and output ripple.
The output inductor must meet both the required inductance
and the energy handling capability of the application. The
inductor value affects the average current limit, the output
voltage ripple, and the efficiency.
Increasing COUT has no effect on loop stability and can
therefore be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ∆VOUT, is:
The ripple current (∆I) of the regulator is:
VOUT
V
IN VOUT
L fSW
I
(5)
1
V
VOUT I
ESR
IN
(8)
8COUT fSW
The maximum average load current, IMAX(LOAD) is related to
the peak current limit, ILIM(PK), by the ripple current as:
where COUT is the effective output capacitance. The
capacitance of COUT decreases at higher output voltages,
which results in higher ∆VOUT
.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
11
If COUT is greater than 100 F, the regulator may fail to start
under load.
Layout Recommendations
The layout recommendations below highlight various top-
copper planes by using different colors. It includes COUT3
to demonstrate how to add COUT capacitance to reduce
ripple and transient excursions. The inductor in this
example is the TDK VLC5020T-R47N.
If an inductor value greater than 1.0 H is used, at least
30 F of COUT should be used to ensure stability.
As can be seen in Figure 8 the lowest ∆VOUT is obtained
when the IC is in PWM mode and, therefore, operating at
3 MHz. In PFM mode, fSW is reduced, causing ∆VOUT to
increase. At extremely light loads, the output ripple
decreases, as the minimum frequency circuit becomes active
and the effective tON (high-side on-time) decreases.
VCC and VIN should be connected together by a thin trace
some distance from the IC, or through a resistor (shown as
R3 below), to isolate the switching spikes on PVIN from the
IC’s bias supply on VCC. If PCB area is at a premium, the
connection between PVIN and VCC can be made on
another PCB layer through vias. The via impedance
provides some filtering for the high-frequency spikes
generated on PVIN.
ESL Effects
The ESL (Equivalent Series Inductance) of the output
capacitor network should be kept low to minimize the square
wave component of output ripple that results from the division
ratio COUT ESL and the output inductor (LOUT). The square
wave component due to the ESL can be estimated as:
PGND and AGND connect through the thermal pad of the
IC. Extending the PGND and AGND planes improves IC
cooling. The IC analog ground (AGND) is bonded to P1
between pins 1 and 12. Large AC ground currents should
return to pins 3 and 4 (PGND) either through the copper
under P1 between pins 6 and 7 or through a direct trace
from pins 3 and 4 (as shown for COUT1-COUT3).
ESLCOUT
VOUT(SQ) VIN
(9)
L1
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value. For
example, to obtain COUT=20 F, a single 22 F 0805 would
produce twice the square wave ripple of 2 x 10 F 0805.
EN and PGOOD connect through vias to the system
control logic.
To minimize ESL, try to use capacitors with the lowest ratio
of length to width. 0805s have lower ESL than 1206s. If low
output ripple is a chief concern, some vendors produce 0508
or 0612 capacitors with ultra-low ESL. Placing additional
small value capacitors near the load also reduces the high-
frequency ripple components.
CIN1 is an optional device used to provide a lower
impedance path for high-frequency switching edges/spikes,
which helps to reduce SW node and VIN ringing. CIN should
be placed as close as possible between PGND and VIN as
shown below.
PGND connection back to inner planes should be
accomplished as series of vias distributed among the COUT
return track and CIN return plane between pins 6 and 7.
Input Capacitor
The 10F ceramic input capacitor should be placed as close
as possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or tantalum)
should be placed between CIN and the power source lead to
reduce under-damped ringing that can occur between the
inductance of the power source leads and CIN.
The effective CIN capacitance value decreases as VIN
increases due to DC bias effects. This has no significant
impact on regulator performance.
AGND
0402
VOUT
COUT1
COUT3
COUT2
1
2
3
4
5
6
12
CVCC
FAN5354
10F
0805
10F
0805
10F
0805
11
10
P1
PGND
(GND)
R3
9
8
7
VCC
VIN
10F
0805
CIN1
0402
SW
CIN
0.47H
5 x 5 mm
PGND
Figure 27. 3 A Layout Recommendation
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
12
Physical Dimensions
Figure 28. 12-lead x 3.5 mm MLP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which
covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
13
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.7
www.fairchildsemi.com
14
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