74LCX257MTC_NL [FAIRCHILD]
暂无描述;型号: | 74LCX257MTC_NL |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | 暂无描述 复用器 |
文件: | 总9页 (文件大小:103K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
May 1995
Revised September 2000
74LCX257
Low Voltage Quad 2-Input Multiplexer
with 5V Tolerant Inputs and Outputs
General Description
Features
■ 5V tolerant inputs and outputs
The LCX257 is a quad 2-input multiplexer with 3-STATE
outputs. Four bits of data from two sources can be selected
using a Common Data Select input. The four outputs
present the selected data in true (non inverted) form. The
outputs may be switched to a high impedance state by
placing a logic HIGH on the common Output Enable (OE)
input, allowing the outputs to interface directly with bus-ori-
ented systems.
■ 2.3V–3.6V VCC specifications provided
■ 6.0 ns tPD max (VCC = 3.3V, In → Zn), 10 µA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The 74LCX257 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX257M
M16A
M16D
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX257SJ
74LCX257MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
S
Common Data Select Input
3-STATE Output Enable Input
Data Inputs from Source 0
Data Inputs from Source 1
3-STATE Multiplexer Outputs
OE
I0a–I0d
I1a–I1d
Za–Zd
© 2000 Fairchild Semiconductor Corporation
DS012466
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Functional Description
Truth Table
The LCX257 is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a Common Data Select input. When the Select
input is LOW, the I0x inputs are selected and when Select
Output
Enable
Select
Data
Outputs
Z
Input
S
Inputs
OE
I0
I1
is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in true (non
inverted) form. The device is the logic implementation of a
4-pole, 2-position switch where the position of the switch is
determined by the logic levels supplied to the Select input.
The logic equations for the outputs are shown below:
H
L
L
L
L
X
H
H
L
X
X
X
L
X
L
Z
L
H
X
X
H
L
Za = OE • (11a • S + I0a • S)
Zb = OE • (11b • S + I0b • S)
Zc = OE • (11c • S + I0c • S)
Zd = OE • (11d • S + I0d • S)
L
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
When the Output Enable (OE) is HIGH, the outputs are
forced to a high impedance state. If the outputs are tied
together, all but one device must be in the high impedance
state to avoid high currents that would exceed the maxi-
mum ratings. Designers should ensure the Output Enable
signals to 3-STATE devices whose outputs are tied
together are designed so there is no overlap.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 2)
IIK
DC Input Diode Current
DC Output Diode Current
−50
−50
VI < GND
mA
mA
IOK
V
V
O < GND
O > VCC
+50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 4)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
5.5
±24
±12
±8
Units
VCC
Supply Voltage
Operating
Data Retention
V
V
V
VI
Input Voltage
VO
Output Voltage
HIGH or LOW State
3-STATE
0
0
IOH/IOL
Output Current
V
V
V
CC = 3.0V − 3.6V
CC = 2.7V − 3.0V
CC = 2.3V − 2.7V
mA
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum rating must be observed.
Note 4: Unused Inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
VIH
Parameter
Conditions
Units
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
Min
1.7
2.0
Max
HIGH Level Input Voltage
V
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
VOH
I
I
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −8 mA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OL = 100 µA
OL = 8 mA
V
CC − 0.2
1.8
2.7
2.2
V
V
3.0
2.4
3.0
2.2
VOL
LOW Level Output Voltage
2.3 − 3.6
2.3
0.2
0.6
OL = 12 mA
OL = 16 mA
OL = 24 mA
2.7
0.4
3.0
0.4
3.0
0.55
±5.0
II
Input Leakage Current
0 ≤ VI ≤ 5.5V
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
2.3 − 3.6
µA
µA
µA
IOZ
3-STATE Output Leakage
2.3 − 3.6
±5.0
IOFF
Power-Off Leakage Current
VI or VO = 5.5V
0
10
3
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DC Electrical Characteristics (Continued)
VCC
TA = −40°C to +85°C
Symbol
ICC
Parameter
Conditions
Units
(V)
Min
Max
10
Quiescent Supply Current
VI = VCC or GND
3.6V ≤ VI, VO ≤ 5.5V (Note 5)
VIH = VCC −0.6V
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
µA
µA
±10
500
∆ICC
Increase in ICC per Input
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500 Ω
CC = 2.7V
L = 50 pF
Max
V
CC = 3.3V ± 0.3V
CL= 50 pF
V
V
CC = 2.5V ± 0.2V
Symbol
Parameter
Units
C
CL= 30 pF
Min
Max
7.0
7.0
6.0
6.0
7.0
7.0
5.5
5.5
1.0
1.0
Min
Min
Max
9.1
9.1
7.2
7.2
9.1
9.1
6.6
6.6
tPHL
Propagation Delay
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
8.5
8.5
6.5
6.5
8.5
8.5
6.0
6.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
tPLH
tPHL
tPLH
tPZL
S→Zn
Propagation Delay
In→Zn
Output Enable Time
OE →Zn
tPZH
tPLZ
Output Disable Time
OE →Zn
tPHZ
tOSHL
tOSLH
Output to Output Skew (Note 6)
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.8
Quiet Output Dynamic Peak VOL
C
C
C
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
V
V
0.6
VOLV
Quiet Output Dynamic Valley VOL
−0.8
−0.6
Capacitance
Symbol
Parameter
Conditions
CC = Open, VI = 0V or VCC
Typical
Units
pF
CIN
Input Capacitance
Output Capacitance
V
V
V
7
8
COUT
CPD
CC = 3.3V, VI = 0V or VCC
pF
Power Dissipation Capacitance
CC = 3.3V, VI = 0V or VCC, f = 10 MHz
25
pF
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4
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
PZL, tPLZ
Switch
Open
t
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tR = tF = 3ns)
VCC
Symbol
Vmi
3.3V ± 0.3V
1.5V
1.5V
2.7V
2.5V ± 0.2V
VCC/2
VCC/2
1.5V
1.5V
Vmo
Vx
V
V
OL + 0.3V
OH − 0.3V
V
V
OL + 0.3V
OH − 0.3V
V
V
OL + 0.15V
OH − 0.15V
Vy
5
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Schematic Diagram Generic for LCX Family
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6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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