74LCX27 [FAIRCHILD]
Low Voltage Triple 3-Input NOR Gate with 5V Tolerant Inputs; 低压三重3输入NOR门与5V容限输入
| 型号： | 74LCX27 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Triple 3-Input NOR Gate with 5V Tolerant Inputs |
| 文件： | 总8页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2001
Revised February 2001
74LCX27
Low Voltage Triple 3-Input NOR Gate
with 5V Tolerant Inputs
General Description
The LCX27 contains three 3-input NOR gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V sys-
tems to 3V systems.
Features
■ 5V tolerant inputs
■ 2.3V–3.6V VCC specifications provided
■ 4.9 ns tPD max (VCC = 3.3V), 10 µA ICC max
The 74LCX27 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
■ Power down high impedance inputs and outputs
■ ±24 mA output drive (VCC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number Package Number
Package Description
74LCX27M
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX27SJ
74LCX27MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Truth Table
O
n = An + Bn + Cn
Pin Names
An, Bn, Cn
On
Description
Inputs
Inputs
Bn
Output
On
Outputs
An
Cn
H
X
X
L
X
H
X
L
X
X
H
L
L
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
© 2001 Fairchild Semiconductor Corporation
DS500454
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Absolute Maximum Ratings(Note 1)
Symbol
VCC
VI
Parameter
Supply Voltage
Value
Conditions
Units
V
−0.5 to +7.0
−0.5 to +7.0
DC Input Voltage
V
VO
DC Output Voltage
−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 2)
V
IIK
DC Input Diode Current
DC Output Diode Current
−50
−50
VI < GND
mA
IOK
V
V
O < GND
O > VCC
mA
+50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 3)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
±24
±12
±8
Units
VCC
Supply Voltage
Operating
V
Data Retention
VI
Input Voltage
Output Voltage
Output Current
V
V
VO
HIGH or LOW State
0
I
OH/IOL
VCC = 3.0V − 3.6V
V
CC = 2.7V - 3.0V
CC = 2.3V - 2.7V
mA
V
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 2: IO Absolute Maximum Rating must be observed.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
VIH
Parameter
Conditions
Units
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
Min
1.7
2.0
Max
HIGH Level Input Voltage
V
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
VOH
I
I
I
I
I
I
I
I
I
I
OH = −100 µA
V
CC − 0.2
OH = −8 mA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OL = 100 µA
OL = 8mA
1.8
2.7
2.2
V
V
3.0
2.4
3.0
2.2
VOL
LOW Level Output Voltage
2.3 − 3.6
2.3
0.2
0.6
0.4
0.4
0.55
±5.0
10
OL = 12 mA
OL = 16 mA
OL = 24 mA
2.7
3.0
3.0
II
Input Leakage Current
0 ≤ VI ≤ 5.5V
2.3 − 3.6
0
µA
µA
IOFF
ICC
Power-Off Leakage Current
Quiescent Supply Current
VI or VO = 5.5V
VI = VCC or GND
3.6V ≤ VI ≤ 5.5V
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
10
µA
µA
±10
500
∆ICC
Increase in ICC per Input
VIH = VCC −0.6V
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2
AC Electrical Characteristics
T
A = −40°C to +85°CF, RL = 500Ω
CC = 2.7V
L = 50pF
Max Min
V
CC = 3.3V ± 0.3V
L = 50pF
Max
V
VCC = 2.5V ± 0.2V
L = 30pF
Max
Symbol
Parameter
Units
C
C
C
Min
Min
tPHL
Propagation Delay
1.5
1.5
4.9
4.9
1.0
1.0
1.5
1.5
5.8
5.8
1.5
1.5
5.9
5.9
ns
ns
tPLH
tOSHL
tOSLH
Output to Output Skew (Note 4)
Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
VOLP
Parameter
Conditions
Unit
V
(V)
3.3
2.5
3.3
2.5
Typical
0.8
Quiet Output Dynamic Peak VOL
C
C
C
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
0.6
VOLV
Quiet Output Dynamic Valley VOL
−0.8
−0.6
V
Capacitance
Symbol
Parameter
Conditions
CC = Open, VI = 0V or VCC
Typical
Units
pF
CIN
Input Capacitance
Output Capacitance
V
V
V
7
8
COUT
CPD
CC = 3.3V, VI = 0V or VCC
pF
Power Dissipation Capacitance
CC = 3.3V, VI = 0V or VCC, f = 10 MHz
25
pF
3
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AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
PZL, tPLZ
Switch
Open
t
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
1.5V
2.5V ± 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
VCC/2
V
V
OL + 0.3V
OH − 0.3V
V
V
OL + 0.3V
V
V
OL + 0.15V
OH − 0.15V
Vy
OH − 0.3V
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4
Schematic Diagram Generic for LCX Family
5
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M14A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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