QLUM3216-PT280C [ETC]
Telecommunication IC ; 电信IC\n型号: | QLUM3216-PT280C |
厂家: | ETC |
描述: | Telecommunication IC
|
文件: | 总22页 (文件大小:238K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
QLUM3216-PT280C Device Data Sheet
Utopia Level 3 to Level 2 Master/Master Bridge
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1.0 Utopia Level 3 to Level 2 Master Bridge Features
• Implements one Utopia L3 Master and one Utopia L2 Master providing a solution to
bridge Utopia Slave devices of different Levels
• Compliant with ATM-Forum af-phy-0039.000 (L2) and af-phy-0136.000 (L3)
specification
• Single chip solution for improved system integration
• Supports 16 Bit busses on both interfaces, single PHY
• Support for cell level transfer mode
• Meets 50MHz performance on Level 2 interface offering up to 800Mbps cell rate
transfers
• Cell and clock rate decoupling with on chip FIFOs
• Up to 1.5 KByte of on chip FIFO per data direction
• Integrated management interface and built-in errored cell discard
• ATM Cell size programmable via external pins from 16 to 128 bytes
• Optional Utopia parity generation/checking enable/disable via external pin
• Built in JTAG port (IEEE1149 compliant)
• Simulation model available for system level verification (Contact Quicklogic for details)
• Solution also available as flexible Soft-IP core, delivered with a full device modelization
and verification testbenches
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QLUM3216-PT280C Device Data Sheet
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QLUM3216-PT280C Device Data Sheet
2.0 Utopia Overview
The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by
the ATM Forum to provide a standard interface between ATM devices and ATM PHY or
SAR (segmentation and Re-assembly) devices.
Figure 1: Utopia Reference Model
The Utopia Standard defines a full duplex bus interface with a Master/Slave paradigm. The
Slave interface responds to the requests from the Master. The Master performs PHY
arbitration and initiates data transfers to and from the Slave device.
The ATM forum has standardized the Utopia Levels 1 (L1) to 3 (L3). Each level extends
the maximum supported interface speed from OC3, 155Mbps (L1) over OC12, 622Mbps
(L2) to 3.2Gbit/s (L3).
The following Table 1 gives an overview of the main differences in these three levels.
Table 1: Utopia Level Differences
Utopia Level
Interface Width
8-bit
Max. Interface Speed
25 MHz
Maximum Throughput
200 Mbps (typ. OC3 155 Mbps)
800 Mbps (typ. OC12 622 Mbps)
3.2 Gbps (typ. OC48 2.5 Gbps)
1
2
3
8-bit, 16-bit
8-bit, 32-bit
50 MHz
104 MHz
Utopia Level 1 implements an 8-bit interface running at up to 25MHz. Level 2 adds a 16
Bit interface and increases the speed to 50MHz. Level 3 extends the interface further by
a 32 Bit word-size and speeds up to 104MHz providing rates up to 3.2 Gbit/s over the
interface.
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QLUM3216-PT280C Device Data Sheet
In addition to the differences in throughput, Utopia Level 2 uses a shared bus offering to
physically share a single interface bus between one master and up to 31 slave devices
(Multi-PHY or MPHY operation). This allows the implementation of aggregation units that
multiplex several slave devices to a single Master device. The Level 2 and Level 3 are point-
to-point only, whereas Level 1 has no notion of multiple slaves. Level 3 still has the notion
of multiple slaves, but they must be implemented in a single physical device connected to
the Utopia Interface.
3.0 Utopia Master/Master Bridge Application
As it is not possible to connect two Slave devices together, the Master/Master Bridge
provides the necessary interfaces to convey between two Slave devices as shown in
Figure 2.
Figure 2: Utopia Master Bridge
The Bridge automatically transfers data as soon as it becomes available from one side to
the other. Internal asynchronous FIFOs enable independent clock domains for each
interface.
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QLUM3216-PT280C Device Data Sheet
4.0 Application
Figure 3: Master/Master Bridge connecting two Slave Devices
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QLUM3216-PT280C Device Data Sheet
5.0 Bridge Core Pinout
Bridge Core implements all the required Utopia signals and provides all the Utopia optional
signals (Indicated by an 'O' in the following tables).
In addition to the Utopia Interface signals, error indication signals are available for error
monitoring or statistics. An error indication always shows that a cell has been discarded by
the bridge. Possible errors are parity or cell-length errors on the receive interface of the
corresponding Utopia Interfaces.
All Utopia interfaces work in the same transfer mode (cell level).
To identify the sides of the bridge, the notion "WEST" and "EAST" for the corresponding
interfaces will be used.
Figure 4: Utopia Level 2 Master/Master Bridge Top Entity
5.1 Signal Descriptions
Table 2: Global Signal
Pin
Mode
Description
reset
In
Active high chip reset
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Table 3: Device Management Interface
Pin
Mode
Description
Receive error indication on west receive interface. When driven high, indicates
that an errored cell (Wrong parity or wrong length) was received from the device
connected to the west interface and is discarded.
wrx_err
Out
Out
Out
Out
Receive error status information for west receive interface. When wrx_err is
driven, indicates the error status of the discarded cell:
• wrx_err_stat(0) : When set to ‘1’ indicates that a cell is discarded because of
a parity error.
wrx_err_stat(1:0)
• wrx_err_stat(1) : When set to ‘1’ indicates that a cell is discarded because it
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia
interface within less than a complete cell time).
Receive error indication on east receive interface(s). When driven high, indicates
that an errored cell (Wrong parity or wrong length) was received from the device
connected to the east interface side.
erx_err(n)
Receive error status information for east receive interface. When erx_err is
driven, indicates the error status of the discarded cell:
• erx_err_stat(0) : When set to ‘1’ indicates that a cell is discarded because of
a parity error.
erx_err_stat(n)
(1:0)
• erx_err_stat(1) : When set to ‘1’ indicates that a cell is discarded because it
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia
interface within less than a complete cell time).
Table 4: West Utopia Master Transmit Interface
Pin
wtxclk
Mode
In
Description
90MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk
rising edge.
wtxdata[15:0]
wtxprty
Out
Out
Transmit data bus.
Transmit data bus parity. Standard odd or non-standard even parity can be
optionally checked by the connected Slave.
When the parity check is disabled during the Core configuration, or not used in
the design, the pin txprty should be left open.
Transmit start of cell. Asserted by the Master to indicate that the current word is
the first word of a cell.
wtxsoc
wtxenb
Out
Out
Active low transmit data transfer enable.
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space to accept one cell.
wtxclav[0]
In
In
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected during the Core configuration, one txclav signal is
implemented per PHY port. The maximum number of clav signals is limited to
four.
wtxclav[3:1] (0)
Utopia transmit address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
wtxaddr[4:0]
Out
NOTE: (O) indicates optional signals.
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QLUM3216-PT280C Device Data Sheet
Table 5: West Utopia Master Receive Interface
Pin
wrxclk
Mode
In
Description
90MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk
rising edge.
wrxdata[15:0]
In
Receive data bus.
Receive data bus parity. Standard odd or non standard even parity can be
optionally generated by the Utopia Slave Core.
When the parity generation is disabled during the Core configuration, the pin
rxprty can be let unconnected.
wrxprty(0)
In
Receive start of cell. Asserted to indicate that the current word is the first word of
a cell.
wrxsoc
wrxenb
In
Out
Active low transmit data transfer enable.
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space one cell available in the FIFO.
wrxclav[0]
In
In
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected, one rxclav signal is implemented per PHY port. The
maximum number of clav signals is limited to four.
wrxclav[3:1] (0)
Utopia receive address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
wrxaddn(4:0)
Out
Table 6: East Utopia Master Transmit Interface
Pin
etxclk
Mode
In
Description
50MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk
rising edge.
etxdata[15:0]
Out
Transmit data bus. The width of the data bus is 16 bit. Bit N is the MSB.
Transmit data bus parity. Standard odd or non-standard even parity can be
optionally checked by the connected Slave.
When the parity check is disabled during the Core configuration, or not used in
the design, the pin txprty should be left open.
etxprty
Our
Transmit start of cell. Asserted by the Master to indicate that the current word is
the first word of a cell.
etxsoc
etxenb
Out
Out
Active low transmit data transfer enable.
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space to accept one cell.
etxclav[0]
In
In
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected during the Core configuration, one txclav signal is
implemented per PHY port. The maximum number of clav signals is limited
to four.
etxclav[3:1] (0)
Utopia transmit address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
etxaddr[4:0]
Out
NOTE: (O) indicates optional signals.
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Table 7: East Utopia Master Receive Interface
Pin
erxclk
Mode
Description
50MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk
rising edge.
In
In
erxdata[15:0]
Receive data bus.
Receive data bus parity. Standard odd or non standard even parity can be
optionally generated by the Utopia Slave Core.
When the parity generation is disabled during the Core configuration, the pin
rxprty can be let unconnected.
erxprty (0)
In
Receive start of cell. Asserted to indicate that the current word is the first word of
a cell.
erxsoc
erxenb
In
Out
Active low transmit data transfer enable.
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space one cell available in the FIFO.
erxclav[0]
In
In
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected, one rxclav signal is implemented per PHY port. The
maximum number of clav signals is limited to four.
rxclav[3:1] (0)
Utopia receive address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
taddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
erxaddr(4:0)
Out
Table 8: Device Configuration Pins
Description
Pin
Mode
Enable parity checking on the Utopia interface.
prty_en
In
If disabled (tied to 0), the wrx_err_stat(0) signal can be ignored and left open and
the rx parity input should be tied to 0. Also the tx parity pins can be left open.
Define cellsize: sets the size in bytes of a cell. Binary value to be set usually by
board wiring. The size must be a multiple of 2.
cellsize[7:0]
In
The configuration pins are not intended for change during operation. They are usually
board wired to configure the device for operation.
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QLUM3216-PT280C Device Data Sheet
6.0 Signal Descriptions
The externally provided Utopia Transmit and Receive clocks are connected to global
resources to provide low skew and fast chip level distribution. In both data directions, the
two corresponding Utopia Interfaces are decoupled by asynchronous FIFOs.
Therefore each interface runs completely independently each at its own tx and rx clocks
which typically are up to 104 MHz on the Level 3 interface (west) and up to 50 MHz on
the Level 2 interface (east).
The Error indications of the two receive interfaces are always sampled within the west clock
domains. The errors of the east rx interface is available on the erx_err signal, which is
handled using the west clock domain (wtxclk). The west rx error is directly derived from the
west rx block (wrxclk).
Figure 5: Master/Master Bridge Clock Distribution
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QLUM3216-PT280C Device Data Sheet
7.0 Functional Description - Utopia Interface
The Utopia Bridge operates in single PHY mode. Therefore no address bus and only a
single status pin (clav[0]) per direction is used on the interfaces.
7.1 Utopia Level 2 Interface Single PHY Transmit Interface
The Transmit interface is controlled by the Master (usually ATM layer).
The transmit interface has data flowing in the same direction as the Master's enable
ut_txenb. The Master transmit block generates all output signals on the rising edge of
the ut_txclk.
Transmit data is transferred from the Master to Slave via the following procedure. The
Slave indicates it can accept data using the ut_txclav(Mapped to ut_txfull in Octet level
transfer mode) signal, then the Master drives data onto ut_txdatand asserts ut_txenb.
The Slave controls the flow of data via the ut_txclavsignal.
7.1.1 Cell Level Transfer - Single Cell
The Slave asserts ut_txclav 1 when it is capable of accepting the transfer of a whole
cell. The Master asserts ut_txenb(Low) to indicate that it drives valid data to the Slave
2. Together with the first word of a cell, the Master asserts ut_txsocfor one clock
cycle 3.
To ensure that the Master does not cause transmit overrun, the Slave must de-assert
ut_txclavat least 4 cycles before the end of a cell if it cannot accept the immediate
transfer of the subsequent cell 4.
The Master can pause the cell transfer by de-asserting ut_txenb5. To complete the
transfer to the Slave, the Master de-asserts ut_txenb6.
Figure 6: Single Cell Transfer - Cell Level Transfer
7.1.2 Cell Level Transfer - Back to Back Cells
When, during a cell transfer, the Slave is able to receive a subsequent cell, the Master can
keep ut_txenbasserted between two cells 1 and asserts ut_txsoc, to start a new cell
transfer, immediately after the last word of the previous cell 2.
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QLUM3216-PT280C Device Data Sheet
Figure 7: Back to Back Cell Transfer - Cell Level Transfer
7.1.3 Octet Level Transfer - Single Cell
During a time period termed the transmit window, the Slave stores data from ut_txdata,
if ut_txenbis asserted 1. The transmit window exists from the time that the Slave
indicates it can accept data by de-asserting the active low ut_txfull(Mapped to Master
signal ut_txclav), until four valid write cycles after the Slave layer asserts
ut_txfull 2.
The Slave asserts the active low ut_txfullwhen it cannot accept data. The Master stops
sending data (ut_txenbde-asserted) three clock cycles after ut_txfullis asserted by
the Slave 3.
When the Slave is able to receive new data, it de-asserts ut_txfull4. The Master
resumes the transfers and re-asserts ut_txenb5.
Figure 8: Cell Transfer - Octet Level Transfer
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QLUM3216-PT280C Device Data Sheet
7.2 Utopia Level 2 Interface Single PHY Receive Interface
The Receive interface is controlled by the Master interface. The receive interface has data
flowing in the opposite direction to the Master's enable ut_rxenb.
Receive data is transferred from the Slave to Master via the following procedure. The Slave
indicates it has valid data, then the Master asserts ut_rxenbto read this data from the
Slave. The Slave indicates valid data (thereby controlling the data flow) via the
ut_rxclavsignal.
7.2.1 Cell Level Transfer - Single Cell
The Slave asserts ut_rxclavwhen it is ready to send a complete cell to the Master device
1. The Master asserts ut_rxenbto start the cell transfer. The Slave samples ut_rxenb
and start driving data 2. The Slave asserts ut_rxsoctogether with the cell first word to
indicate the start of a cell 3.
The Master can pause a transfer by de-asserting ut_rxenb4. The Slave samples high
ut_rxenband stops driving data 5. To resume the transfer, the Master re-asserts
ut_rxenb6. The Slave samples low ut_rxenband starts driving valid data 7.
The Master drives ut_txenbhigh one before the expected end of the current cell if the
Slave has no more cell to transfer 8. The Slave de-asserts ut_rxclav to indicate that no
new cell is available 9.
Figure 9: Single Cell Transfer - Cell Level Transfer
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QLUM3216-PT280C Device Data Sheet
7.2.2 Cell Level Transfer - Back to Back Cells
The Master keeps ut_rxenbasserted at the end of a cell transfer 1 if the Slave has a new
cell to send, the Slave should then keep ut_rxclavasserted 2 and immediately drives
the new cell asserting ut_rxsocto indicate the start of a new cell 3.
Figure 10: Back to Back Cells Transfer - Cell Level Transfer
7.3 Utopia Level 3 Interface Single PHY Receive Interface
The Receive interface is controlled by the Master interface. The receive interface has data
flowing in the opposite direction to the Master's enable ut_rxenb.
Receive data is transferred from the Slave to the Master via the following procedure. The
Slave indicates it has valid data, then the Master asserts ut_rxenbto read this data from
the Slave. The Master indicates valid data (thereby controlling the data flow) via the
ut_rxclavsignal.
When a cell transfer is initiated, the transfer cannot be paused by the Master or the Slave.
7.3.1 Cell Level Transfer - Single Cell
The Slave asserts ut_rxclavwhen it is ready to send a complete cell to the Master 1.
The Master interface asserts ut_rxenbto start the cell transfer 2. The Slave samples
ut_rxenband start driving data on the following clock edge 3. The Slave asserts
ut_rxsoctogether with the cell first word to indicate the start of a cell 4.
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QLUM3216-PT280C Device Data Sheet
The Master drives ut_txenbhigh two clock cycles before the expected end of the current
cell if the Slave has no more cell to transfer 5. The Slave de-asserts ut_rxclavto indicate
that no new cell is available 6 together with the start of cell indication.
Figure 11: Single Cell Transfer - Cell Level Transfer
7.3.2 Cell Level Transfer - Back to Back Cells
If the Master keeps ut_rxenbasserted at the end of a cell transfer 1 and if the Slave has
a new cell to send, the Slave keeps ut_rxclavdrives the new cell asserting ut_rxsoc
to indicate the start of a new cell 2.
Figure 12: Back to Back Cells Transfer
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QLUM3216-PT280C Device Data Sheet
8.0 Core Management and Error Handling
On Ingress, the Utopia Master Blocks are designed to handle and report Utopia errors such
as Parity error or wrong cell length. Errored cells are discarded with an error status
provided on pins for use by external management facilities.
The error handling only applies to the corresponding receive parts of the core
(i.e. Ingress Ports).
When an errored cell is received on the Utopia interface, the Core discards the complete
cell and provides a cell discard indication (Signal eg_err asserted) 1 together with a cell
discard status (Signal eg_err_stat(n)(m:0)) 2.
NOTE: eg_err is routed to the corresponding wrx_err and erx_err respectively (see Figure 4).
Figure 13: Cell Discard Indication
Table 9: Error Status Word Bit Coding
Error Status Bit
Name
Description
Valid when wrx/erx_err is asserted. If set to one indicates that a cell is discarded
with a parity error decoded by the Core.
0
PARITY_ERR
Valid when wrx/erx_err is asserted. If set to one indicates that a cell is discarded
with a cell length error detected on the Utopia interface.
1
LENGTH_ER
The signals are sampled on the corresponding clocks from the west interface:
• erx_... sampled with wtxclk (west transmit clock)
• wrx_... sampled with wrxclk (west receive clock)
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QLUM3216-PT280C Device Data Sheet
9.0 Complexity and Performance Summary
9.1 Timing Parameters Definition
Figure 14: Tco Timing Parameter Definition
Figure 15: Tsu Timing Parameter Definition
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QLUM3216-PT280C Device Data Sheet
Table 10: 16-Bit Utopia Interface Timing Characteristics
Parameter
tco
typ
7.0
2.5
Max
6.0
2.0
90
Unit
ns
tsu
ns
wrxclk
wtxclk
erxclk
etxclk
MHz
MHz
MHz
MHz
90
50
50
minimum reset
time
50
ns
NOTE: Timing model "worst" case is used.
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QLUM3216-PT280C Device Data Sheet
10.0 Device Pinout
10.1 Signals Overview
Table 11: Signals Overview Table
Signals
Description
wrxclk, wrxclav, wrxenb*,
West Utopia Receive Interface.
wrxdat, wrxsoc
wtxclk, wtxclav, wtxenb*,
wtxdata, wtxsoc
West Utopia Transmit Interface.
wrx_err, wrx_err_stat
West Interface error indication (sampled with wrxclk).
erxclk, erxclav, erxenb*,
erxdata, erxsoc
East Utopia Receive Interface.
etxclk, etxclav, etxenb*,
etxdata, etxsoc
East Utopia Transmit Interface.
erx_err, erx_err_stat
East Interface error indication (sampled with wtxclk).
Configuration Pins to be board wired.
prty_en, cellsize
reset
Cellsize [0] should be tied to GND.
Active high device reset
GND
VCC
Ground
Device Power 2.5 V
clk(x)
unused clock inputs should be tied to GND
IOCTRL(x)
VCCIO(x)
INREF(x)
PLLRST(x)
PLLOUT(x)
VCCPLL(x)
GNDPLL(x)
TCK, TRSTB
TMS, TDI
TDO
IO Power 3.3 V
connect to GND
connect to GND or VCC
connect to GND or VCC
JTAG signals. connect to GND
JTAG signals. connect to VCC
JTAG signal. leave open
iov
nc
not connected. should be left open
*: active low signal
NOTE: Unused Pins (data busses) in the following tables are to be handled like "nc".
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QLUM3216-PT280C Device Data Sheet
10.2 280 Pin FPBGA (PT280) Device Diagram
EAST receive error indication
QLUM3216
-PT280C
Figure 16: PT280 bottom view
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QLUM3216-PT280C Device Data Sheet
10.3 280 Pin FPBGA (PT280) Pinout Table
Table 12: 280 Pin FPBGA (PT280) Pinout Table
PIN
A1
Function
pllout(3)
gndpll(0)
erx_err
erx_err_stat[0]
erx_err_stat[1]
ioctrl(f)
wtxclav[0]
wtxprty
wtxenb
wtxclk
PIN
D1
Function
N/C
PIN
G19
H1
Function
wrxdat[12]
N/C
PIN
N16
N17
N18
N19
P1
Function
N/C
PIN
U6
Function
inref(a)
N/C
A2
D2
N/C
N/C
U6
A3
D3
N/C
H2
N/C
ioctrl(c)
ioctrl(c)
erxdat[10]
erxdat[11]
ioctrl(h)
inref(h)
vcc
U8
N/C
A4
D4
N/C
H3
N/C
U9
vccio(a)
erxclk
vccio(b)
N/C
A5
D5
N/C
H4
N/C
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
V1
A6
D6
nc (cellsize[0])
prty_en
reset
H5
vcc
P2
A7
D7
H15
H16
H17
H18
H19
J1
vcc
P3
A8
D8
vcc
P4
etxdat[13]
ioctrl(b)
vccio(b)
etxdat[5]
tdo
A9
D9
clk(8)
wrxdat[13]
wrxdat[14]
wrxdat[15]
N/C
P5
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
E1
wrxclav[0]
wrxprty
wrxenb
inref(e)
wrxsoc
wrxdat[0]
wrxdat[1]
wrxdat[2]
wrxdat[3]
wrxdat[4]
cellsize[3]
cellsize[2]
vccio(g)
cellsize[1]
gnd
P15
P16
P17
P18
P19
R1
gnd
wtxsoc
wtxdat[0]
wtxdat[1]
ioctrl(e)
wtxdat[2]
wtxdat[3]
wtxdat[4]
pllrst(1)
gnd
N/C
N/C
J2
N/C
wrx_err
wrx_err_stat[0]
erxdat[7]
erxdat[8]
vccio(h)
erxdat[9]
gnd
pllrst(2)
etxprty
pllout(2)
gndpll(3)
gnd
J3
vccio(g)
N/C
J4
J5
gnd
R2
V2
J15
J16
J17
J18
J19
K1
vcc
R3
V3
N/C
R4
V4
erxprty
erxenb
ioctrl(a)
N/C
vccio(d)
N/C
R5
V5
pllrst(0)
gnd
R6
gnd
V6
B2
E2
N/C
R7
vcc
V7
B3
wtxdat[5]
wtxdat[6]
wtxdat[7]
inref(f)
E3
vcc
R8
vcc
V8
N/C
B4
E4
K2
tck
R9
gnd
V9
N/C
B5
E5
K3
N/C
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
T1
gnd
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W1
clk(1)
B6
E6
vcc
K4
N/C
vcc
clk(4)
B7
wtxdat[8]
wtxdat[9]
tms
E7
vcc
K5
gnd
vcc
N/C
B8
E8
vcc
K15
K16
K17
K18
K19
L1
gnd
vcc
etxdat[14]
inref(b)
etxdat[9]
etxdat[6]
etxdat[1]
gndpll(2)
gnd
B9
E9
vcc
N/C
vcc
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
C1
clk(6)
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
F1
gnd
N/C
gnd
wtxdat[10]
wtxdat[11]
ioctrl(e)
wtxdat[12]
wtxdat[13]
wtxdat[14]
vccpll(1)
gndpll(1)
pllout(0)
N/C
gnd
N/C
etxdat[3]
vccio(c)
etxenb
wrx_err_stat[1]
erxdat[2]
erxdat[3]
erxdat[4]
erxdat[5]
erxdat[6]
ioctrl(a)
N/C
vcc
trstb
vcc
N/C
gnd
L2
N/C
gnd
L3
vccio(h)
N/C
gnd
wrxdat[5]
vccio(d)
inref(d)
ioctrl(d)
inref(g)
ioctrl(g)
cellsize[5]
cellsize[4]
gnd
L4
T2
W2
pllrst(3)
nc
L5
vcc
T3
W3
L15
L16
L17
L18
L19
M1
M2
M3
M4
M5
M15
M16
M17
M18
M19
N1
gnd
T4
W4
nc
N/C
T5
W5
nc
vccio(c)
N/C
T6
W6
erxclav[0]
N/C
C2
vccpll(0)
N/C
F2
T7
W7
C3
F3
N/C
T8
N/C
W8
N/C
C4
N/C
F4
etxdat[15]
N/C
T9
N/C
W9
tdi
C5
vccio(f)
ioctrl(f)
N/C
F5
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
U1
N/C
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
etxclk
C6
F15
F16
F17
F18
F19
G1
vcc
N/C
clk(3)
N/C
C7
ioctrl(d)
wrxdat[6]
wrxdat[7]
wrxdat[8]
N/C
N/C
N/C
N/C
C8
N/C
vcc
etxdat[12]
etxdat[11]
etxdat[8]
etxdat[4]
vccpll(2)
etxsoc
etxclav[0]
erxsoc
erxdat[0]
vccpll(3)
erxdat[1]
vccio(a)
etxdat[15]
ioctrl(b)
etxdat[10]
etxdat[7]
etxdat[2]
etxdat[0]
pllout(1)
C9
vccio(f)
wrxclk
vcc
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
inref(c)
N/C
vccio(e)
N/C
G2
cellsize[7]
ioctrl(g)
cellsize[6]
vcc
N/C
N/C
G3
N/C
N/C
G4
ioctrl(h)
etxdat[12]
etxdat[13]
etxdat[14]
vcc
vccio(e)
N/C
G5
N2
G15
G16
G17
G18
vcc
N3
U2
N/C
wrxdat[9]
wrxdat[10]
wrxdat[11]
N4
U3
N/C
N5
U4
N/C
N15
vcc
U5
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www.quicklogic.com
© 2001 QuickLogic Corporation
QLUM3216-PT280C Device Data Sheet
11.0 References
• ATM Forum, Utopia Level 2, af-phy-0039.000
• ATM Forum, Utopia Level 3, af-phy-0136.000
12.0 Contact
QuickLogic Corp.
Tel
: 408 990 4000 (US)
: + 44 1932 57 9011 (Europe)
: + 49 89 930 86 170 (Germany)
: + 852 8106 9091 (Asia)
: + 81 45 470 5525 (Japan)
E-mail : info@quicklogic.com
Internet : www.quicklogic.com
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QLUM3216-PT280C Device Data Sheet
21
QLUM3216-PT280C Device Data Sheet
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www.quicklogic.com
© 2001 QuickLogic Corporation
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