QLUM3309-PT280C [ETC]
Telecommunication IC ; 电信IC\n
| 型号： | QLUM3309-PT280C |
| 厂家： | 
ETC |
| 描述： | Telecommunication IC
|
| 文件： | 总20页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QLUM3309-PT280C Device Datasheet
Utopia Level 3 Master Bridges
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1.0 Utopia Level 3 (L3) Bridge Core Features
• Implements two Utopia L3 Masters providing a solution to bridge Utopia Slave devices
• Compliant with ATM-Forum af-phy-0136.000 (Utopia L3)
• Meets 104MHz performance offering more than 622 Mbps cell rate transfers
• Single chip solution for improved system integration
• Support cell level transfer mode
• Cell and clock rate decoupling with on chip FIFOs
• Up to 1.5 KByte of on chip FIFO per data direction
• Integrated management interface and built-in errored cell discard
• ATM Cell size programmable via external pins from 16 to 128 bytes
• Optional Utopia parity generation/checking enable/disable via external pin
• Built in JTAG port (IEEE1149 compliant)
• Simulation model available for system level verification (Contact Quicklogic for details)
• Solution also available as flexible Soft-IP core, delivered with a full device modelization
and verification testbenches
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QLUM3309-PT280C Device Data Sheet
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QLUM3309-PT280C Device Datasheet
2.0 Utopia Overview
The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by
the ATM Forum to provide a standard interface between ATM devices and ATM PHY or
SAR (segmentation and Re-assembly) devices.
Figure 1: Utopia Reference Model
The Utopia Standard defines a full duplex bus interface with a Master/Slave paradigm. The
Slave interface responds to the requests from the Master. The Master performs PHY
arbitration and initiates data transfers to and from the Slave device.
The ATM forum has standardized the Utopia Levels 1 (L1) to 3 (L3). Each level extends
the maximum supported interface speed from OC3, 155Mbps (L1) over OC12, 622Mbps
(L2) to 3.2Gbit/s (L3).
The following Table 1 gives an overview of the main differences in these three levels.
Table 1: Utopia Level Differences
Utopia Level
Interface Width
8-bit
Max. Interface Speed
25 MHz
Maximum Throughput
200 Mbps (typ. OC3 155 Mbps)
800 Mbps (typ. OC12 622 Mbps)
3.2 Gbps (typ. OC48 2.5 Gbps)
1
2
3
8-bit, 16-bit
8-bit, 32-bit
50 MHz
104 MHz
Utopia Level 1 implements an 8-bit interface running at up to 25MHz. Level 2 adds a 16
Bit interface and increases the speed to 50MHz. Level 3 extends the interface further by
a 32 Bit word-size and speeds up to 104MHz providing rates up to 3.2 Gbit/s over the
interface.
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QLUM3309-PT280C Device Datasheet
In addition to the differences in throughput, Utopia Level 2 uses a shared bus offering to
physically share a single interface bus between one master and up to 31 slave devices
(Multi-PHY or MPHY operation). This allows the implementation of aggregation units that
multiplex several slave devices to a single Master device. The Level 2 and Level 3 are point-
to-point only, whereas Level 1 has no notion of multiple slaves. Level 3 still has the notion
of multiple slaves, but they must be implemented in a single physical device connected to
the Utopia Interface.
3.0 Utopia Master/Master Bridge Application
As it is not possible to connect two Slave devices together, the Master/Master Bridge
provides the necessary interfaces to convey between two Slave devices as shown in
Figure 2.
Figure 2: Utopia Master Bridge
The Bridge automatically transfers data as soon as it becomes available from one side to
the other. Internal asynchronous FIFOs enable independent clock domains for each
interface.
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QLUM3309-PT280C Device Data Sheet
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QLUM3309-PT280C Device Datasheet
4.0 Application
Figure 3: Master/Master Bridge connecting two Slave Devices
Data flows from the Bridge's RX Ports to the corresponding TX Ports on the other side of
the bridge.
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QLUM3309-PT280C Device Datasheet
5.0 Core Pinout
Bridge Core implements all the required Utopia signals and provides all the Utopia optional
signals (Indicated by an 'O' in the following tables).
In addition to the Utopia Interface signals, error indication signals are available for error
monitoring or statistics. An error indication always shows that a cell has been discarded by
the bridge. Possible errors are parity or cell-length errors on the receive interface of the
corresponding Utopia Interfaces.
All Utopia interfaces work in the same transfer mode (cell level).
To identify the sides of the bridge, the notion "WEST" and "EAST" for the corresponding
interfaces will be used.
Figure 4: Utopia Level 3 Master/Master Bridge Top Entity
5.1 Signal Descriptions
Table 2: Global Signal
Pin
Mode
Description
reset
In
Active high chip reset
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QLUM3309-PT280C Device Datasheet
Table 3: Device Management Interface
Pin
Mode
Description
Receive error indication on west receive interface. When driven high, indicates
that an errored cell (Wrong parity or wrong length) was received from the device
connected to the west interface and is discarded.
wrx_err
Out
Out
Out
Out
Receive error status information for west receive interface. When wrx_err is
driven, indicates the error status of the discarded cell:
• wrx_err_stat(0) : When set to ‘1’ indicates that a cell is discarded because of
a parity error.
wrx_err_stat(1:0)
• wrx_err_stat(1) : When set to ‘1’ indicates that a cell is discarded because it
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia
interface within less than a complete cell time).
Receive error indication on east receive interface(s). When driven high, indicates
that an errored cell (Wrong parity or wrong length) was received from the device
connected to the east interface side.
erx_err
Receive error status information for east receive interface. When erx_err is
driven, indicates the error status of the discarded cell:
• erx_err_stat(0) : When set to ‘1’ indicates that a cell is discarded because of
a parity error.
erx_err_stat(1:0)
• erx_err_stat(1) : When set to ‘1’ indicates that a cell is discarded because it
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia
interface within less than a complete cell time).
NOTE: wrx_.. signals are sampled with west receive clock (wrxclk). erx_.. signals are sampled
with west transmit clock (wtxclk).
Table 4: West Utopia Master Transmit Interface
Pin
wtxclk
Mode
In
Description
104MHz transmit byte clock. The Core samples all Utopia Transmit signals on
txclk rising edge.
wtxdata[7:0]
Out
Transmit data bus.
Transmit data bus parity. Standard odd or non-standard even parity can be
optionally checked by the connected Slave.
When the parity check is disabled during the Core configuration, or not used in
the design, the pin txprty should be left open.
wtxprty
Out
Transmit start of cell. Asserted by the Master to indicate that the current word is
the first word of a cell.
wtxsoc
wtxenb
Out
Out
Active low transmit data transfer enable.
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space to accept one cell.
wtxclav[0]
In
In
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected during the Core configuration, one txclav signal is
implemented per PHY port. The maximum number of clav signals is limited to
four.
wtxclav[3:1] (0)
Utopia transmit address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
wtxaddr[4:0]
Out
NOTE: (O) indicates optional signals.
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QLUM3309-PT280C Device Datasheet
Table 5: West Utopia Master Receive Interface
Pin
wrxclk
Mode
In
Description
104MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk
rising edge.
wrxdata[7:0]
In
Receive data bus.
Receive data bus parity. Standard odd or non standard even parity can be
optionally generated by the Utopia Slave Core.
When the parity generation is disabled during the Core configuration, the pin
rxprty can be let unconnected.
wrxprty(0)
In
Receive start of cell. Asserted to indicate that the current word is the first word of
a cell.
wrxsoc
wrxenb
In
Out
Active low transmit data transfer enable.
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space one cell available in the FIFO.
wrxclav[0]
In
In
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected, one rxclav signal is implemented per PHY port. The
maximum number of clav signals is limited to four.
wrxclav[3:1] (0)
Utopia receive address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
wrxaddn(4:0)
Out
Table 6: East Utopia Master Transmit Interface
Pin
etxclk
Mode
In
Description
104MHz transmit byte clock. The Core samples all Utopia Transmit signals on
txclk rising edge.
etxdata[7:0]
Out
Transmit data bus.
Transmit data bus parity. Standard odd or non-standard even parity can be
optionally checked by the connected Slave.
When the parity check is disabled during the Core configuration, or not used in
the design, the pin txprty should be left open.
etxprty
Our
Transmit start of cell. Asserted by the Master to indicate that the current word is
the first word of a cell.
etxsoc
etxenb
Out
Out
Active low transmit data transfer enable.
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space to accept one cell.
etxclav[0]
In
In
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected during the Core configuration, one txclav signal is
implemented per PHY port. The maximum number of clav signals is limited to
four.
etxclav[3:1] (0)
Utopia transmit address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
etxaddr[4:0]
Out
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Table 7: East Utopia Master Receive Interface
Pin
erxclk
Mode
Description
104MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk
rising edge.
In
In
erxdata[7:0]
Receive data bus.
Receive data bus parity. Standard odd or non standard even parity can be
optionally generated by the Utopia Slave Core.
When the parity generation is disabled during the Core configuration, the pin
rxprty can be let unconnected.
erxprty (0)
In
Receive start of cell. Asserted to indicate that the current word is the first word of
a cell.
erxsoc
erxenb
In
Out
Active low transmit data transfer enable.
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space one cell available in the FIFO.
erxclav[0]
In
In
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected, one rxclav signal is implemented per PHY port. The
maximum number of clav signals is limited to four.
rxclav[3:1] (0)
Utopia receive address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
taddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
erxaddr(4:0)
Out
Table 8: Device Configuration Pins
Pin
Mode
Description
Enable parity checking on the Utopia interface.
prty_en
In
If disabled (tied to 0), the wrx_err_stat(0) signal can be ignored and left open and
the rx parity input should be tied to 0. Also the tx parity pins can be left open.
Define cellsize: sets the size in bytes of a cell. Binary value to be set usually by
board wiring.
cellsize[7:0]
In
The configuration pins are not intended for change during operation. They are usually
board wired to configure the device for operation.
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QLUM3309-PT280C Device Datasheet
6.0 Global Signal Descriptions
The externally provided Utopia Transmit and Receive clocks are connected to global
resources to provide low skew and fast chip level distribution. In both data directions, the
two corresponding Utopia Interfaces are decoupled by asynchronous FIFOs.
Therefore each interface runs completely independently each at its own tx and rx clocks
which typically are 104 MHz.
The Error indications of the two receive interfaces are always sampled within the west clock
domains. The errors of the east rx interface is available on the erx_err signal, which is
handled using the west clock domain (wtxclk). The west rx error is directly derived from the
west rx block (wrxclk).
Figure 5: Master/Master Bridge Clock Distribution
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QLUM3309-PT280C Device Datasheet
7.0 Functional Description - Utopia Interface
The Utopia Bridge operates in single PHY mode. Therefore no address bus and only a
single status pin (clav[0]) per direction is used on the interfaces.
7.1 Utopia Interface Single PHY Transmit Interface
The Transmit interface is controlled by the ATM layer.
The transmit interface has data flowing in the same direction as the ATM enable
ut_txenb. The ATM transmit block generates all output signals on the rising edge of the
ut_txclk.
Transmit data is transferred from the ATM layer to PHY layer via the following procedure.
The Core indicates it can accept data using the ut_txclav signal, then the ATM layer
drives data onto ut_txdatand asserts ut_txenb.
When a cell transfer is initiated, the Master or the Slave cannot pause the transfer by
any means.
7.1.1 Single Cell Transfer
The Slave asserts ut_txclav 1 when it is capable of accepting the transfer of a whole
cell. The Core asserts ut_txenb(Low) to indicates that it drives valid data to the Slave 2.
Together with the first word of a cell, the Core device asserts ut_txsocfor one clock
cycle 3.
To ensure that the ATM Layer (Core) does not cause transmit overrun, the Slave de-asserts
ut_txclav when ut_txsocis de-asserted by the Core 4.
To complete the cell transfer, the Core de-asserts the Utopia enable signal ut_txenb5.
Figure 6: Single Cell Transfer - Cell Level Transfer
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QLUM3309-PT280C Device Datasheet
7.1.2 Back to Back Cells Transfer
When, during a cell transfer, the Slave is able to receive a subsequent cell, the Master can
keep ut_txenbasserted between two cells 1 and asserts ut_txsoc, to start a new cell
transfer, immediately after the last word of the previous cell 2.
Figure 7: Back to Back Cell Transfer
7.2 Utopia Interface Single PHY Receive Interface
The Receive interface is controlled by the Master interface. The receive interface has data
flowing in the opposite direction to the Master's enable ut_rxenb.
Receive data is transferred from the Slave to the Master via the following procedure. The
Slave indicates it has valid data, then the Master asserts ut_rxenbto read this data from
the Slave. The Master indicates valid data (thereby controlling the data flow) via the
ut_rxclavsignal.
When a cell transfer is initiated, the transfer cannot be paused by the Master or the Slave.
7.2.1 Cell Level Transfer - Single Cell
The Slave asserts ut_rxclavwhen it is ready to send a complete cell to the Master 1.
The Master interface asserts ut_rxenbto start the cell transfer 2. The Slave samples
ut_rxenband start driving data on the following clock edge 3. The Slave asserts
ut_rxsoctogether with the cell first word to indicate the start of a cell 4.
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QLUM3309-PT280C Device Datasheet
The Master drives ut_txenbhigh two clock cycles before the expected end of the current
cell if the Slave has no more cell to transfer 5. The Slave de-asserts ut_rxclavto indicate
that no new cell is available 6 together with the start of cell indication.
Figure 8: Single Cell Transfer
7.2.2 Cell Level Transfer - Back to Back Cells
If the Master keeps ut_rxenbasserted at the end of a cell transfer 1 and if the Slave has
a new cell to send, the Slave keeps ut_rxclav drives the new cell asserting ut_rxsoc
to indicate the start of a new cell 2.
Figure 9: Back to Back Cells Transfer
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QLUM3309-PT280C Device Datasheet
8.0 Core Management and Error Handling
On Ingress, the Utopia Master Blocks are designed to handle and report Utopia errors such
as Parity error or wrong cell length. Errored cells are discarded with an error status
provided on pins for use by external management facilities.
The error handling only applies to the corresponding receive parts of the Core (i.e. Ingress
Ports).
When an errored cell is received on the Utopia interface, the Core discards the complete
cell and provides a cell discard indication (Signal eg_err asserted) 1 together with a cell
discard status (Signal eg_err_stat(1:0)) 2.
NOTE: eg_err is routed to the corresponding wrx_err and erx_err respectively
(see Figure 4).
Figure 10: Cell Discard Indication
Table 9: Error Status Word Bit Coding
Error Status Bit Name
Description
PARITY_ Valid when wrx/erx_err is asserted. If set to one indicates that a cell is discarded
ERR with a parity error decoded by the Core.
0
1
LENGTH_ Valid when wrx/erx_err is asserted. If set to one indicates that a cell is discarded
ER with a cell length error detected on the Utopia interface.
The signals are sampled on the corresponding clocks from the west interface:
• erx_... sampled with wtxclk (west transmit clock)
• wrx_... sampled with wrxclk (west receive clock)
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QLUM3309-PT280C Device Datasheet
9.0 Complexity and Performance Summary
9.1 Timing Parameters Definition
Figure 11: Tco Timing Parameter Definition
Figure 12: Tsu Timing Parameter Definition
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QLUM3309-PT280C Device Datasheet
Table 10: 8-Bit Utopia Interface Timing Characteristics
Parameter
typ
7.0
2.5
Max (worst)
Unit
ns
tco
tsu
6.0
1.8
ns
wrxclk
104
104
104
104
MHz
MHz
MHz
MHz
ns
wtxclk
erxclk
etxclk
minimum reset time
50
NOTE: timing model "worst" case is used.
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QLUM3309-PT280C Device Datasheet
10.0 Device Pinout
10.1 Signals Overview
Table 11: Signals Overview Table
Signals
Description
wrxclk, wrxclav, wrxenb*,
wrxdat, wrxsoc
West Utopia Receive Interface.
wtxclk, wtxclav, wtxenb*,
wtxdata, wtxsoc
West Utopia Transmit Interface.
wrx_err, wrx_err_stat
West Interface error indication (sampled with wrxclk).
erxclk, erxclav, erxenb*,
erxdata, erxsoc
East Utopia Receive Interface.
etxclk, etxclav, etxenb*,
etxdata, etxsoc
East Utopia Transmit Interface.
erx_err, erx_err_stat
East Interface error indication (sampled with wtxclk).
Configuration Pins to be board wired.
prty_en, cellsize
reset
Cellsize [0] should be tied to GND.
Active high device reset
GND
Ground
VCC
Device Power 2.5 V
clk(x)
unused clock inputs should be tied to GND
IOCTRL(x)
VCCIO(x)
INREF(x)
PLLRST(x)
PLLOUT(x)
VCCPLL(x)
GNDPLL(x)
TCK, TRSTB
TMS, TDI
TDO
IO Power 3.3 V
connect to GND
connect to GND or VCC
connect to GND or VCC
JTAG signals. connect to GND
JTAG signals. connect to VCC
JTAG signal. leave open
iov
nc
not connected. should be left open
*: active low signal
NOTE: Unused Pins (data busses) in the following tables are to be handled like "nc".
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QLUM3309-PT280C Device Datasheet
10.2 PT280 FPBGA Device Diagram
EAST receive error indication
QLUM3309
-PT280C
Figure 13: PT280 bottom view (0.8mm FPBGA)
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QLUM3309-PT280C Device Data Sheet
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QLUM3309-PT280C Device Datasheet
10.3 PT280 FPBGA Pinout Table
Table 12: PT280 FPBGA Pinout Table
PIN
A1
Function
pllout(3)
gndpll(0)
erx_err
erx_err_stat[0]
erx_err_stat[1]
ioctrl(f)
wtxclav[0]
wtxprty
wtxenb
wtxclk
wtxsoc
wtxdat[0]
wtxdat[1]
ioctrl(e)
wtxdat[2]
wtxdat[3]
wtxdat[4]
pllrst(1)
gnd
PIN
D1
Function
nc
PIN
G19
H1
Function
nc
PIN
N16
N17
N18
N19
P1
Function
nc
PIN
U6
Function
inref(a)
nc
A2
D2
nc
nc
nc
U7
A3
D3
nc
H2
nc
ioctrl(c)
ioctrl(c)
nc
U8
nc
A4
D4
nc
H3
nc
U9
vccio(a)
erxclk
vccio(b)
nc
A5
D5
nc
H4
nc
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
V1
A6
D6
nc (cellsize[0])
prty_en
reset
H5
vcc
vcc
vcc
nc
P2
nc
A7
D7
H15
H16
H17
H18
H19
J1
P3
ioctrl(h)
inref(h)
vcc
A8
D8
P4
nc
A9
D9
clk(8)
P5
ioctrl(b)
vccio(b)
etxdat[5]
tdo
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
E1
wrxclav[0]
wrxprty
wrxenb
inref(e)
wrxsoc
wrxdat[0]
wrxdat[1]
wrxdat[2]
wrxdat[3]
wrxdat[4]
cellsize[3]
cellsize[2]
vccio(g)
cellsize[1]
gnd
nc
P15
P16
P17
P18
P19
R1
gnd
nc
nc
nc
nc
J2
nc
wrx_err
wrx_err_stat[0]
erxdat[7]
nc
pllrst(2)
etxprty
pllout(2)
gndpll(3)
gnd
J3
vccio(g)
nc
J4
J5
gnd
vcc
nc
R2
V2
J15
J16
J17
J18
J19
K1
R3
vccio(h)
nc
V3
R4
V4
erxprty
erxenb
ioctrl(a)
nc
vccio(d)
nc
R5
gnd
V5
pllrst(0)
gnd
R6
gnd
V6
B2
E2
nc
R7
vcc
V7
B3
wtxdat[5]
wtxdat[6]
wtxdat[7]
inref(f)
nc
E3
vcc
tck
R8
vcc
V8
nc
B4
E4
K2
R9
gnd
V9
nc
B5
E5
K3
nc
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
T1
gnd
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W1
clk(1)
clk(4)
nc
B6
E6
vcc
K4
nc
vcc
B7
E7
vcc
K5
gnd
gnd
nc
vcc
B8
nc
E8
vcc
K15
K16
K17
K18
K19
L1
vcc
nc
B9
tms
E9
vcc
vcc
inref(b)
nc
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
C1
clk(6)
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
F1
gnd
nc
gnd
nc
gnd
nc
etxdat[3]
vccio(c)
etxenb
wrx_err_stat[1]
erxdat[2]
erxdat[3]
erxdat[4]
erxdat[5]
erxdat[6]
ioctrl(a)
nc
etxdat[6]
etxdat[1]
gndpll(2)
gnd
nc
vcc
trstb
nc
ioctrl(e)
nc
vcc
gnd
L2
nc
nc
gnd
L3
vccio(h)
nc
gnd
nc
wrxdat[5]
vccio(d)
inref(d)
ioctrl(d)
inref(g)
ioctrl(g)
cellsize[5]
cellsize[4]
gnd
L4
T2
W2
pllrst(3)
nc
vccpll(1)
gndpll(1)
pllout(0)
nc
L5
vcc
gnd
nc
T3
W3
L15
L16
L17
L18
L19
M1
M2
M3
M4
M5
M15
M16
M17
M18
M19
N1
T4
W4
nc
T5
W5
nc
vccio(c)
nc
T6
W6
erxclav[0]
nc
C2
vccpll(0)
nc
F2
T7
W7
C3
F3
nc
T8
nc
W8
nc
C4
nc
F4
nc
T9
nc
W9
tdi
C5
vccio(f)
ioctrl(f)
nc
F5
nc
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
U1
nc
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
etxclk
nc
C6
F15
F16
F17
F18
F19
G1
vcc
nc
clk(3)
nc
C7
ioctrl(d)
wrxdat[6]
wrxdat[7]
nc
nc
nc
C8
nc
vcc
vcc
inref(c)
nc
nc
nc
C9
vccio(f)
wrxclk
vccio(e)
nc
nc
ioctrl(b)
nc
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
nc
nc
etxdat[4]
vccpll(2)
etxsoc
etxclav[0]
erxsoc
erxdat[0]
vccpll(3)
erxdat[1]
vccio(a)
etxdat[7]
etxdat[2]
etxdat[0]
pllout(1)
G2
cellsize[7]
ioctrl(g)
cellsize[6]
vcc
nc
nc
G3
nc
nc
G4
ioctrl(h)
nc
vccio(e)
nc
G5
N2
G15
G16
G17
G18
vcc
N3
nc
U2
nc
nc
N4
nc
U3
nc
nc
N5
vcc
vcc
U4
nc
nc
N15
U5
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www.quicklogic.com
© 2001 QuickLogic Corporation
QLUM3309-PT280C Device Datasheet
11.0 References
• · ATM Forum, Utopia Level 3, af-phy-0136.000, 1999
12.0 Contact
QuickLogic Corp.
Tel
: 408 990 4000 (US)
: + 44 1932 57 9011 (Europe)
: + 49 89 930 86 170 (Germany)
: + 852 8106 9091 (Asia)
: + 81 45 470 5525 (Japan)
: info@quicklogic.com
E-mail
Internet
: www.quicklogic.com
•
•
•
•
•
•
QLUM3309-PT280C Device Data Sheet
19
QLUM3309-PT280C Device Datasheet
•
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20
www.quicklogic.com
© 2001 QuickLogic Corporation
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