QLUM3317-PQ208C [ETC]

Telecommunication IC ; 电信IC\n
QLUM3317-PQ208C
型号: QLUM3317-PQ208C
厂家: ETC    ETC
描述:

Telecommunication IC
电信IC\n

电信
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QLUM3317-PQ208C Device Data Sheet  
Utopia Level 3 Master/Master Bridge  
• • • • • •  
1.0 Utopia Level 3 (L3) Bridge Core Features  
Implements two Utopia L3 Masters providing a solution to bridge Utopia Slave devices  
Compliant with ATM-Forum af-phy-0136.000 (Utopia L3)  
Meets 104MHz performance offering up to 3.2Gbps cell rate transfers (32 bit)  
Single chip solution for improved system integration  
Support cell level transfer mode  
Cell and clock rate decoupling with on chip FIFOs  
Up to 1.5 KByte of on chip FIFO per data direction  
Integrated management interface and built-in errored cell discard  
ATM Cell size programmable via external pins from 16 to 128 bytes  
Optional Utopia parity generation/checking enable/disable via external pin  
Built in JTAG port (IEEE1149 compliant)  
Simulation model available for system level verification (Contact Quicklogic for details)  
Solution also available as flexible Soft-IP core, delivered with a full device modelization  
and verification testbenches  
QLUM3317-PQ208C Device Data Sheet  
1
QLUM3317-PQ208C Device Data Sheet  
2.0 Utopia Overview  
The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by  
the ATM Forum to provide a standard interface between ATM devices and ATM PHY or  
SAR (segmentation and Re-assembly) devices.  
Figure 1: Utopia Reference Model  
The Utopia Standard defines a full duplex bus interface with a Master/Slave paradigm. The  
Slave interface responds to the requests from the Master. The Master performs PHY  
arbitration and initiates data transfers to and from the Slave device.  
The ATM forum has standardized the Utopia Levels 1 (L1) to 3 (L3). Each level extends  
the maximum supported interface speed from OC3, 155Mbps (L1) over OC12, 622Mbps  
(L2) to 3.2Gbit/s (L3).  
The following Table 1 gives an overview of the main differences in these three levels.  
Table 1: Utopia Level Differences  
Utopia Level  
Interface Width  
8-bit  
Max. Interface Speed  
25 MHz  
Maximum Throughput  
200 Mbps (typ. OC3 155 Mbps)  
800 Mbps (typ. OC12 622 Mbps)  
3.2 Gbps (typ. OC48 2.5 Gbps)  
1
2
3
8-bit, 16-bit  
8-bit, 32-bit  
50 MHz  
104 MHz  
Utopia Level 1 implements an 8-bit interface running at up to 25MHz. Level 2 adds a 16  
Bit interface and increases the speed to 50MHz. Level 3 extends the interface further by  
a 32 Bit word-size and speeds up to 104MHz providing rates up to 3.2 Gbit/s over the  
interface.  
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QLUM3317-PQ208C Device Data Sheet  
In addition to the differences in throughput, Utopia Level 2 uses a shared bus offering to  
physically share a single interface bus between one master and up to 31 slave devices  
(Multi-PHY or MPHY operation). This allows the implementation of aggregation units that  
multiplex several slave devices to a single Master device. The Level 2 and Level 3 are point-  
to-point only, whereas Level 1 has no notion of multiple slaves. Level 3 still has the notion  
of multiple slaves, but they must be implemented in a single physical device connected to  
the Utopia Interface.  
3.0 Utopia Master/Master Bridge Application  
As it is not possible to connect two Slave devices together, the Master/Master Bridge  
provides the necessary interfaces to convey between two Slave devices as shown in  
Figure 2.  
Figure 2: Utopia Master Bridge  
The Bridge automatically transfers data as soon as it becomes available from one side to  
the other. Internal asynchronous FIFOs enable independent clock domains for each  
interface.  
QLUM3317-PQ208C Device Data Sheet  
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QLUM3317-PQ208C Device Data Sheet  
4.0 Application  
Figure 3: Master/Master Bridge connecting two Slave Devices  
Data flows from the Bridge's RX Ports to the corresponding TX Ports on the other side of  
the bridge.  
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QLUM3317-PQ208C Device Data Sheet  
5.0 Core Pinout  
Bridge Core implements all the required Utopia signals and provides all the Utopia optional  
signals (Indicated by an 'O' in the following tables).  
In addition to the Utopia Interface signals, error indication signals are available for error  
monitoring or statistics. An error indication always shows that a cell has been discarded by  
the bridge. Possible errors are parity or cell-length errors on the receive interface of the  
corresponding Utopia Interfaces.  
All Utopia interfaces work in the same transfer mode (cell level).  
To identify the sides of the bridge, the notion "WEST" and "EAST" for the corresponding  
interfaces will be used.  
Figure 4: Utopia Level 3 Master/Master Bridge Top Entity  
5.1 Signal Descriptions  
Table 2: Global Signal  
Pin  
Mode  
Description  
reset  
In  
Active high chip reset  
QLUM3317-PQ208C Device Data Sheet  
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QLUM3317-PQ208C Device Data Sheet  
Table 3: Device Management Interface  
Pin  
Mode  
Description  
Receive error indication on west receive interface. When driven high, indicates  
that an errored cell (Wrong parity or wrong length) was received from the device  
connected to the west interface and is discarded.  
wrx_err  
Out  
Receive error status information for west receive interface. When wrx_err is  
driven, indicates the error status of the discarded cell:  
• wrx_err_stat(0) : When set to ‘1’ indicates that a cell is discarded because of  
a parity error.  
wrx_err_stat(1:0)  
Out  
Out  
Out  
• wrx_err_stat(1) : When set to ‘1’ indicates that a cell is discarded because it  
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia  
interface within less than a complete cell time).  
Receive error indication on east receive interface(s). When driven high, indicates  
that an errored cell (Wrong parity or wrong length) was received from the device  
connected to the east interface side.  
erx_err(n)  
Receive error status information for east receive interface. When erx_err is  
driven, indicates the error status of the discarded cell:  
• erx_err_stat(0) : When set to ‘1’ indicates that a cell is discarded because of  
a parity error.  
erx_err_stat  
(1:0)  
• erx_err_stat(1) : When set to ‘1’ indicates that a cell is discarded because it  
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia  
interface within less than a complete cell time).  
Table 4: West Utopia Master Transmit Interface  
Pin  
wtxclk  
Mode  
In  
Description  
104MHz transmit byte clock. The Core samples all Utopia Transmit signals on  
txclk rising edge.  
wtxdata[15:0]  
wtxprty  
Out  
Out  
Transmit data bus.  
Transmit data bus parity. Standard odd or non-standard even parity can be  
optionally checked by the connected Slave.  
When the parity check is disabled during the Core configuration, or not used in  
the design, the pin txprty should be left open.  
Transmit start of cell. Asserted by the Master to indicate that the current word is  
the first word of a cell.  
wtxsoc  
wtxenb  
Out  
Out  
Active low transmit data transfer enable.  
Cell buffer available. Asserted in octet level transfers to indicate to the Master that  
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the  
Master that the PHY port FIFO has space to accept one cell.  
wtxclav[0]  
In  
In  
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status  
indication is selected during the Core configuration, one txclav signal is  
implemented per PHY port. The maximum number of clav signals is limited to  
four.  
wtxclav[3:1] (0)  
Utopia transmit address. When the Core operates in MPHY mode, address bus  
used during polling and slave port selection. Bit 4 is the MSB.  
txaddr(4:0) becomes optional (And should be left open) when the Core does not  
operate in MPHY mode.  
wtxaddr[4:0]  
Out  
NOTE: (O) indicates optional signals.  
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QLUM3317-PQ208C Device Data Sheet  
Table 5: West Utopia Master Receive Interface  
Pin  
wrxclk  
Mode  
In  
Description  
104MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk  
rising edge.  
wrxdata[15:0]  
In  
Receive data bus.  
Receive data bus parity. Standard odd or non standard even parity can be  
optionally generated by the Utopia Slave Core.  
When the parity generation is disabled during the Core configuration, the pin  
rxprty can be let unconnected.  
wrxprty(0)  
In  
Receive start of cell. Asserted to indicate that the current word is the first word of  
a cell.  
wrxsoc  
wrxenb  
In  
Out  
Active low transmit data transfer enable.  
Cell buffer available. Asserted in octet level transfers to indicate to the Master that  
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the  
Master that the PHY port FIFO has space one cell available in the FIFO.  
wrxclav[0]  
In  
In  
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status  
indication is selected, one rxclav signal is implemented per PHY port. The  
maximum number of clav signals is limited to four.  
wrxclav[3:1] (0)  
Utopia receive address. When the Core operates in MPHY mode, address bus  
used during polling and slave port selection. Bit 4 is the MSB.  
txaddr(4:0) becomes optional (And should be left open) when the Core does not  
operate in MPHY mode.  
wrxaddn(4:0)  
Out  
Table 6: East Utopia Master Transmit Interface  
Pin  
etxclk  
Mode  
In  
Description  
104MHz transmit byte clock. The Core samples all Utopia Transmit signals on  
txclk rising edge.  
etxdata[15:0]  
Out  
Transmit data bus.  
Transmit data bus parity. Standard odd or non-standard even parity can be  
optionally checked by the connected Slave.  
When the parity check is disabled during the Core configuration, or not used in  
the design, the pin txprty should be left open.  
etxprty  
Our  
Transmit start of cell. Asserted by the Master to indicate that the current word is  
the first word of a cell.  
etxsoc  
etxenb  
Out  
Out  
Active low transmit data transfer enable.  
Cell buffer available. Asserted in octet level transfers to indicate to the Master that  
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the  
Master that the PHY port FIFO has space to accept one cell.  
etxclav[0]  
In  
In  
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status  
indication is selected during the Core configuration, one txclav signal is  
implemented per PHY port. The maximum number of clav signals is limited  
to four.  
etxclav[3:1] (0)  
Utopia transmit address. When the Core operates in MPHY mode, address bus  
used during polling and slave port selection. Bit 4 is the MSB.  
txaddr(4:0) becomes optional (And should be left open) when the Core does not  
operate in MPHY mode.  
etxaddr[4:0]  
Out  
NOTE: (O) indicates optional signals.  
QLUM3317-PQ208C Device Data Sheet  
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QLUM3317-PQ208C Device Data Sheet  
Table 7: East Utopia Master Receive Interface  
Pin  
erxclk  
Mode  
In  
Description  
104MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk  
rising edge.  
erxdata[15:0]  
In  
Receive data bus.  
Receive data bus parity. Standard odd or non standard even parity can be  
optionally generated by the Utopia Slave Core.  
When the parity generation is disabled during the Core configuration, the pin  
rxprty can be let unconnected.  
erxprty (0)  
In  
Receive start of cell. Asserted to indicate that the current word is the first word of  
a cell.  
erxsoc  
erxenb  
In  
Out  
Active low transmit data transfer enable.  
Cell buffer available. Asserted in octet level transfers to indicate to the Master that  
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the  
Master that the PHY port FIFO has space one cell available in the FIFO.  
erxclav[0]  
In  
In  
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status  
indication is selected, one rxclav signal is implemented per PHY port. The  
maximum number of clav signals is limited to four.  
rxclav[3:1] (0)  
Utopia receive address. When the Core operates in MPHY mode, address bus  
used during polling and slave port selection. Bit 4 is the MSB.  
taddr(4:0) becomes optional (And should be left open) when the Core does not  
operate in MPHY mode.  
erxaddr(4:0)  
Out  
Table 8: Device Configuration Pins  
Description  
Pin  
Mode  
Enable parity checking on the Utopia interface.  
prty_en  
In  
If disabled (tied to 0), the wrx_err_stat(0) signal can be ignored and left open and  
the rx parity input should be tied to 0. Also the tx parity pins can be left open.  
Define cellsize: sets the size in bytes of a cell. Binary value to be set usually by  
board wiring.  
cellsize[7:0]  
In  
The size must be a multiple of 2.  
The configuration pins are not intended for change during operation. They are usually  
board wired to configure the device for operation.  
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QLUM3317-PQ208C Device Data Sheet  
6.0 Signal Descriptions  
The externally provided Utopia Transmit and Receive clocks are connected to global  
resources to provide low skew and fast chip level distribution. In both data directions, the  
two corresponding Utopia Interfaces are decoupled by asynchronous FIFOs.  
Therefore each interface runs completely independently each at its own tx and rx clocks  
which typically are 104 MHz.  
The Error indications of the two receive interfaces are always sampled within the west clock  
domains. The errors of the east rx interface is available on the erx_err signal, which is  
handled using the west clock domain (wtxclk). The west rx error is directly derived from the  
west rx block (wrxclk).  
Figure 5: Master/Master Bridge Clock Distribution  
QLUM3317-PQ208C Device Data Sheet  
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QLUM3317-PQ208C Device Data Sheet  
7.0 Functional Description - Utopia Interface  
The Utopia Bridge operates in single PHY mode. Therefore no address bus and only a  
single status pin (clav[0]) per direction is used on the interfaces.  
7.1 Utopia Interface Single PHY Transmit Interface  
The Transmit interface is controlled by the ATM layer.  
The transmit interface has data flowing in the same direction as the ATM enable ut_txenb.  
The ATM transmit block generates all output signals on the rising edge of the ut_txclk.  
Transmit data is transferred from the ATM layer to PHY layer via the following procedure.  
The Core indicates it can accept data using the ut_txclavsignal, then the ATM layer  
drives data onto ut_txdatand asserts ut_txenb.  
When a cell transfer is initiated, the Master or the Slave cannot pause the transfer by any  
means.  
7.1.1 Single Cell Transfer  
The Slave asserts ut_txclav1 when it is capable of accepting the transfer of a whole  
cell. The Core asserts ut_txenb(Low) to indicates that it drives valid data to the Slave 2.  
Together with the first word of a cell, the Core device asserts ut_txsocfor one clock  
cycle 3.  
To ensure that the ATM Layer (Core) does not cause transmit overrun, the Slave de-asserts  
ut_txclavwhen ut_txsocis de-asserted by the Core 4.  
To complete the cell transfer, the Core de-asserts the Utopia enable signal ut_txenb5.  
Figure 6: Single Cell Transfer - Cell Level Transfer  
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QLUM3317-PQ208C Device Data Sheet  
7.1.2 Back to Back Cells Transfer  
When, during a cell transfer, the Slave is able to receive a subsequent cell, the Core keeps  
ut_txenbasserted between two cells 1 and asserts ut_txsoc, to start a new cell  
transfer, immediately after the last word of the previous cell 2.  
Figure 7: Back to Back Cell Transfer  
7.2 Utopia Interface Single PHY Receive Interface  
The Receive interface is controlled by the Master interface. The receive interface has data  
flowing in the opposite direction to the Master's enable ut_rxenb.  
Receive data is transferred from the Slave to the Master via the following procedure. The  
Slave indicates it has valid data, then the Master asserts ut_rxenbto read this data from  
the Slave. The Master indicates valid data (thereby controlling the data flow) via the  
ut_rxclavsignal.  
When a cell transfer is initiated, the transfer cannot be paused by the Master or the Slave.  
7.2.1 Cell Level Transfer - Single Cell  
The Slave asserts ut_rxclavwhen it is ready to send a complete cell to the Master 1.  
The Master interface asserts ut_rxenbto start the cell transfer 2. The Slave samples  
ut_rxenband start driving data on the following clock edge 3. The Slave asserts  
ut_rxsoctogether with the cell first word to indicate the start of a cell 4.  
QLUM3317-PQ208C Device Data Sheet  
11  
QLUM3317-PQ208C Device Data Sheet  
The Master drives ut_txenbhigh two clock cycles before the expected end of the current  
cell if the Slave has no more cell to transfer 5. The Slave de-asserts ut_rxclavto indicate  
that no new cell is available 6 together with the start of cell indication.  
Figure 8: Single Cell Transfer  
7.2.2 Cell Level Transfer - Back to Back Cells  
If the Master keeps ut_rxenbasserted at the end of a cell transfer 1 and if the Slave has  
a new cell to send, the Slave keeps ut_rxclav drives the new cell asserting ut_rxsoc  
to indicate the start of a new cell 2.  
Figure 9: Back to Back Cells Transfer  
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QLUM3317-PQ208C Device Data Sheet  
8.0 Core Management and Error Handling  
On Ingress, the Utopia Master Blocks are designed to handle and report Utopia errors such  
as Parity error or wrong cell length. Errored cells are discarded with an error status  
provided on pins for use by external management facilities.  
The error handling only applies to the corresponding receive parts of the core  
(i.e. Ingress Ports).  
When an errored cell is received on the Utopia interface, the Core discards the complete  
cell and provides a cell discard indication (Signal eg_err asserted) 1 together with a cell  
discard status (Signal eg_err_stat(n)(m:0)) 2.  
NOTE: eg_err is routed to the corresponding wrx_err and erx_err respectively (see Figure 4).  
Figure 10: Cell Discard Indication  
Table 9: Error Status Word Bit Coding  
Error Status Bit  
Name  
Description  
Valid when wrx/erx_err is asserted. If set to one indicates that a cell is discarded  
with a parity error decoded by the Core.  
0
PARITY_ERR  
Valid when wrx/erx_err is asserted. If set to one indicates that a cell is discarded  
with a cell length error detected on the Utopia interface.  
1
LENGTH_ER  
The signals are sampled on the corresponding clocks from the west interface:  
erx_... sampled with wtxclk (west transmit clock)  
wrx_... sampled with wrxclk (west receive clock)  
QLUM3317-PQ208C Device Data Sheet  
13  
QLUM3317-PQ208C Device Data Sheet  
9.0 Complexity and Performance Summary  
9.1 Timing Parameters Definition  
Figure 11: Tco Timing Parameter Definition  
Figure 12: Tsu Timing Parameter Definition  
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QLUM3317-PQ208C Device Data Sheet  
Table 10: 16-Bit Utopia Interface Timing Characteristics  
Parameter  
tco  
typ  
7.0  
2.5  
Max  
6.0  
Unit  
ns  
tsu  
1.8  
ns  
wrxclk  
wtxclk  
erxclk  
etxclk  
104  
104  
104  
104  
MHz  
MHz  
MHz  
MHz  
minimum reset  
time  
50  
ns  
NOTE: Timing model "worst" case is used.  
QLUM3317-PQ208C Device Data Sheet  
15  
QLUM3317-PQ208C Device Data Sheet  
10.0 Device Pinout  
10.1 Signals Overview  
Table 11: Signals Overview Table  
Signals  
Description  
wrxclk, wrxclav, wrxenb*,  
West Utopia Receive Interface.  
wrxdat, wrxsoc  
wtxclk, wtxclav, wtxenb*,  
wtxdata, wtxsoc  
West Utopia Transmit Interface.  
wrx_err, wrx_err_stat  
West Interface error indication (sampled with wrxclk).  
erxclk, erxclav, erxenb*,  
erxdata, erxsoc  
East Utopia Receive Interface.  
etxclk, etxclav, etxenb*,  
etxdata, etxsoc  
East Utopia Transmit Interface.  
erx_err, erx_err_stat  
East Interface error indication (sampled with wtxclk).  
Configuration Pins to be board wired.  
prty_en, cellsize  
reset  
Cellsize [0] should be tied to GND.  
Active high device reset  
GND  
VCC  
Ground  
Device Power 2.5 V  
clk(x)  
unused clock inputs should be tied to GND  
IOCTRL(x)  
VCCIO(x)  
INREF(x)  
PLLRST(x)  
PLLOUT(x)  
VCCPLL(x)  
GNDPLL(x)  
TCK, TRSTB  
TMS, TDI  
TDO  
IO Power 3.3 V  
connect to GND  
connect to GND or VCC  
connect to GND or VCC  
JTAG signals. connect to GND  
JTAG signals. connect to VCC  
JTAG signal. leave open  
iov  
nc  
not connected. should be left open  
*: active low signal  
NOTE: Unused Pins (data busses) in the following tables are to be handled like "nc".  
16  
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QLUM3317-PQ208C Device Data Sheet  
10.2 PQ208 PQFP Device Diagram  
Figure 13: PQ208 top view  
QLUM3317-PQ208C Device Data Sheet  
17  
QLUM3317-PQ208C Device Data Sheet  
10.3 PQ208 PQFP Pinout Table  
Table 12: 208 Pin PQFP (PQ208) Pinout Table  
PIN  
1
Function  
pllrst(3)  
vccpll(3)  
gnd  
PIN  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
Function  
gnd  
PIN  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
Function  
pllrst(1)  
vccpll(1)  
etxclav[0]  
gnd  
PIN  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
Function  
gnd  
2
vccpll(2)  
pllrst(2)  
vcc  
vccpll(0)  
pllrst(0)  
gnd  
3
4
gnd  
5
wtxclav[0]  
wtxprty  
wtxenb  
vccio(a)  
wtxsoc  
wtxdat[0]  
ioctrl(a)  
vcc  
wrxprty  
gnd  
etxprty  
etxenb  
vccio(e)  
etxsoc  
erxdat[0]  
vccio(g)  
erxdat[1]  
erxdat[2]  
vcc  
6
7
wrxenb  
vccio(c)  
wrxsoc  
8
9
vcc  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
wrxdat[0]  
wrxdat[1]  
wrxdat[2]  
wrxdat[3]  
wrxdat[4]  
ioctrl(c)  
inref(c)  
etxdat[0]  
etxdat[1]  
etxdat[2]  
ioctrl(e)  
inref(e)  
ioctrl(e)  
etxdat[3]  
etxdat[4]  
vccio(e)  
gnd  
erxdat[3]  
erxdat[4]  
erxdat[5]  
ioctrl(g)  
inref(g)  
ioctrl(g)  
erxdat[6]  
erxdat[7]  
iov  
inref(a)  
ioctrl(a)  
wtxdat[1]  
wtxdat[2]  
wtxdat[3]  
wtxdat[4]  
vccio(a)  
wtxdat[5]  
gnd  
ioctrl(c)  
wrxdat[5]  
wrxdat[6]  
vccio(c)  
wrxdat[7]  
wtxdat[8]  
gnd  
vcc  
etxdat[5]  
etxdat[6]  
etxdat[7]  
clk(5)  
etxdat[8]  
vccio(g)  
gnd  
wtxdat[6]  
tdi  
etxdat[9]  
etxdat[10]  
etxdat[11]  
vcc  
wtxclk  
vcc  
etxclk  
clk(1)  
wtxdat[9]  
trstb  
vcc  
vcc  
erxclk  
wrxclk  
vcc  
vcc  
tck  
clk(3)  
wtxdat[10]  
wtxdat[11]  
wtxdat[12]  
gnd  
clk(8)  
vcc  
vcc  
tms  
etxdat[12]  
etxdat[13]  
etxdat[14]  
gnd  
clk(4)  
etxdat[8]  
etxdat[9]  
etxdat[10]  
gnd  
wtxdat[7]  
wtxdat[8]  
gnd  
vccio(d)  
wtxdat[13]  
vcc  
vccio(h)  
etxdat[15]  
cellsize[7]  
ioctrl(h)  
cellsize[6]  
inref(h)  
vcc  
vccio(b)  
wtxdat[9]  
wtxdat[10]  
wtxdat[11]  
wtxdat[12]  
ioctrl(b)  
inref(b)  
ioctrl(b)  
wtxdat[13]  
wtxdat[14]  
vccio(b)  
N/C  
vccio(f)  
etxdat[11]  
etxdat[12]  
etxdat[13]  
etxdat[14]  
etxdat[15]  
ioctrl(f)  
inref(f)  
wtxdat[14]  
wtxdat[15]  
vcc  
wrx_err  
wrx_err_stat[0]  
ioctrl(d)  
inref(d)  
ioctrl(h)  
cellsize[5]  
cellsize[4]  
cellsize[3]  
cellsize[2]  
cellsize[1]  
cellsize[0]  
vccio(h)  
gnd  
ioctrl(d)  
wrx_err_stat[1]  
erx_err  
vcc  
ioctrl(f)  
nc  
erx_err_stat[0]  
vccio(d)  
erx_err_stat[1]  
reset  
erxclav[0]  
vccio(f)  
erxprty  
erxenb  
gnd  
vcc  
nc  
wrxclav[0]  
gnd  
gnd  
prty_en  
pllout(2)  
gnd  
tdo  
pllout(0)  
gnd  
erxsoc  
pllout(3)  
gndpll(0)  
pllout(1)  
gndpll(2)  
gndpll(1)  
gndpll(3)  
18  
www.quicklogic.com  
© 2001 QuickLogic Corporation  
QLUM3317-PQ208C Device Data Sheet  
11.0 References  
· ATM Forum, Utopia Level 3, af-phy-0136.000, 1999  
12.0 Contact  
QuickLogic Corp.  
Tel  
: 408 990 4000 (US)  
: + 44 1932 57 9011 (Europe)  
: + 49 89 930 86 170 (Germany)  
: + 852 8106 9091 (Asia)  
: + 81 45 470 5525 (Japan)  
E-mail : info@quicklogic.com  
Internet : www.quicklogic.com  
QLUM3317-PQ208C Device Data Sheet  
19  
QLUM3317-PQ208C Device Data Sheet  
20  
www.quicklogic.com  
© 2001 QuickLogic Corporation  

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