AN-32 [ETC]
TOPSwitch-GX Flyback Design Methodology ; TOPSwitch-GX的反激式设计方法\n
| 型号： | AN-32 |
| 厂家： | 
ETC |
| 描述： | TOPSwitch-GX Flyback Design Methodology
|
| 文件： | 总16页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
TOPSwitch®-GX Flyback
Design Methodology
Application Note AN-32
Designing an off-line power supply involves many aspects of
electrical engineering: analog and digital circuits, bipolar and
MOS power device characteristics, magnetics, thermal
considerations, safety requirements, control loop stability, etc.
This represents an enormous challenge involving complex
trade-offs with a large number of design variables. As a result,
newoff-linepowersupplydevelopmenthasalwaysbeentedious
and time consuming even for the experts in the field. This
application note introduces a simple, yet highly efficient
methodology for the design of TOPSwitch-GX family based
off-line power supplies. For TOPSwitch-GX Flyback designs,
Power Integrations recommends the use of PI Expert which
implements this design methodology and also includes a
knowledgebaseandoptimizationfeatureformakingkeydesign
choices, further reducing design time.
and a step-by-step design procedure. The flow chart shows the
design sequence at a conceptual level for TOPSwitch-GX
flybackpowersupplydesign. Thestep-by-stepproceduregives
details within each step of the design flow chart, including
empiricaldesignguidelinesandlook-uptables.Allkeyequations
and guidelines are provided wherever possible to assist the
readers in better understanding and/or further optimization.
Basic Circuit Configuration
Because of the high level integration of TOPSwitch-GX, many
power supply design issues are resolved in the chip. Far fewer
issues are left to be addressed externally, resulting in one
common circuit configuration for all applications. Different
output power levels may require different values for some
circuit components, but the circuit configuration stays
unchanged. TOPSwitch-GX is a feature-rich product family.
Advanced features like under-voltage, overvoltage, external
ILIMIT, line feed forward, and remote ON/OFF are easily
implemented with a minimal number of external components,
but do involve additional design considerations. Please refer to
the TOPSwitch-GX data sheet for details. Other application
Introduction
The design of a switching power supply, by nature, is an
iterative process with many variables requiring adjustment to
optimize the design. The design method described in this
document consists of two major sections: A design flow chart
Output Post Filter L, C
Clamp Zener
Output Capacitor
Blocking Diode
+V
-
D
+
V
O
-
Line Sense
Resistor
+
+V
-
V
+
B
DB
-
V
AC
Bias Capacitor
C
IN
TOPSwitch-GX
L
D
S
CONTROL
C
X
F
Feedback Circuit
fS = 132 kHz if connected as shown.
For fS = 66 kHz, connect "F" Pin to "C" Pin
(fS option not available with P or G package)
External ILIMIT Resistor CONTROL Pin Capacitor
(optional)
and Series Resistor
PI-3038-091102
Figure 1. Typical TOPSwitch-GX Flyback Power Supply.
December 2002
AN-32
1. System Requirements
VACMIN, VACMAX, fL, VO, PO, η, Z
Step 1-2
Determine System Level Requirements
and Choose Feedback Circuit
2. Choose Feedback Circuit & VB
3. Determine CIN, VMIN, VMAX
4. Determine VOR, VCLO
5. Set KP
6. Determine DMAX
Step 3-11
Choose The Smallest TOPSwitch-GX
For The Required Power
7. Calculate Primary Peak Current IP
8. Calculate Primary RMS Current IRMS
9. Choose TOPSwitch-GX & fS Using AN-29
10. Set ILIMIT Reduction Factor KI
Calculate ILIMIT (min) & ILIMIT (max)
From Step 23
N
11. IP ≤ ILIMIT (min)
Y
To Step 12
PI-3039-080502
Figure 2A. TOPSwitch-GX Design Flow Chart. Step 1 to 11.
specificissuessuchasconstantcurrent,constantpoweroutputs,
etc. are beyond the scope of this application note. However,
suchrequirementsmaybesatisfiedbyaddingadditionalcircuitry
to the basic converter configuration. The only part of the circuit
configuration that may change from application to application
isthefeedbackcircuitry.Dependingonthepowersupplyoutput
specifications, one of the four feedback circuits, shown in
Figures 3, 4, 5 and 6, will be chosen for the application.
Design Flow
Figures 2A, 2B and 2C present a design flow chart showing the
complete design procedure in 37 steps. With the basic circuit
configuration shown in Figure 1 as its foundation, the logic
behind this design approach can be summarized as follows:
1. Determine system requirements and decide on feedback
circuit accordingly.
The basic circuit configuration used in TOPSwitch-GX flyback
power supplies is shown in Figure 1, which also serves as the
reference circuit for component identifications used in the
description throughout this application note.
2. Choose the smallest TOPSwitch-GX capable of the
required output power.
3. Design the smallest transformer for the TOPSwitch-GX
chosen.
4. Select all other components in Figure 1 to complete the
design.
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AN-32
From Step 11
12. Determine LP
13. Choose Core & Bobbin
Determine Ae, Le, AL, BW
Y
N
14. Set NS, L
22. NS, L Iterated
15. Calculate NP, NB
16. Calculate OD, DIA, AWG
17. Calculate BM
N
18. BM ≤ 3000
Y
19. Calculate Lg, CMA
Step 12-28
Design the Smallest Transformer
to work with the TOPSwitch-GX Chosen
N
20. Lg ≥ 0.10 mm
Y
N
21. 200 ≤ CMA ≤ 500
Y
N
23. BP ≤ 4200
To Step 10
Y
24. Calculate ISP
25. Calculate ISRMS
26. Calculate ODS, DIAS, AWGS
27. Calculate IRIPPLE
28. Calculate PIVS, PIVB
To Step 29
PI-3040-091802
Figure 2B. TOPSwitch-GX Design Flow Chart. Step 12 to 28.
B
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AN-32
From Step 28
29. Select Clamp Zener & Blocking Diode
30. Select Output Rectifier
31. Select Output Capacitor
32. Select Output Post Filter L, C
33. Select Bias Rectifier
34. Select Bias Capacitor
Step 29-37
Select Other Components
35. Select CONTROL Pin Capacitor
& Series Resistor
36. Select Feedback Circuit Compenents
According to Reference Feedback Circuits
in Figures 3, 4, 5 and 6
37. Select Bridge Rectifier
Design
Complete
PI-2584-091402
Figure 2C. TOPSwitch-GX Design Flow Chart. Step 29 to 37.
The overriding objective of this procedure is “design for cost
effectiveness.” Using smaller components usually leads to a
less expensive power supply. However, for applications with
stringent size or weight limitations, the designer may need to
strike a compromise between cost and specific design
requirementsinordertoachievetheoptimumcosteffectiveness
for the end product.
B
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4
AN-32
Step-by-Step Design Procedure
• Power supply efficiency, η: 0.8 if no better reference data
available. (Refer to AN-29)
ThisdesignprocedureusesthePIExpertdesignsoftware(available
from Power Integrations), which contains all the important
equations required for a TOPSwitch-GX flyback power supply
design,andautomatesmostcalculations.Designersare,therefore,
relievedfromthetediouscalculationsinvolvedinthecomplicated
and highly iterative design process. Look-up tables and empirical
designguidelinesareprovidedinthisprocedurewhereappropriate
to facilitate the design task.
• Loss allocation factor, Z: If Z = 1, all losses are on the
secondary side. If Z = 0, all losses are on the primary side.
Set Z = 0.5 if no better reference data is available.
Step 2. Choose feedback circuit and bias voltage VB based
on output requirements
Feedback
Circuit
VB Circuit Load* Line
(V) Tolerance Reg. Reg.
Total
Reg.
Step 1. Determine system requirements: VACMAX, VACMIN
,
fL, VO, PO, η, Z
Pri./Basic 5.8 ±10%
Pri./Enhan. 27.8 ±5%
±5% ±1.5% ±16.5%
±2.5% ±1.5% ±9%
±1% ±0.5% ±6.5%
±0.2% ±0.2% ±1.4%
• Minimum AC input voltage, VACMIN: in volts.
• Maximum AC input voltage, VACMAX: in volts.
• Recommended AC input ranges:
Opto/Zener 12
Opto/TL431 12
±5%
±1%
*Over 10% to 100% Load Range.
Table 2.
Input (VAC)
Universal
VACMIN (VAC) VACMAX (VAC)
85
265
265
• Use primary feedback for lowest cost (for low power
applications only).
230 or 115 with doubler
195
• Use Opto/Zener for low cost, good output accuracy.
• Use Opto/TL431 for best output accuracy.
• Set bias voltage VB according to Table 2.
• Choose optocoupler from Table 3.
Table 1.
• Line frequency, fL: 50 Hz or 60 Hz.
• Output voltage, VO: in Volts.
• Output power: PO: in Watts.
+
+
VO
-
VAC
CIN
Feedback Circuit
TOPSwitch-GX
15 Ω
D
S
L
CONTROL
C
X
F
CIRCUIT PERFORMANCE
Circuit Tolerance ±10%
Load Regulation ±5%
Line Regulation ±1.5%
PI-3331-112202
Figure 3. Primary/Basic Feedback Circuit.
B
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AN-32
+
+
VO
-
VAC
CIRCUIT PERFORMANCE
Circuit Tolerance ±5%
Load Regulation ±2.5%
Line Regulation ±1.5%
CIN
15 Ω
TOPSwitch-GX
1N5251D
22 V
1%
D
S
L
CONTROL
C
Feedback Circuit
X
F
100 nF
50 V
PI-3330-091102
Figure 4. Primary/Enhanced Feedback Circuit.
+
+
VO
-
VAC
∗
47 Ω
CIN
CIRCUIT PERFORMANCE
Circuit Tolerance ±5%
Load Regulation ±1%
Line Regulation ±0.5%
∗∗
470 Ω
TOPSwitch-GX
LTV817A
D
S
L
CONTROL
C
Feedback Circuit
X
F
Zener, 2%
∗
47 Ω is suitable for VO up to 7.5V. For VO > 7.5V, a higher value may be required for optimum transient response.
∗∗
470 Ω is good for Zeners with IZT = 5 mA. Lower values are needed for Zeners with higher IZT. (E.g. 150 Ω for IZT = 20 mA).
PI-3328-112202
Figure 5. Opto/Zener Feedback Circuit.
B
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AN-32
+
+
VO
-
VAC
470 Ω (VO = 12 V)
100 Ω (VO = 5 V)
CIRCUIT PERFORMANCE
Circuit Tolerance ±1%
Load Regulation ±0.2%
Line Regulation ±0.2%
CIN
UTV817A
TOPSwitch-GX
1 kΩ
D
S
L
CONTROL
C
VO - 2.5
R =
X10 kΩ
100 nF
2.5
3.3 kΩ
X
F
TL431
10 kΩ
Feedback Circuit
PI-3329-112202
Figure 6. Opto/TL431 Feedback Circuit.
Step 3. Determine minimum and maximum DC input
voltagesVMIN,VMAX andinputstoragecapacitanceCIN based
on AC input voltage and PO (Figure 7)
P/N
CTR(%) BVCEO Manufacturer
4 Pin DIP
PC123Y6
PC817X1
SFH615A-2
SFH617A-2
SFH618A-2
ISP817A
LTV817A
LTV816A
LTV123A
K1010A
6 Pin DIP
LTV702FB
LTV703FB
LTV713FA
K2010
80-160 70 V Sharp
80-160 70 V Sharp
• Choose input storage capacitor, CIN per Table 4.
63-125 70 V Vishay, Isocom
63-125 70 V Vishay, Isocom
63-125 55 V Vishay, Isocom
80-160 35 V Vishay, Isocom
80-160 35 V Liteon
80-160 80 V Liteon
80-160 70 V Liteon
60-160 60 V Cosmo
Input (VAC)
Universal
CIN (µF/Watt of PO) VMIN (V)
2 ~ 3
1
≥ 90
230 or 115 with doubler
Table 4
≥ 240
63-125 70 V Liteon
63-125 70 V Liteon
80-160 35 V Liteon
60-160 60 V Cosmo
• Set bridge rectifier conduction time, tC = 3 ms.
• Derive minimum DC input voltage VMIN
PC702V2NSZX 63-125 70 V Sharp
PC703V2NSZX 63-125 70 V Sharp
PC713V1NSZX 80-160 35 V Sharp
PC714V1NSZX 80-160 35 V Sharp
1
2 × P ×
− t
C
O
2 × f
VMIN = (2 × VA2CMIN ) −
L
η × CIN
MOC8102
MOC8103
MOC8105
CNY17F-2
73-117 30 V Vishay, Isocom
where units are volts, watts, Hz, seconds and farads
108-173 30 V Vishay, Isocom
63-133 30 V Vishay, Isocom
63-125 70 V Vishay, Isocom,
Liteon
• Calculate maximum DC input voltage VMAX
:
VMAX = 2 × VACMAX
Table 3. Optocoupler
B
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AN-32
Step 4. Determine reflected output voltage VOR and clamp
Zener voltage VCLO (Figure 8)
TOPSwitch-GX when and only when current limit is set
externally with current limit reduction as a function of line
voltage. Compared to Zener clamps, designs using RCD
clamps usually have lower efficiency at light load. In
addition, great care must be taken in RCD clamp design.
Because of its inherent variation in clamp voltage across
load range, if not designed properly, an RCD clamp may
fail to protect TOPSwitch-GX, especially under startup or
output overload conditions.
• Set reflected output voltage, VOR = 100 V for multiple
output, 120 V for single output. These values optimize
cross-regulation and efficiency. To obtain the maximum
output power from a given TOPSwitch-GX device, set
VOR = 135 V.
• RCD (Resistor/Capacitor/Diode) clamp may be used with
VACMIN × 2
V+
VMIN
t
C
P = Output Power
O
f
t
= Line Frequency
(50 or 60 Hz)
L
= Conduction Angle
Use 3 ms if unknown
C
η = Efficiency
PI-2585-012500
Figure 7. Input Voltage Waveform.
BV
700 V
DSS
Margin = 53 V (95 V)
647 V (605 V)
627 V (585 V)
Blocking Diode Forward Recovery = 20 V
555 V (525 V)
495 V (475 V)
V
V
CLM
CLO
V
= 120 V (100 V)
OR
V
MAX
375 V
V
= 1.5 x V
= 1.4 x V
= 180 V (150 V)
CLO
CLM
OR
V
= 252 V (210 V)
CLO
0 V
0 V
Universal/230 VAC Input
Use V
= 120 V (100 V) and 180 V (150 V) Zener Clamp
For Single (Multiple) Output
OR
PI-3336-091402
Figure 8. Reflected Voltage VOR and Clamp Zener Voltage VCLO
.
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AN-32
Step 5. Set current waveform parameter KP for desired
mode of operation and current waveform: KP ≡ KRP for KP
≤ 1.0 and KP ≡ KDP for KP ≥ 1.0 (Figures 9 and 10)
IR
IP
KP ≡ KRP =
• For KP ≤ 1.0, KP ≡ KRP, continuous mode (see Figure 9)
I
R
Primary
I
IR
P
KP ≡ KRP
=
where IR is primary ripple current and IP
IP
is primary peak current.
• For KP ≥ 1.0, KP ≡ KDP, discontinuous mode (see Figure 10)
(a) Continuous, K < 1
P
VOR × (1−DMAX
)
KP ≡ KDP
=
I
I
P
Primary
R
(VMIN −VDS ) × DMAX
• For continuous mode design, set
KP = 0.4 for universal input
(b) Borderline Continuous/Discontinuous, K = 1
P
0.6 for 230 VAC or 115 VAC with doubler.
PI-2587-011400
• For discontinuous mode design, set KP = 1.0.
• KP must be kept within the range specified in Table 5.
Figure 9. Continuous Mode Current Waveform, KP ≤1.
(1-D) x T
=
KP ≡ KDP
t
T = 1/fS
Primary
D x T
(1-D) x T
t
Secondary
(a) Discontinuous, K > 1
P
T = 1/fS
Primary
D x T
(1-D) x T = t
Secondary
(b) Boarderline Discontinuous/Continuous, K = 1
P
PI-2578-011800
Figure 10. Discontinuous Mode Current Waveform, KP ≥1.
B
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AN-32
Step 9. Choose TOPSwitch-GXbased on AC input voltage,
VO, PO and η using AN-29 selection curves
KP
Input (VAC)
Continuous
Mode
Discontinuous
Mode
• ChoosethesmallestTOPSwitch-GXusingTOPSwitch-GX
Selection Curves in AN-29.
• Identify appropriate selection curves according to AC
input voltage and output voltage, VO.
• Continuous mode: Use selection curves as is.
• Discontinuous mode: Use selection curves with the output
power derated by 33%. This effectively makes a 10 W
discontinuous design equivalent to a 15 W continuous
design in TOPSwitch-GX selection.
Universal
230
0.4~1.0
0.6~1.0
≥1.0
≥1.0
Table 5
Step 6. Determine DMAX based on VMIN and VOR
• Switching Frequency fS: For DIP and SMP packages, set
fS = 132 kHz. For TO-220 package, choose between
66 kHz and 132 kHz.
• Continuous mode
VOR
DMAX
=
(VMIN − VDS ) + VOR
Step 10. Set ILIMIT reduction factor KI for External ILIMIT
• Discontinuous mode
external ILIMIT
•
where 0.3 ≤ KI ≤ 1.0
KI =
default ILIMIT
VOR
DMAX
=
• KI is set by the value of the resistor connected between M
pinandSOURCEpin(RefertoTOPSwitch-GXdatasheet).
• For applications demanding very high efficiency, a
TOPSwitch-GX bigger than necessary may be used by
lowering ILIMIT externally to take advantage of the lower
KP × (VMIN − VDS ) + VOR
• Set TOPSwitch-GX Drain to Source voltage, VDS = 10 V.
Step 7. Calculate primary peak current IP
• Continuous mode (KP ≤ 1.0)
RDS(ON)
.
• If no special requirement, set KI = 1.0.
• Calculate ILIMIT(min) and ILIMIT(max)
IAVG
IP =
ILIMIT(min) = default ⋅ILIMIT(min) ×KI
ILIMIT(max) = default ⋅ILIMIT(max) ×KI
K
P
1−
× DMAX
2
• Discontinuous mode (KP ≥ 1.0)
Step 11. Validate TOPSwitch-GX selection by checking IP
2 ×IAVG
IP =
against ILIMIT(min)
DMAX
• For KI = 1.0, check IP ≤ 0.96 x ILIMIT(min).
• For KI < 1.0, check IP ≤ 0.94 x ILIMIT(min).
• Choose larger TOPSwitch-GX if necessary.
PO
• Input average current
IAVG
=
η ×VMIN
Step 12. Calculate primary inductance LP
Step 8. Calculate primary RMS current IRMS
• Continuous mode
• Continuous mode
106 ×PO
Z × (1− η) + η
2
KP
LP =
×
2
K
IRMS = IP × DMAX
×
−KP+1
P
η
IP × KP × 1−
× fS (min)
3
2
where units are µH, watts, amps and Hz
• Discontinuous mode
IP2
• Discontinuous mode.
106 × PO
Z × (1− η) + η
IRMS = DMAX
×
3
LP =
×
2
1
η
IP × × fS (min)
2
where units are µH, watts, amps and Hz
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AN-32
• Z is loss allocation factor and η is efficiency from Step 1.
Step 14. Set value for number of primary layers L and
number of secondary turns NS (may need iteration)
Step 13. Choose core and bobbin based on fS and PO using
Table 6 and determine Ae, Le, AL and BW from core and
bobbin catalog
• Starting with L = 2 (Keep 1.0 ≤ L ≤ 2.0 throughout
iteration).
• Starting with NS = 0.6 turn/volt.
• Both L and NS may need iteration.
• Core effective cross-sectional area, Ae: in cm2.
• Core effective path length, Le: in cm.
• Core ungapped effective inductance, AL: in nH/turn2.
• Bobbin width, BW: in mm.
Step 15. Calculatenumberof primaryturnsNP andnumber
of bias turns NB
• Choose core and bobbin based on fS, PO and construction
type.
• Diode forward voltages: 0.7 V for ultra-fast P/N diode and
0.5 V for Schottky diode.
• Set output rectifier forward voltage, VD.
• Set bias rectifier forward voltage, VDB.
• Calculate number of primary turns.
66 kHz
Triple
Insulated
Wire
132 kHz
Triple
Insulated
Wire
Output
Power
Margin
Wound
Margin
Wound
VOR
NP = NS ×
EF12.6
EE13
EF16
EE16
EE19
EI22
EI22
EE19
EI22/19/6 EF16
EEL16
EF20
EI25
EF12.6
EE13
EI22
EE19
E122/19/6
EEL16
VO + VD
• Calculate number of bias turns NB.
EE16
0-10 W
VB + VDB
NB = NS ×
EI22/19/6 EEL19
VO + VD
EF20
EI28
EEL22
EE19
EI22
EF20
EI25
10 W-
20 W
Step 16. DetermineprimarywindingwireparametersOD,
DIA, AWG
EF25 EI22/19/6 EEL19
EF20
EF25
EI30
EPC30
EEL25
E30/15/7
EER28
E128
• Primary wire outside diameter in mm.
20 W-
30 W
L × (BW − 2 × M)
EI28
EI30
EF25
EEL22
EF25
EI30
OD =
NP
E30/15/7 ETD29
EER28
30 W-
50 W
where L is number of primary layers,
BW is bobbin width in mm,
M is safety margin in mm.
EI35
EI33/29/
13-Z
EER28L
EF32
EPC30
ETD29
EI35
EF32
EI28
EI30
EEL25
E30/15/7
EER28
ETD29
EI35
EI33/29/
13-Z
EER28L
EF32
ETD34
EI40
• Determine primary wire bare conductor diameter DIA and
primary wire gauge AWG.
50 W-
70 W
ETD34
ETD34
EI40
Step 17 to Step 22. Check BM, CMA and Lg. Iterate if
necessary by changing L, NS or core/bobbin until within
specified range
E36/18/11 E36/18/11 E30/15/7
EI40
EER35
EER28
ETD29
70 W-
100 W
• Set safety margin, M. Use 3 mm (118 mils) for margin
wound and zero for triple insulated secondary.
• Maximum flux density: 3000 ≥ BM ≥ 2000, in gauss or
0.3 ≥ BM ≥ 0.2, in tesla.
ETD39
EER40
ETD39
EER40
EI35
EF32
100 W-
150 W
E42/21/15 ETD34 E36/18/11
EER35
E42/21/15 E42/21/20 E36/18/11 ETD39
E42/21/20 E55/28/21 EI40 EER40
100 × IP ×LP
BM =
E55/28/21
ETD39 E42/21/15
EER40 E42/21/20
E42/21/15 E55/28/21
E42/21/20
NP ×Ae
>150W
where units are gauss, amps, µH and cm2
E55/28/21
Table 6. Transformer Core.
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AN-32
• Gap length in mm: Lg ≥ 0.1
Step 26. Determine secondary winding wire parameters
ODS, DIAS, AWGS
NP2
1
• Secondary wire outside diameter in mm
Lg= 40 × π ×Ae ×
−
1000 × L
A
L
P
BW − (2 × M)
where Lg in mm, Ae in cm2, AL in nH/turn2 and
ODS =
NS
LP in µH
• Secondary wire bare conductor diameter in mm
• Primary winding current capacity in circular mils per amp:
500 ≥ CMA ≥ 200
4 × CMAS × ISRMS 25.4
DIAS =
×
1.27 × DIA2 ×
π
1.27 × π
1000
2
1000
25.4
4
CMA =
×
where CMAS is secondary winding current capacity
in circular mils per amp. Minimum wire diameter is
calculated by using a CMAS of 200.
IRMS
where DIA is the bare conductor diameter in mm
• Iterate by changing L, NS, core/bobbin according to Table 7.
• Determine secondary winding wire gauge AWGS based on
DIAS. If the bare conductor diameter of the wire is larger
than that of the 27 AWG for 132 kHz or 25 AWG for
66kHz,aparallelwindingusingmultiplestrandsofthinner
wire should be used to minimize skin effect.
BM
-
Lg
-
CMA
L
↑
↑
↑
↑
↑
↑
NS
↑
↑
Step 27. Determine output capacitor ripple current IRIPPLE
core
size
↑
↑
• Output capacitor ripple current
IRIPPLE = IS2RMS − IO2
Table 7.
Step 23. Check BP ≤ 4200 . If necessary, reduce current
where IO is the output DC current
limit by lowering ILIMIT reduction factor KI
Step 28. Determine maximum peak inverse voltages PIVS,
PIVB for secondary and bias windings
ILIMIT(max)
•
BP =
× BM
IP
• Secondary winding maximum peak inverse voltage.
• Check BP ≤ 4200 gauss (0.42 tesla) to avoid transformer
saturation at startup and output over load.
• Decrease KI, if necessary, until BP ≤ 4200.
NS
PIV = VO + (VMAX
×
)
S
NP
• Bias winding maximum peak inverse voltage.
Step 24. Calculate secondary peak current ISP
NB
NP
PIVB = VB + (VMAX
×
)
•
ISP= IP ×
NP
NS
Step 29. Select clamp Zener and blocking diode per Table 8
for primary clamping based on VOR and the type of output
Step 25. Calculate secondary RMS current ISRMS
Blocking
Diode
BYV26C
MUR160 P6KE150
UF4005
Clamp
Zener
• Continuous mode
PS Output
VOR
2
KP
ISRMS = ISP × 1− D
×
− KP +1
(
)
MAX
Multiple Output 100 V
3
BYV26C
• Discontinuous mode
MUR160 P6KE180
UF4005
Single Output
120 V
1−DMAX
3 ×KP
ISRMS = ISP ×
Table 8.
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AN-32
Step 30. Select output rectifier per Table 9
Step 31. Select output capacitor
• VR ≥ 1.25 xPIVS; where PIVS is from Step 28 and VR is the
rated reverse voltage of the rectifier diode.
• ID ≥ 3 x IO; where ID is the diode rated DC current and
IO = PO / VO.
• Ripple current specification at 105 °C, 100 kHz: Must be
equal to or larger than IRIPPLE, where IRIPPLE is from Step 27.
• ESR specification: Use low ESR, electrolytic capacitor.
Output switching ripple voltage is ISP x ESR , where ISP is
from Step 24.
Rec. Diode VR(V) ID(A) Package Manufacturer
• Examples:
Schottky
1N5819
SB140
Output
Output Capacitor
40
40
60
60
60
40
40
40
60
60
40
60
45
1
1
1
1
1.1
3
3
3
3
3
Axial General Semi
Axial General Semi
Axial General Semi
Axial IR
5 V to 24 V, 1 A 330 µF, 35 V, low ESR, electrolytic
SB160
MBR160
11DQ06
1N5822
SB340
MBR340
SB360
MBR360
SB540
SB560
UnitedChemicon
Axial IR
LXZ35VB331M10X16LL
Rubycon 35YXG330M10x16
Panasonic EEUFC1V331
Axial General Semi
Axial General Semi
Axial IR
Axial General Semi
Axial IR
Axial General Semi
Axial General Semi
TO-220 General Semi
IR
5 V to 24 V, 2 A 1000 µF, 35 V, low ESR, electrolytic
United Chemicon
5
5
7.5
LXZ35VB102M12X25LL
Rubycon 35YXG1000M12.5x25
Panasonic EEUFC1V102
MBR745
MBR760
MBR1045
60
45
7.5
10
TO-220 General Semi
TO-220 General Semi
IR
TO-220 General Semi
TO-220 General Semi
TO-220 General Semi
IR
Step 32.
Select output post filter L, C
• Inductor L: 2.2 µH to 4.7 µH. Use ferrite bead for low
current (≤1A) output and standard off-the-shelf choke for
highercurrentoutput. Increasechokecurrentratingorwire
size, if necessary, to avoid significant DC voltage drop.
• Capacitor C:100 µF to 330 µF, 35 V, electrolytic
MBR1060
MBR10100
MBR1645
60
100
45
10
10
16
MBR1660
60
16
TO-220 General Semi
Examples for 100 µF, 35 V, electrolytic:
MBR2045CT 45 20(2x10) TO-220 General Semi
United Chemicon KMG35VB101M6X11LL
Rubycon 35YXA100M6.3x11
IR
MBR2060CT 60 20(2x10) TO-220 General Semi
Panasonic ECA1VHG101
MBR20100
100 20(2x10) TO-220 General Semi
IR
Step 33. Select bias rectifier from Table 10
UFR
UF4002
UF4003
MUR120
EGP20D
100
200
200
200
1
1
1
2
2
Axial General Semi
Axial General Semi
Axial General Semi
Axial General Semi
Axial General Semi
Philips
Axial General Semi
Axial General Semi
Axial General Semi
Axial General Semi
Philips
TO-220 General Semi
TO-220 General Semi
Philips
TO-220 General Semi
Philips
• VR ≥ 1.25 xPIVB; where PIVB is from Step 28 and VR is the
rated reverse voltage of the rectifier diode.
Rectifier
VR (V)
Manufacturer
BYV27-200 200
BAV21
UF4003
1N4148
200
200
75
Philips
General Semi
Motorola
UF5401
UF5402
EGP30D
100
200
200
3
3
3
Table 10.
BYV28-200 200
3.5
Step 34. Select bias capacitor
MUR420 200
4
8
BYW29-200 200
BYV32-200 200
• Use 0.1 µF, 50 V, ceramic.
18
Step 35. SelectCONTROLpincapacitorandseriesresistor
• CONTROLpincapacitor:47µF,10V,lowcostelectrolytic
Table 9.
(Do not use low ESR capacitor).
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AN-32
• Series resistor: 6.8 Ω, 1/4 W (Not needed if KP ≥ 1, i.e.
discontinuous mode).
Step 36. Select feedback circuit components according to
applicable reference feedback circuits shown in Figures 3,
4, 5 and 6
• Applicable reference circuit: Identified in Step 2.
Step 37. Select input bridge rectifier
2
• VR ≥ 1.25 x
x VACMAX; where VACMAX is from Step 1.
• ID ≥ 2 x IAVE; where ID is the bridge rectifier rated current
and IAVE is average input current.
P
OUT
I
=
Note:
;
AVE
VMIN × η
where VMIN is from Step 3 and η from Step 1.
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AN-32
Customization of secondary designs for each output
The turns for each secondary winding are calculated based on
the respective output voltage VO(n):
Appendix A
Multiple Output Flyback Power
Supply Design
VO(n) + VD(n)
NS(n) = NS ×
The only difference between a multiple output flyback power
supply and a single output flyback power supply of the same
total output power is in the secondary side design. Instead of
delivering all power to one output as in the single output case,
a multiple output flyback distributes its output power among
severaloutputs.Therefore,thedesignprocedurefortheprimary
side stays the same, while that for the secondary side demands
further considerations.
V + VD
Output rectifier maximum inverse voltage is
NS (n)
PIV (n) = VMAX
×
+ VO(n)
S
NP
With output RMS current ISRMS(n), secondary number of turns
NS(n) and output rectifier maximum inverse voltage PIVS(n)
known, the secondary side design for each output can now be
carried out exactly the same way as for the single output design.
Design with lumped output power
One simple way of doing multiple output flyback design is
described in detail in AN-22, “Designing Multiple Output
FlybackPowerSupplieswithTOPSwitch”. Thedesignmethod
starts with a single output equivalent by lumping output power
ofalloutputstoonemainoutput.SecondarypeakcurrentISP and
RMS current ISRMS are derived. Output average current IO
corresponding to the lumped power is also calculated.
Secondary winding wire size
TheTOPSwitch-GXdesignspreadsheetassumesaCMAof200
whencalculatingsecondarywindingwirediameters.Thisgives
the minimum wire sizes required for the RMS currents of each
output using seperate windings. Designers may wish to use
larger size wire for better thermal performance. Other
considerations such as skin effect and bobbin coverage may
suggest the use of a smaller wire by using multiple strands
wound in parallel. In addition, practical considerations in
transformer manufacturing may also dictate the wire size.
Assumption for simplification
The current waveforms in the individual output windings are
determinedbytheimpedanceineachcircuit,whichisafunction
of leakage inductance, rectifier characteristics, capacitor value
and most importantly, output load. Although this current
waveform may not be exactly the same from output to output,
it is reasonable to assume that, to the first order, all output
currents have the same shape as for the single output equivalent
of lumped power.
Output RMS current vs. average current
The output average current is always equal to the DC load
current, while the RMS value is determined by current wave
shape. Since the current wave shapes are assumed to be the
sameforalloutputs, theirratioofRMStoaveragecurrentsmust
also be identical. Therefore, with the output average current
known, the RMS current for each output winding can be
calculated as
ISRMS
ISRMS(n) =IO(n) ×
IO
where ISRMS(n) and IO(n) are the secondary RMS current and
output average current of the nth output and ISRMS and IO are the
secondary RMS current and output average current for the
lumped single output equivalent design.
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AN-32
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Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it
convey any license under its patent rights or the rights of others.
The products and applications illustrated herein may be covered by one or more U.S. and foreign patents or potentially by
pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents
may be found at www.powerint.com.
The PI Logo, TOPSwitch, TinySwitch, LinkSwitch and EcoSmart are registered trademarks of Power
Integrations, Inc. PI Expert is a trademark of Power Integrations, Inc. ©Copyright 2002, Power Integrations, Inc.
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