AN-4003 [FAIRCHILD]
PC POWER SUPPLY DESIGN WITH KA3511; 与KA3511 PC电源的设计
| 型号： | AN-4003 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | PC POWER SUPPLY DESIGN WITH KA3511 |
| 文件： | 总28页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2,1999
AN4003
PC POWER SUPPLY DESIGN WITH KA3511
Sang-Tae Im
1. GENERAL DESCRIPTION
The KA3511 is a fixed-frequency improved-performance pulse-width modulation control circuit with
complete housekeeping circuitry for use in the secondary side of SMPS (Switched mode power
supply). It contains various functions, which are precision voltage reference, over voltage protec-
tion, under voltage protection, remote on/off control, power good signal generator and etc.
OVP (Over voltage protection) section
It has OVP functions for +3.3V,+5V,+12V and PT outputs. The circuit is made up of a comparator
with four detecting inputs and without hysteresis voltage. Especially, PT (Pin16) is prepared for an
extra OVP input or another protection signal.
UVP (Under voltage protection) section
It also has UVP functions for +3.3V, +5V, +12V outputs. The block is made up of a comparator with
three detecting inputs and without hysteresis voltage.
Remote on/off section
Remote on/off section is used to control SMPS externally. If a high signal is supplied to the remote
on/off input, PWM signal becomes a high state and all secondary outputs are grounded. The
remote on/off signal is transferred with some on-delay and off-delay time of 8ms, 24ms respec-
tively.
Precision reference section
±
The reference voltage trimmed to 2% (4.9V<Vref<5.1V)
PG (Power good signal generator) section
Power good signal generator is to monitor the voltage level of power supply for safe operation of a
microprocessor.
KA3511 requires few external components to accomplish a complete housekeeping circuits for
SMPS. The KA3511 is available in a 22-pin dual in-line package.
Rev C, November 1999
1
ORDERING INFORMATION
22-DIP-400
Device
Package
Operating Temperature
° °
-25 C ~ 85 C
KA3511
22 DIP
FEATURES
• Complete PWM control and house keeping circuitry
• Few external components
• Precision voltage reference trimmed to 2%
• Dual output for push-pull operation
• Each output TR for 200mA sink current
• Variable duty cycle by dead time control
• Soft start capability by using dead time control
• Double pulse suppression logic
• Over voltage protection for 3.3V / 5V / 12V
• Under voltage protection for 3.3V / 5V / 12V
• One more external input for various protection (PT)
• Remote on/off control function (PS-ON)
• Latch function controlled by remote and protection input
• Power good signal generator with hysteresis
• 22-Pin dual in-line package
2. BLOCK DIAGRAM
22 C1
R
T
7
8
D
Q
Q
OSCILLATOR
C
T
PWM
CONTROL
C2
E
20
CK
COMP
2
21
5
V5
V12
DELAY
CONTROLLER
DEAD TIME
CONTROLLER
R
S
REMOTE ON/OFF
1.4V
T
REM
E/A(-)
E/A(+)
3
4
Q
6
REM
(PS-ON)
1.25V
0.1V
DEAD TIME
CONTROL
11
PG
19
5V
16
15
14
PT
INTERNAL
BIAS
V12
12
1
VREF
V5
VREF
VREF
VREF
OVP
13 V3.3
Start Up
PG
COMP
V
CC
GENERATOR
Ichag
COMP1
COMP2
1.25V
5V
COMP3
DET
9
1.8V 0.6V
0.6V
1.8V
1.25V
UVP
COMP
1.25V
10
17
18
T
T
GND
PG
UVP
2.2uF
2.2uF
Rev C, November 1999
2
3. PIN DESCRIPTION
C1
E
C2
DTC
GND
TUVP
PT
V12
V5
V3.3
Vref
#22
#12
KA3511
#1
#11
VCC
COMPE/A(-)
EA(+)
TREM
REM
RT
CT
DET
GTP G P
Pin
No. Name I/O
Pin
Function
Supply voltage
No. Name I/O
Function
1
2
VCC
COMP
E/A(-)
E/A(+)
TREM
REM
RT
I
O
I
12
13
14
15
16
17
Vref
V3.3
V5
O
I
Precision reference VTG
OVP, UVP input for 3.3V
OVP, UVP input for 5V
OVP, UVP input for 12V
Extra protection input
UVP delay
E/A output
3
E/A (-) input
I
4
I
E/A (+) input
V12
PT
I
5
–
I
Remote on/off delay
Remote on/off input
I
6
TUVP
GND
DTC
C2
–
–
I
7
–
–
I
Oscillation freq. setting R 18
Oscillation freq. setting C 19
Signal ground
8
CT
Deadtime control input
Output 2
9
DET
TPG
Detect input
PG delay
20
21
O
–
O
10
11
–
O
E
Power ground
PG
Power good signal output 22
C1
Output 1
Rev C, November 1999
3
Pin
No. Name
Function
Supply voltage. Operating range is 14V~30V. VCC =20V, Ta=25 C at test.
°
1
2
VCC
COMP Error amplifier output. It is connected to non-inverting input of pulse width
modulator comparator.
3
4
E/A(-) Error amplifier inverting input. Its reference voltage is always 1.25V.
E/A(+) Error amplifier non-inverting input feedback voltage.This pin may be used to
sense power supply output voltage.
5
6
TREM Remote on/off delay. Ton/Toff=8ms/24ms (Typ.) with C=0.1µF. Its high/low
threshold voltage is 1.8V/0.6V.
REM
Remote on/off input. It is TTL operation and its threshold voltage is 1.4V. Voltage
at this pin can reach normal 4.6V, with absolutely maximum voltage, 5.25V. If
REM = “Low”, PWM = “Low”. That means the main SMPS is operational. When
REM = “High”, then PWM = “High” and the main SMPS is turned-off.
Ω
7
8
RT
CT
Oscillation frequency setting R. (Test Condition RT=10k )
Oscillation frequency setting C. (Test Condition CT=0.01µF)
Under-voltage detect pin. Its threshold voltage is 1.25V Typ.
9
DET
TPG
10
PG delay. Td=250ms (Typ) with CPG=2.2µF. The high/low threshold voltage are
1.8V/0.6V and the voltage of Pin10 is clamped at 2.9V for noise margin.
11
PG
Power good output signal. PG = “High” means that the power is “Good” for
operation and PG = “Low” means “Power fail”.
12
13
14
15
16
Vref
V3.3
V5
Precision voltage reference trimmed to 2%. (Typical Value = 5.03V)
Over voltage protection for output 3.3V. (Typical Value = 4.1V)
Over voltage protection for output 5V. (Typical Value = 6.2V)
Over voltage protection for output 12V. (Typical Value = 14.2V)
V12
PT
This is prepared for an extra OVP input or another protection signal. (Typical
Value = 1.25V)
17
TUVP
Timing pin for under voltage protection blank-out time. Its threshold voltage is
1.8V and clamped at 2.9V after full charging. Target of delay time is 250ms and
it is realized through external (C=2.2µF).
18
19
GND
DTC
Signal ground.
Deadtime control input. The dead-time control comparator has an effective
120mV input offset which limits the minimum output dead time. Dead time may
be imposed on the output by setting the dead time control input to a fixed
voltage, ranging between 0V to 3.3V.
20
21
22
C2
E
Output drive pin for push-pull operation.
Power ground.
C1
Output drive pin for push-pull operation.
Rev C, November 1999
4
4. ABSOLUTE MAXIMUM RATINGS
Characteristic
Supply voltage
Symbol
Value
40
Unit
V
VCC
Collector output voltage
Collector output current
Power dissipation
V
C1, VC2
40
V
IC1, IC2
PD
200
mA
W
1
Operating temperature
Storage temperature
TOPR
TSTG
-25 to 85
-65 to 150
°C
°C
TEMPERATURE CHARACTERISTICS
Value
Typ.
0.01
Characteristic
Symbol Min.
Max.
Unit
∆
∆
Temperature coefficient of Vref (-25 °C<Ta<85°C)
Vref/ T
–
–
%/°C
Rev C, November 1999
5
5. ELECTRICAL CHARACTERISTICS
(V =20V, T =25°C)
CC
A
Value
Characteristic
REFERENCE SECTION
Reference output voltage
Line regulation
Symbol
Test Condition
Min. Typ. Max. Unit
Vref
Iref=1mA
4.9
–
5
5.1
25
15
–
V
∆
Vref.LINE 14V<VCC<30V
2.0
1.0
0.01
35
mV
∆
Load regulation
Vref.LOAD 1mA<Iref<10mA
–
mV
Temperature coefficient of Vref(1)
Short-circuit output current
OSCILLATOR SECTION
Oscillation frequency
Vref/ T
-25°C<Ta<85°C
Vref=0
–
%/°C
mA
∆
∆
ISC
15
75
fosc
CT=0.01µF, RT=12k
CT=0.01µF, RT=12k
–
–
10
2
–
–
kHz
%
Frequency change with
temperature(1)
fosc/T
DEAD TIME CONTROL SECTION
Input bias current
IB(DT)
–
45
–
-2.0 -10
µA
%
V
Maximum duty voltage
Input threshold voltage
DCMAX
VTH(DT)
Pin19 (DTC)=0V
Zero Duty Cycle
Max. Duty Cycle
48
3.0
–
50
3.3
–
0
ERROR AMP SECTION
Inverting reference voltage
Input bias current
Open-loop voltage gain(1)
Unit-gain bandwidth(1)
Output sink current
Vref(EA)
IB(EA)
GVO
1.20 1.25 1.30
%
VCOMP=2.5V
–
70
–
-0.1 -1.0 µA
0.5V<VCOMP<3.5V
95
650
0.9
–
–
–
–
dB
kHz
mA
mA
BW
ISINK
VCOMP=0.7V
VCOMP=3.5V
0.3
Output source current
PWM COMPARATOR SECTION
Input threshold voltage
OUTPUT SECTION
ISOURCE
-2.0 -4.0
VTH(PWM) Zero Duty Cycle
–
4
4.5
V
V
Output saturation voltage
Collector off-state current
Rising time
VCE(SAT)
IC(off)
TR
IC=200mA
–
–
–
–
1.1 1.3
VCC=VC=30V, VE=0V
2
100 µA
100 200
50 200
ns
ns
Falling time
TF
PROTECTION SECTION
Over voltage protection for 3.3V
VOVP1
3.8
4.1 4.3
V
Rev C, November 1999
6
ELECTRICAL CHARACTERISTICS
5.
(continued)
Value
Characteristic
Symbol
VOVP2
VOVP3
VPT
Test Condition
Min. Typ. Max. Unit
Over voltage protection for 5V
Over voltage protection for 12V
Input threshold voltage for PT
Under voltage protection for 3.3V
Under voltage protection for 5V
Under voltage protection for 12V
Charging current for UVP delay
UVP Delay Time
–
–
–
–
–
–
5.8 6.2 6.6
13.5 14.2 15.0
1.20 1.25 1.30
2.1 2.3 2.5
3.7 4.0 4.3
V
V
VUVP1
VUVP2
VUVP3
ICHG.UVP
TD.UVP
V
V
9.2
10 10.8
V
C=2.2µF, VTH =1.8V -10 -15 -23
uA
C=2.2µF
100 260 500 ms
REMOTE ON/OFF SECTION
REM on input voltage
VREMH
VREML
IREML
IREM = -200µA
–
2.0
–
–
–
–
V
V
REM off input voltage
0.8
REM off input bias voltage
REM on open voltage
VREM =0.4V
–
–
–
-1.6 mA
VREM(OPEN)
Ton
2.0
4
–
5.25
14
V
REM on delay time
C=0.1µF
C=0.1µF
8
ms
ms
REM off delay time
Toff
16
24
34
REMOTE ON/OFF SECTION(2)
Detecting input voltage
Detecting V5 voltage
VIN(DET)
V5(DET)
HY1
–
1.20 1.25 1.30
4.1 4.3 4.5
V
V
–
COMP1, 2
COMP3
–
Hysteresis voltage 1
10
0.6 1.2
0.5
40
80
–
mV
V
Hysteresis voltage 2
HY2
Ω
k
PG output load resistor
Charging current for PG delay
PG delay time
RPG
1
2
ICHG.PG
TD.PG
C=2.2µF, VTH =1.8V -10 -15 -23
uA
C=2.2µF
100 260 500 ms
PG output saturation voltage
TOTAL DEVICE
VSAT(PG)
IPG =10mA
–
–
0.4 0.2
V
Standby supply current
ICC
–
10
20
mA
Notes:
1. These Parameters, although guaranteed over their recommended operating conditions are not 100%
tested in production.
2. REM on delay time (Pin6 REM: “L” → “H”),
REM off delay time (Pin6 REM: “H” → “L”)
Rev C, November 1999
7
6. BLOCK DESCRIPTION & APPLICATION INFORMATIONS
6.1 OSCILLATOR BLOCK
Vref
12
VCC
1
12
12
RT
CT
Figure 1. Oscillator RT, CT
The KA3511 is a fixed-frequency pulse width modulation control circuit. An internal-linear sawtooth
oscillator is frequency-programmable by two external components, RT and CT. The oscillator fre-
quency is determined by
1.1
= --------------------
fosc
×
RT CT
300K
100K
VCC=15V
0.001µF
10K
1K
CT=0.01µF
0.1µF
1.0µF
100
30
1K
2K
5K 10K
20K
50K 100K 200K
500K 1M
RT. TIMING RESISTANCE( Ω)
Figure 2. Oscillator Frequency vs. Timing Resistance
6.2 PWM CONTROL BLOCK
Output pulse width modulation is accomplished by comparison of the positive sawtooth waveform
across capacitor CT to either of two control signals. The NOR gates, which drive output transistors
Q1 and Q2, are enabled only when the flip-flop clock-input line is in its low state. This happens only
during that portion of time when the sawtooth voltage is greater than the control signals. Therefore,
an increase in control-signal amplitude causes a corresponding linear decrease of output pulse
width. (Refer to the timing diagram shown in Figure 4)
Rev C, November 1999
8
RT
CT
7
8
OSCILLATOR
Output
Drive
Q1
Q2
D
Q
Q
2
CK
PWM
CONTROL
COMP
4
3
0.12V
DEAD TIME
CONTROLLER
1.25V
Figure 3. PWM Control Block
The control signals are external inputs that can be fed into the dead-time control, the error amplifier
inputs, or the feedback input. The dead-time control comparator has an effective 120mV input off-
set which limits the minimum output dead time. Dead time may be imposed on the output by set-
ting the dead time control input to a fixed voltage, ranging between 0V to 3.3V.
The pulse width modulator comparator provides a means for the error amplifier to adjust the output
pulse width from the maximum percent on-time, established by the dead time control input, down
to zero, as the voltage at the feedback pin varies from 0.5V to 3.5V. The error amplifier may be
used to sense power-supply output voltage, and its output is connect to noninverting input of the
pulse width modulator comparator. With this configuration, the amplifier that demands minimum
output on time, dominates control of the loop.
When capacitor CT is discharged, a positive pulse is generated on the output of the dead time
comparator, which clocks the pulse-steering flip-flop and inhibits the output transistors, Q1 and Q2.
The pulse-steering flip-flop directs the modulated pulses to each of the two output transistors
always for push-pull operation. The output frequency is equal to half that of the oscillator.
The KA3511 has an internal 5.0V reference capable of sourcing up to 10mA of load current for
external bias circuits. The reference has an internal accuracy of ±2% with typical thermal drift of
less than 50mV over an operating temperature range of -25°C to 85°C
Rev C, November 1999
9
Ct
Feedback
Dead-time
control
Ck
Q
Q
Output Q1
Output Q2
Figure 4. Operating Waveform
6.3 DEADTIME CONTROL for SOFT-START
12
Vref
3mA
+
C1
22uF
R1
47k
19
DTC
R2
1k
Remote
ON/OFF
Figure 5. Soft-Start Circuit
Deadtime control for soft-start makes a power supply output rising time (Typ. 15ms) to reduce out-
put ringing voltage for 3.3V, 5V, and 12V. If output rising time is too fast, output ringing voltage
reaches OVP level.
You can make a soft start function by add external components R1, R2 and C1 (refer to figure 5).
At first the main power is turned-on, the deadtime control voltage keeps high state ( · = · 3V), and
then go to the low voltage( · = · 105mV) that devided by R1, R2.
R2
= --------------------- ×
VDTC LOW
Vref(5V) = 104.9mV
+
R1 R2
Rev C, November 1999
10
So Output Duty Ratio will change from the minimum duty ratio to the maximum duty ratio.
Ω
Also, if the remote voltage is high, the deadtime control voltage will keep 3V (=3mA xR2 (1k )) by
the internal 3mA current source for soft start. Therefore, when the remote voltage is low, the dead-
time control voltage will be changed from 3V to almost ground potential. And its soft start time
dependent on external capacitor C1.
6.4 OUTPUT VOLTAGE REGULATION
+12V
+5V
COMP
2
R1
R2
Ω
Ω
33k
11k
R5
1kΩ
Vref
E/A(+)
4
3
PWM Control
Comparator
R3
2kΩ
C1
103
Err-Amp
R4
1kΩ
1.25V
E/A(-)
Figure 6. Output Regulation Circuit
+5V/+12V output voltages are determined by resistor ratio of R1,R2,R3 and R4. The resistor value
can be changed by set condition and requirements.
R5, C1 are the compensation circuit for stability.
If output voltage (+5V or +12V) is increase, duty ratio of main power switch will be reduced by
PWM control comparator signal and error amplifier output. Therefore the output voltage will be
reduced.
On the contrary, if output voltage (+5V or +12V) is reduce, duty ratio of main power switch will be
increased by PWM control comparator signal and error amplifier output. Therefore the output volt-
age will be increased. So the output voltage of power supply will be regulated.
Rev C, November 1999
11
6.5 OVP BLOCK
3.3V 5V 12V
VO
13
14 15
R1
R2
R101
PT
R3
Vref=5V
R5
16
D
A
SET of
R/S Latch
B
C
R102
OVP COMP
R4
1.25V
R6
R102, R102
: External Components
OVP function is simply realized by connecting Pin13, Pin14, Pin15 to each secondary output. R1,
2, 3, 4, 5, 6 are internal resistors of the IC. Each OVP level is determined by resistor ratio and the
typical values are 4.1V/6.2V/14.2V.
OVP Detecting voltage for +3.3V
+
+
R1 R2
R1 R2
(
) = -------------------- ×
= -------------------- ×
=
VOVP 1 +3.3V
VA
Vref
Vref
Vref
4.1V
6.2V
R2
R2
OVP Detecting voltage for +5V
+
+
R3 R4
R3 R4
--------------------
--------------------
(
) =
×
=
VB
×
=
VOVP 2 +5V
R4
R4
OVP Detecting voltage for +12V
+
+
R5 R6
R5 R6
(
) = -------------------- ×
= -------------------- ×
=
14.2V
VOVP 3 +12V
VC
R6
R6
Especially, pin16 (PT) is prepared for extra OVP input or another protection signal. That is, if you
want over voltage protection of extra output voltage, then you can make a function with two exter-
nal resistors.
OVP Detecting voltage for PT
+
+
R101 R102
R101 R102
= ------------------------------ ×
= ------------------------------ ×
VPT
VD
Vref
R102
R102
In the case of OVP, system designer should know a fact that the main power can be dropped after
a little time because of system delay, even if PWM is triggered by OVP.
So when the OVP level is tested with a set, you should check the secondary outputs (+3.3V/+5V/
+12V) and PG (Pin11) simultaneously. you can know the each OVP level as checking each output
voltage in just time that PG (Pin11) is triggered from high to low.
Rev C, November 1999
12
6.6 UVP BLOCK
3.3V
13
5V
14
12V
15
R1
R3
Vref=5V
R5
A
B
SET of
R2
R/S Latch
C
UVP COMP
R2
R6
1.25V
The KA3511 has UVP functions for +3.3V, +5V, +12V Outputs. The block is made up of three input
comparators. Each UVP level is determined by resistor ratio and the typical values are 2.3V/4V/
10V.
UVP Detecting voltage for +3.3V
+
+
R1 R2
R1 R2
(
) = -------------------- ×
= -------------------- ×
=
=
=
VUVP 1 +3.3V
VA
VA
VA
Vref
Vref
Vref
2.3V
4V
R2
R2
UVP Detecting voltage for +5V
) =
+
+
R1 R2
R1 R2
--------------------
--------------------
(
×
=
×
VUVP 2 +5V
R2
R2
UVP Detecting voltage for +12V
+
+
R1 R2
R1 R2
= -------------------- ×
R2
(
) = -------------------- ×
VUVP 3 +12V
10V
R2
Rev C, November 1999
13
6.7 REMOTE ON/OFF & DELAY BLOCK
Ton
Toff
Vref
12
PWM
REM
5V
Ion
Rpull
Trem
5
B
C
2.2V
+
COMP
1.8V
Trem
0.1uF
0.6V
COMP6
Ion/Ioff
PG
Block
Q1
Q2
6
REM
Remote On/Off
Figure 9. Remote ON/OFF Delay Block
Remote ON/OFF section is controlled by a microprocessor. If a high signal is supplied to the
remote ON/OFF input (Pin6), the output of COMP6 becomes high status. The output signal is
transferred to ON/OFF delay block and PG block.
If no signal is supplied to Pin6, Pin6 maintains high status (=5V) for Rpull.
When Remote ON/OFF is high, it produces PWM (Pin6) “High” signal after ON delay time (about
8ms) for stabilizing system.
Then, all outputs (+3.3V, +5V, +12V) are grounded.
When Remote ON/OFF is changed to “Low”, it produces PWM “Low” signal after OFF delay time
(about 24ms) for stabilizing the system.
If REM is low, then PWM is low. That means the main SMPS is operational. When REM is high,
PWM is high and the main SMPS is turned-off.
ON/OFF delay Time can be calculated by following equation.
× ∆
Ion
µ ×
µ
23 A
Ctrem
Von
0.1 F 2V
-----------------------------
×
0.95
--------------------------------------
=
=
×
×
≈
≈
Ton
Toff
K1
K2
= 8.2msec
= 24msec
× ∆
µ
8 A
×
µ
Ctrem
---------------------------------------
Ioff
Voff
0.1 F 2.1V
----------------------------------
×
0.8
(K1, K2: Constant value gotten by test)
In above equation, typical capacitor value is 0.1uF. If the capacitor is changed to larger value, it
can cause malfunction in case of AC power on at remote High. Because PWM maintains low sta-
tus and main power turns on for on delay time. So you should use 0.1uF or smaller capacitor.
Rev C, November 1999
14
6.8 R/S FLIP FLOP (LATCH) BLOCK
R-S F/F (LATCH)
PG BLOCK
R-S FF
REMOTE
ON/OFF
Q
OVP
UVP
S
R
NOR
ON/OFF
DELAY
Start-up
NOR
Q
PG
generator
Delayed
REMOTE
Figure 10. R-S F/F Block Diagram
OVP+
SET
RESET
Low
Qn+1
Qn
Qn+1
Qn
Low
Low
High
High
Low
Low
High
Low
High
Low
High
High
Low
High
Low
High
High
There is a R-S F/F (Latch) circuit for shutdown operation in the KA3511. R-S F/F (Latch) is con-
trolled by OVP, UVP, and some delayed remote ON/OFF signal.
If any output of OVP or UVP is High, SET signal of R-S F/F is high status and it produces PWM
“High” and main power is turned off. When remote signal is high, its delayed output signal is sup-
plied to RESET port of R-S F/F and it produces SET low. So output Q is low status. At this time,
PWM maintains high status by delayed remote high signal.
After main power is turned-off by OVP/UVP and initialized by remote, if remote signal is changed to
low, main power becomes operational.
When you test KA3511, Remote ON/OFF signal should be toggled once for initializing.
Rev C, November 1999
15
6.9 POWER GOOD SIGNAL GENERATOR
Vref +5V
12
14
V
CC
R15
1k
R13
Ichg
11
Vref
Vref
PG COMP
R11
60k
PG
COMP1
Q3
COMP3
1.8V
0.6V
Q2
DET
9
COMP2
10
TPG
Remote
ON/OFF
1.25V
R12
4.7k
+
CPG
2.2uF
R14
Figure 11. PG Signal Generator Block
Power good signal generator curcuits generate “ON & OFF” signal depending on the status of out-
put voltage to prevent the malfunctions of following systems like microprocessor and etc. from
unstable outputs at power on & off. At power on, it produces PG “High” signal after some delay
(about 250ms) for stabilizing outputs.
At power off, it produces PG “Low” signal without delay by sensing the status of power source for
protecting following systems. VCC detection point can be calculated by following equation. recom-
mended values of R11, R12 are external components.
R11
R12
=
×
+ ----------
1 = 17.2V
VDET
1.25V
COMP3 creates PG “Low” without delay when +5V output falls to less than 4.3V to prevent some
malfunction at transient status, thus it improves system stability.
When remote On/Off signal is high, it generates PG “Low” signal without delay. It means that PG
becomes “Low” before main power is grounded.
PG delay time (Td) is determined by capacitor value, threshold voltage of COMP3 and the charg-
ing current and its equation is as following.
∆
Ichg
×
Ichg
µ ×
µ
18 A
V
PG Vth
2.2 F 2V
= ----------- ≈ ------------------------ = ----------------------------- ≈
Td
250ms
Rev C, November 1999
16
Considering the lightning surge and noise, there are two types of protections. One is a few sec-
onds delay between TPG and PG for safe operation and another is some noise margin of Pin10.
Noise_Margin_of_TPG = V10(max) – Vth(L) = 2.9V – 0.6V = 2.3V
7. ABOUT TEST METHOD
You can verify the KA3511 with a SMPS set. But you should pay attention to the device damage
problem by increasing VCC. You should remove the sub-board after +5Vsb drops to 0V and VCC of
KA3511 is grounded and then fan stops under the Remote Low.
– OVP function of +3.3V/+5V/+12V
You can test OVP for +3.3V/+5V/+12V by shorting Pin16 and Pin17 to GND.
– UVP function of +3.3V/+5V/+12V
You can simply test UVP for +3.3V/+5V/+12V by shorting Pin16 to GND.
– OVP input threshold voltage for PT
The test condition is remote “Low” and you increase the supply voltage of pin16 using a DC
power supply. When the voltage is over 1.2 x V, main power supply will shutdown. So, you can
measure the shutdown point of main power supply, and that will be a OVP input threshold volt-
age for PT.
– Remote On/Off delay time
You can measure the time difference of remote On/Off and the main power supply output as
toggling the remote On/Off.
– PG delay time
In AC power-on time, secondary outputs are turned on and then after some delay time PG out-
put is triggered from low to high. You can measure the time difference of +5V and PG in turn-on
time.
Rev C, November 1999
17
8. HOUSE KEEPING CIRCUIT
2kΩ(1W)
2kΩ(1W)
Standby
Supply
1
2
22
21
20
19
18
17
16
15
14
13
12
VCC
COMP
E/A(-)
E/A(+)
TREM
C1
E
VCC=20V
15k
Ω
12V
5V
0.01uF
3
C2
11kΩ
33kΩ
4
DTC
GND
K
A
3
5
1
1
1.8kΩ
5
+
0.1uF
6
REM
TUVP
1k
Ω
Micom
+
2.2uF
7
PT
RT
12kΩ
8
12V
V12
V5
CT
+
0.01uF
9
DET
5V
3V
10
11
TPG
V3.3
Vref
+
2.2uF
PG
PG
+
1uF
Using the KA3511 requires few external components to accomplish a complete housekeeping cir-
cuits for SMPS.
Rev C, November 1999
18
9. TYPICAL CHARACTERISTICS
Bandgap Reference Voltage
Temperature Characteristic
V
-I
CC CC
0.014
0.012
5.010
5.008
0.010
0.008
5.006
5.004
0.006
0.004
0.002
0.000
5.002
-40 -20
0
20
40
60
80 100 120 140
0
10
20
30
40
Supply Voltage [V]
TEMP [°C]
PIN19(Dead Time Control Voltage)-Duty Cycle
OVP for 3.3V
50
40
5
4
3
2
31.1%
30
20
10
21.8%
12.8%
1
0
0
3.6
3.8
4.0
4.2
4.4
4.6
0.0
0.5
1.0
1.5
2.0
2.52.73 3.0
Deadtime Control Voltage [V]
V3.3 [V]
OVP for 5V
OVP for 12V
7
6
5
4
3
2
5
4
3
2
1
0
1
0
5.0
5.5
6.0
V5 [V]
6.5
7.0
14.0
14.2
14.4
14.6
V12 [V]
14.8
15.0
Rev C, November 1999
19
UVP for 3.3V
OVP for PT
5
4
3
2
5
4
3
2
1
0
1
0
21
22
23
24
25
1.15
1.20
1.25
1.30
1.35
Pin 13 (V3.3) Voltage [V]
Vpt [V]
UVP for 5V
UVP for 12V
5
5
4
3
4
3
2
2
1
0
1
0
9.0
9.5
10.0
10.5
11.0
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
Pin 15 (V12) Voltage [V]
Pin 14 (V5) Voltage [V]
Remote ON Charging Current
REM ON/OFF Vth
-0.000016
5
4
-0.000018
-0.000020
3
2
1
-0.000022
-0.000024
0
0
1
2
3
4
5
0
50
100
150
200
250
Vrem [V]
Rev C, November 1999
20
Detecting V
Voltage (DET)
CC
Remote ON Open Voltage
5
5
4
3
4
3
2
1
2
1
0
0
0
1
2
3
4
5
1.0
1.1
1.2
1.3
1.4
1.5
Pin 9 (DET) Voltage [V]
Detecting V5 Voltage
Charging Current for PG
-0.000005
-0.000010
-0.000015
5
4
3
2
1
-0.000020
0
4.0
4.2
4.4
4.6
4.8
5.0
0
20
40
60
80 100 120 140 160
Pin 14 (5V) Voltage [V]
Short Circuit Current
Hysteresis Voltage 2
5
4
-0.032
-0.033
-0.034
3
2
1
0
-0.035
0
100
200
300
400
0.0
0.5
1.0
1.5
2.0
2.5
Pin 10 (TPG) Voltage [V]
Rev C, November 1999
21
Error Amp Sink Current
Reference Voltage
0.002
0.00
5
4
3
2
1
-0.002
-0.004
-0.006
-0.008
0
0
20
40
60
80
100
120 140
0
10
20
30
40
Supply Voltage [V]
Rev C, November 1999
22
10. PACKAGE DIMENSION
22-DIP-400
9.14 ±0.20
0.360 ±0.008
1
22
12
11
10.16
0.400
3.81 ±0.20
0.150 ±0.008
0.51
0.020
MIN
3.40 ±0.30
0.134 ±0.012
5.08
MAX
0.200
Rev C, November 1999
23
11. EXPERIMENTAL RESULT
CH1 : PS-ON
CH2 : +5Vdc Output
CH3 : PG Signal
Figure 12. Rising Time of +5Vdc Output Voltage
CH1 : PS-ON
CH2 : +5Vdc Output
CH3 : PG Signal
Figure 13. PG Signal Delay Time
Rev C, November 1999
24
CH1 : PS-ON
CH2 : +5Vdc Output
CH3 : PG Signal
Figure 14. Power Down Warning
CH1 : +3.3Vdc Output
CH2 : +5Vdc Output
CH3 : +12Vdc Output
Figure 15. No Load Protection
25
Rev C, November 1999
CH1 : Vcc
CH2 : +5Vdc Output
CH3 : PG Signal
Figure 16. Vcc, +5Vdc Output vs. PG Signal (High)
CH1 : Vcc
CH2 : +5Vdc Output
CH3 : PG Signal
Figure 16. Vcc, +5Vdc Output vs. PG Signal (Low)
Rev C, November 1999
26
12. APPLICATION CIRCUIT
47K
R6
70K
R5
VCC
IC1
C1
C2
1
22
21
20
19
18
17
16
15
14
13
12
103
Vcc
C1
E
2
3
COMP
E/A(-)
E/A(+)
TREM
REM
RT
R4
C2
1.2K
15K
4
POWER ON
OUT REF
DTC
GND
TUVP
PT
5
0.1uF
6
R3
C6
56K
2.2uF
+
7
22uF
8
12V OUT
5V OUT
CT
V12
V5
103
9
DET
TPG
PG
10
11
3.3V OUT
V3.3
Vref
2.2uF
PG
AR3511X
D19
D9
C16
100K
VR1
+
CT
Reference
1. Power Electronics by Marvin J. Fisher
2. Principles Of Power Electronics by Kassakian
AUTHOR:
Sang-Tae Im: P-IC Application Team
Tel. 82-32-680-1275
Fax. 82-32-680-1317
E-mail. sangtae.im@Fairchildsemi.co.kr
Rev C, November 1999
27
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
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FACT™
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DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
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systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Definition
Advance Information
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product development. Specifications may change in
any manner without notice.
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First Production
This datasheet contains preliminary data, and
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