AN-35 [ETC]
LinkSwitch Design Guide ; LinkSwitch的设计指南\n
| 型号： | AN-35 |
| 厂家： | 
ETC |
| 描述： | LinkSwitch Design Guide
|
| 文件： | 总16页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
LinkSwitch
Design Guide
Application Note AN-35
LinkSwitch is designed to produce an approximate CV/CC
outputcharacteristicasshowninFigure2.Inchargerapplications,
a discharged battery operates on the CC portion of the curve
until almost fully charged and then naturally transitions to the
CV portion of the curve. Below an output voltage of
approximately 2 V (consistent with a failed battery pack), the
supply enters auto-restart, reducing the average output current
to approximately 8% of nominal.
Introduction
Integrated switching power supply technology, offering small
size, low weight and universal AC input voltage operation, has
finally evolved to cost-effectively replace linear transformer-
based power supplies for low power applications. LinkSwitch
reduces the cost of switching battery chargers and AC adapters
to the level of linear transformer power supplies. LinkSwitch
also easily meets standby and no-load energy consumption
guidelinesspecifiedbyworldwideregulatoryprogramssuchas
the USA’s Presidential 1 W Standby Executive Order and the
European Commission’s 2005 requirement for 300 mW
no-load consumption.
In an AC adapter, normal operation occurs only on the CV
portion of the curve, the CC portion providing overload
protection and auto-restart short circuit protection.
LinkSwitch is a fixed frequency PWM controlled device,
designed to operate with flyback converters in discontinuous
mode. In the CV portion of the curve, the device operates using
voltage mode control and changes to a current limit mode
during the CC portion of the curve. Total system CV accuracy
is typically 10% at the peak power point, including all device
tolerances and line input voltage variations. With transformer
primary inductance variations within 10%, the total system
CC accuracy is typically 20% (LNK501) or 25% (LNK500)
compared to nominal values.
The feature set of LinkSwitch offers the following advantages
over other solutions:
• Lowest cost and component count for a constant voltage,
constant current (CV/CC) solution
• Extremely simple circuit – only 14 components required
for a production-worthy design
• Primary based CV/CC solution eliminates 10 to 20
components for low system cost
• Up to 75% lighter power supply reduces shipping costs
• Fully integrated auto-restart for short circuit and open
loop fault protection
DuringCVoperation,thereflectedoutputvoltage(VOR)controls
the duty cycle. LinkSwitch is placed in the high side rail, as
shown in Figure 1, such that VOR can be sensed directly,
requiring no additional subtraction of the input voltage
component.
• 42 kHz operation simplifies EMI filter design
• 3 W output with EE13 core for low cost and small size
L1
U1
CCP
680 µH - 2.2 mH,
≥80 mA RMS
LinkSwitch 0.22 µF/1 µF,
V
RSEC
V
DOUT
V
+
+
+
RCABLE
10 V
N :N
P S
D
S
RSEC
0.15 Ω
DOUT
0.7 V/
1.1 V
RCABLE
0.3 Ω
C
RF1
10 Ω
IO
IDCT
RFB
CCLAMP
VFB
+
C1+C2
3 µF/W
or 1 µF/W
0.1 µF, 100 V
Fusible
+
VO
+
VSEC
VOR
Load
COUT
AC INPUT
+
DCLAMP
1N4937
D1-D4
IN4005
1 A, 600 V
~
ISEC(RMS) 2 x I
ISEC(PEAK) 4 x I
~
O
O
VLEAK
+
~
~
RLF
100 Ω
L
P
PI-2957-081602
Figure 1. Key Parameters for an Initial LinkSwitch Design.
April 2003
AN-35
During CC operation, duty cycle is controlled by the peak drain
current limit (ILIM). The device current limit is designed to be a
function of reflected voltage such that the load current remains
approximately constant as the load impedance is reduced. When
the output voltage falls to approximately 30% of nominal value
(normally associated with a failed battery), LinkSwitch enters the
auto-restartmodeofoperationtosafelylimitaveragefaultcurrent
(typically 8% of IO).
QUICK START
Figure 1 shows the key parameters and components
needed to generate an initial LinkSwitch design.
Where initial estimates can be used, they are shown
below the parameter they refer to.
1) Let VOR equal 50 V.
With discontinuous mode design, maximum output power is
independentofinputvoltageandisasimplefunctionofprimary
inductance, peak primary current squared and switching
frequency (Equation 6). LinkSwitch controls and cancels out
variationsnormallyassociatedwithfrequencyandpeakcurrent
by specifying a device I2f term. This allows users to easily
design for a specific corner point where CV mode transitions to
CC mode.
2) Define the transformer turns ratio according to
Equation 5. If no better estimates or measure-
ments are available, then let VDOUT equal 0.7 V
foraSchottkyor1.1VforaPNdiode,RCABLE equal
0.3 Ω, RSEC equal 0.15 Ω, ISEC(RMS) equal 2x IO, and
I
SEC(PEAK) equal 4 x IO, where IO is the desired CC
output current and VO is the desired output
voltage at the CV/CC transition point.
Scope
3) Calculate PO(EFF) according to Equation 13. As an
initial estimate for PCORE use 0.1 W.
This application note is for engineers designing an AC-DC
powersupplyusingtheLinkSwitchLNK500orLNK501devices
in a discontinuous mode flyback converter. Since LinkSwitch is
designed to replace linear transformer based power supplies,
the output characteristic provides an approximate CV
characteristic, offering much better line and load regulation
thananequivalentlineartransformer. Theverysimplenatureof
the LinkSwitch circuit allows an initial paper design to be
completed quickly using simple design equations. It is then
recommended that the circuit performance be tuned with a
prototypepowersupplytofinalizeexternalcomponentchoices.
This document therefore highlights the key design parameters
and provides expressions to calculate the transformer turns
ratio,primaryinductanceandclamp/feedbackcomponentvalues.
This enables designers to build an operating prototype and
iterate to reach the final design.
4) Calculate LP according to Equation 14 and
other transformer parameters from Equations
15, 16, 17, 18 and 19.
5) Calculate value for feedback resistor RFB accord-
ing to Equations 20, 21, 22, 23 and 24.
This should be a 1/4 W, 1% part.
6) Set clamp capacitor CCLAMP as a 0.1 µF, 100 V
metalized plastic film type.
7) Set clamp resistor RLF as 100 Ω, 1/4 W.
8) Set CONTROL pin capacitor CCP to be 0.22 µF,
10 V for battery loads or 1 µF, 10 V for resistive
loads.
9) Select input and output components. See
Figure 3 and relevant sections.
For readers who want to generate a design as quickly as
possible, the Quick Start section provides enough information
to generate an initial prototype.
10) Construct prototype.
11) Iterate design (see Hints and Tips section).
This document does not address transformer construction.
Please see LinkSwitch DAK Engineering Prototype Report for
examplesshowingtypicaltransformerconstructiontechniques.
Further details of support tools and updates to this document
can be found at www.powerint.com.
nominalpeakpowerpointoutputvoltageVO,whiletransformer
primary inductance is calculated from the total output power.
Few components require computations, while the balance are
selected from the included recommendations.
CV/CC Circuit Design
The LinkSwitch circuit shown in Figure 3 serves as a CV/CC
chargerexampletoillustratedesigntechniques.Nominaloutput
voltage is 5.5 V and nominal CC output current is 500 mA.
Design and selection criteria for each component are described
startingwiththetransformer. Onceset, transformerparameters
and behavior are used to design clamp, bias and feedback
componentsforpropersupplyoperation. Outputcapacitorsand
the input circuitry can then be determined.
LinkSwitch design methodology is very simple. Transformer
turns ratios and bias component values are selected at the
B
4/03
2
AN-35
10
9
115 VAC
230 VAC
Limits (LNK501)
Limits (LNK500)
Auto-restart
8
7
6
5
4
3
2
1
0
0
100
200
300
400
500
600
700
Output Current (mA)
Figure 2. Typical Output Characteristic for LinkSwitch Based 5.5 V, 0.5 A Charger with Specification Limits.
Transformer T1
The value for IPRI(PEAK) is equal to the typical value of the
LinkSwitch data sheet parameter ILIM
.
Transformer design begins by selecting the reflected output
voltage (VOR). For most LinkSwitch designs, VOR should be
between 40 V and 60 V. A good starting point is 50 V allowing
for optimization later.
As an initial estimate the ISEC(PEAK) can be approximated as
4 xIO. Once the first prototype has been built this can be refined
as the final turns ratio is known or alternatively, the peak diode
forwardvoltagecanbemeasureddirectlyusinganoscilloscope.
VOR values over 60 V are recommended only for those
applications allowed to consume over 300 mW at no-load.
VRCABLE = IO × RCABLE
(2)
To calculate the transformer turns ratio, the voltage required
across the secondary winding VSEC is first calculated. This is a
function of output cable voltage drop VRCABLE, nominal output
VRSEC = ISEC(PEAK) × RSEC
VSEC = VO + VRCABLE + VDOUT + VRSEC
(3)
(4)
voltage VO, the secondary winding voltage drop VRSEC, and
output diode forward voltage drop VDOUT. Figure 1 shows the
sources of secondary side voltage drops. Since CCLAMP charges
tothepeakvalueofVOR plusanerrorduetoleakageinductance,
the value of VRSEC and VDOUT are defined at the peak secondary
current. The output cable drop VRCABLE is defined at the nominal
CC output current IO.
The transformer turns ratio is given by:
NP VOR
(5)
=
NS VSEC
If no better estimates or measurements are available, use
0.15Ωasaninitialvalueforthetransformersecondarywinding
resistance RSEC, 0.7 V for the forward voltage (VDOUT) of a
Schottky diode or 1.1 V for a PN diode and 0.3 Ω for the cable
Curves of VDOUT versus instantaneous current can be found in
the diode manufacturer’s data sheet. Peak secondary current is
defined as:
resistance RCABLE
.
NP
ISEC(PEAK) = IPRI(PEAK)
×
(1)
NS
B
4/03
3
AN-35
U1
L1
1 mH
LinkSwitch
T1
5.5 V,
500 mA
1
4
D
S
5
6
C3
0.22 µF
50 V
C
15 T
#30 AWG
TIW
C5
470 µF
10 V
116 T
#34 AWG
BR1
RF1
10 Ω 1 W
Fusible
1 A, 600 V
C4
0.1 µF
100 V
R1
20.5 kΩ
1%
RTN
3
P
C1
C2
D6
11DQ06
85-265
VAC
4.7 µF
400 V
4.7 µF
400 V
EE13
= 2.55 mH
D5
L
1N4937
R2
100 Ω
PERFORMANCE SUMMARY
Output Power:
Efficiency:
2.75 W
≥72%
No Load
Consumption:
260 mW, 230 VAC
200 mW, 115 VAC
PI-3476-032403
Figure 3. Example Schematic for a Typical LinkSwitch Charger.
The next transformer design step is to calculate the nominal
primary inductance LP. LP tolerance should be within 10% (to
meet peak power CC tolerance of 20% for LNK501, 25% for
LNK500). The simple LinkSwitch feedback circuit is designed
specifically for discontinuous mode operation. Continuous
mode designs result in control loop instability and are therefore
not recommended. For proper CC operation, the LinkSwitch
transformer must therefore be designed for discontinuous
operation under all line/load conditions.
the sum of actual output power PO and the following loss terms:
cable power PCABLE, diode power PDIODE, bias power PBIAS(the
power required to drive the LinkSwitch CONTROL pin),
transformer secondary copper loss PS(CU) , and transformer core
loss PCORE
.
P
= RCABLE × IO2
= VDOUT × IO
(7)
CABLE
(8)
(9)
P
DIODE
P
= VOR × 2.3 mA
BIAS
At the peak power point, the power processed by the core or
PO(EFF) is given by:
KCORE × VE
(10)
(11)
P
=
CORE
2
P
= IS2EC(RMS) × RSEC
2
1
S(CU)
P
=
× LP × IP × fS
(6)
O(EFF)
[
]
2
RCABLE is the total cable DC resistance, IO is the nominal CC
output current, VDOUT is output diode forward voltage drop, VOR
is reflected output voltage, ISEC(RMS) is secondary RMS current,
RSEC is output winding DC resistance, VE is core effective
volume and KCORE is core loss per unit volume. As before, if no
better estimates or measurements are available, use 0.15 Ω for
RSEC, 0.7 V for the forward voltage (VDOUT) of a Schottky diode
or 1.1 V for a PN diode, 0.3 Ω for RCABLE and ISEC(PEAK) equal to
4 x IO. Both VE and KCORE can be read from the ferrite core
manufacturer’smaterialcurves. TofindKCORE,usethecoreflux
swing BM. In discontinuous mode operation, AC Flux Density
BAC is equal to BM:
LP is the nominal transformer primary inductance, IP is equal to
the LinkSwitch parameter ILIM and fS is the switching frequency.
NotethatIP andfS areenclosedinbracketsastheLinkSwitchdata
2
2f
sheet specifies an I f coefficient equal to the IP product,
S
normalized to IDCT. By normalizing to IDCT (the CONTROL pin
current at 30% duty cycle), the effect of IDCT tolerance is
included and does not need to be considered separately. Output
power is therefore dependent primarily on transformer primary
inductance tolerance (typically 10% for low cost high volume
production methods).
As shown above, effective output power PO(EFF) is calculated
from the total energy stored in the transformer and is therefore
(12)
BAC = BM
B
4/03
4
AN-35
The division by two in the expression for PCORE is required since
a flyback transformer only excites the core asymmetrically and
the core loss curves are typically specified assuming a
symmetrical excitation.
OnceanestimateforthenumberofsecondaryturnsNS hasbeen
made, the primary turns is found from:
VOR
(15)
NP =
× NS
VSEC
KCORE is then read directly from material core loss curves at the
LinkSwitch switching frequency (typically 42 kHz). A figure
for BM of approximately 3300 gauss (330 mT) is a good initial
estimate. A figure for PCORE of 0.1 W is a good initial estimate.
100
80
PO(EFF) is calculated from:
P
CORE
P
= P + P
)
+ P
+ P + P
+
O
CABLE
DIODE
BIAS
S(CU)
O EFF
(
Area compensated
2
by ∆L term
(13)
PO here is defined as the output power seen by the load. Note
the core loss term is divided in half as only the loss associated
with transferring energy to the output during the off time needs
to be compensated for in the primary inductance value.
250 330
Flux Density (mT)
PI-3148-081502
Figure 4. Typical Reduction in Primary Inductance with Flux
Density for Small E Cores with Small Gap Sizes.
Nominal primary inductance LP(NOM) is calculated from:
2 × P
O EFF
(
)
LP(NOM)
=
× ∆L
(14)
At this point the core size should be selected. Common core
sizes suitable for a LinkSwitch design include EE13, EF12.6,
EE16 and EF16. With the core selected and the number of
transformer turns known, the core peak flux density BP (gauss)
can be found using the effective cross sectional area of the core
Ae (cm2), the primary inductance (µH) and the LinkSwitch peak
current limit ILIM(MAX) (A):
IP2 × fS
[
]
ThetypicaldatasheetvaluefortheI2fcoefficientshouldbeused
to replace IP2fS, this defining the nominal primary inductance at
the nominal output peak power point.
As the flux density increases, the inductance falls slightly due
to the BH characteristic of the core material as shown in
Figure 4. This drop in inductance is compensated by increasing
the inductance at zero flux density by a factor ∆L. This is
typically in the range of 1 to 1.05 for common low cost ferrite
materials. This effect can be minimized by increasing the gap
size, reducing the flux density or using ferrite materials with a
higher saturation flux density.
100 × ILIM(MAX) × LP
(16)
BP =
NP × Ae
BP should be in the range of 3000 gauss to 3500 gauss
(300 mT to 350 mT).
The relative permeability µr of the ungapped core must be
calculated to estimate the gap length Lg. The relative
permeability, µr is found from core parameters Ae (cm2), the
effective core path length Le (cm), and ungapped effective
inductance AL(nH/t2):
Transformer inductance tolerance is most affected by the
transformer core gap length. Inductance must also be stable
over temperature and as a function of current. Recommended
minimumgaplengthis0.08mm(3.2mils)atapeakfluxdensity
of 3300 gauss to 3500 gauss (330 mT to 350 mT).
AL × Le
0.4 × π × Ae ×10
µr =
(17)
The number of secondary turns for small E cores is typically 2
to 3 turns per volt across the secondary winding (including
cable, secondary and diode voltage drops). The actual number
is adjusted to meet gap size and flux density limits.
Gap length Lg is the air gap ground into the center leg of the
transformer core. Grinding tolerances and AL accuracy place a
minimumlimitofapproximately0.08mmonLg.If Lg issmaller
than this then either the core size (Ae) or NP must be increased.
Lg (mm) is calculated from primary turns NP, core effective
B
4/03
5
AN-35
cross sectional area Ae (cm2), primary inductance LP (µH), core
effective path length Le (cm) and relative permeability µr:
The secondary diode peak voltage was measured as 0.7 V, the
secondarywindingresistanceas0.15Ωandthecableresistance
as 0.23 Ω. Therefore VSEC is defined as:
2
0.4 ×π × NP × Ae Le
(18)
Lg =
−
×10
VSEC
=
=
VO + VRCABLE + VDOUT + VRSEC
VO + (IO × RCABLE ) + VDOUT
+ (ISEC(PEAK) × RSEC )
LP ×100
µr
The gapped effective inductance ALG (nH/t2), required by the
transformer manufacturer, is calculated from the primary
inductance LP (µH) and the number of primary turns NP:
(21)
= 5.5 V + (0.5 A × 0.23 Ω) + 0.7 V
+ (1.96 A × 0.15 Ω)
= 6.61 V
LP
NP2
(19)
ALG = 1000 ×
Voltage VSEC allows the exact VOR to be calculated:
Clamp, Bias, Bypass and Feedback
NP
An RCD clamp, formed by RFB, CCLAMP, and DCLAMP
(Figure 1), safely limits transformer primary voltage, due to
transformerleakageinductance,tobelowtheLinkSwitchinternal
MOSFET breakdown voltage BVDSS each time LinkSwitch
turns off. Leading-edge voltage spikes (caused by transformer
leakage inductance) are filtered by RLF and CCLAMP, such that
CCLAMP effectively charges to the transformer reflected voltage.
VOR =
× VSEC
NS
116
15
(22)
=
× 6.61 V
= 51.1 V
Resistor RFB, a 1%, 0.25 W resistor, converts clamp voltage to
Feedbackisderivedfromthereflectedvoltage,thatapproximates
closely the transformer secondary winding output voltage
(VSEC inFigure1)multipliedbythetransformerturnsratio. Due
to effects of leakage inductance (causing peak charging),
calculated VOR may be slightly different from actual voltage
measured across CCLAMP. Since LinkSwitch is in the upper rail,
reflected voltage information is now relative to the LinkSwitch
SOURCE pin and independent of the input voltage.
LinkSwitch bias and control current.
Feedback voltage VFB is calculated from VOR and the error due
to leakage inductance, VLEAK
.
The value for VLEAK varies depending on the value of leakage
inductance,thesizeoftheclampcapacitorandthetypeofclamp
diode selected. For a leakage inductance of 50 µH, a value of
5 V is a good initial estimate.
Reflected voltage is directly converted by RFB to LinkSwitch
CONTROL pin current for duty cycle control and bias. The
CONTROL pin capacitor CCP provides bypass filtering, control
loop compensation, and the energy storage required during
start-up and auto-restart.
VFB = VOR + VLEAK
(23)
Once a prototype has been constructed, the value of VFB can be
found directly, by measuring the voltage across CCLAMP at the
power supply peak output power point, using a battery powered
digitalvoltmeter. Thesehavesufficientcommonmoderejection
to be unaffected by the switching waveform and provide
accurate results. The voltage measured is VFB. By subtracting
VOR thevalueforVLEAK canbedetermined, usefulasanestimate
in future designs. For the design in Figure 3, VFB was measured
as 56.7 V, giving VLEAK as 5.6 V.
Feedback Resistor (RFB)
Clamp and feedback circuit design begins by first considering
reflected voltage. Using the schematic in Figure 3 as an
example. With primary turns NP = 116 and secondary turns
NS = 15 the peak secondary current can be calculated from
Equation 20, where IPRI(PEAK) is equal to the LinkSwitch
typical current limit ILIM(TYP)
.
An initial value for RFB is calculated from the feedback voltage
VFB, the CONTROL pin voltage VC(IDCT) and current IDCT at the
CC/CV transition point, specified in the LinkSwitch
data sheet.
NP
NS
116
ISEC(PEAK)
=
=
× IPRI(PEAK)
× 0.254
(20)
15
= 1.96 A
B
4/03
6
AN-35
V
V
Peak Power
Curve
Peak Power
Curve
Reduced RLF or
increased leakage
inductance
Increased RLF or
reduced leakage
inductance
Reference
Reference
Reduced RLF
or increased
leakage
Higher RLF
or lower
leakage
inductance
inductance
Auto-restart
Auto-restart
I
I
PI-2958-081602
Figure 5. Effect on Output Characteristic when RLF or Leakage Inductance Changes.
VFB − VC(IDCT)
V
RFB =
IDCT
56.7 V − 5.75 V
2.3 mA
(24)
Peak Power
Curve
=
= 22 kΩ
Select the nearest standard value. Resistor RFB can then be
adjusted to center the output voltage. The example in
Figure 3 uses a 20.5 kΩ value for RFB (R1), centering the output
voltage VO near 5.5 V at nominal output current IO.
Increased RFB
Reference
Increased
R
FB to adjust
for LLEAK
Note that RFB power dissipation, a significant component of
Auto-restart
LinkSwitch standby power, should always be calculated:
I
PI-2959-071902
2
(25)
P
= 2.3 mA × R = 111 mW
(
)
RFB
FB
Figure 6. Increasing RFB to Adjust for High Leakage Increases No
load Voltage and Consumption.
For applications that do not need to comply with strict standby
power requirements, higher values of VOR can be used, also
increasing the power capability of LinkSwitch.
Clamp Resistor (RLF)
ThevalueforRLF,whicheffectivelyfilterstheleakageinductance
spikefromthereflectedvoltagewaveform,isverifiedempirically
through iteration. RLF has a direct effect on both the average
value and slope of both the CV and CC curves as shown in
Figure5andcanthereforebeusedtotunetheoutputcharacteristic
to some extent.
Clamp Diode (DCLAMP
)
DiodeDCLAMP shouldbeanultra-fastorfastrecoverydiodewith
at least 600 V breakdown voltage. Fast types typically offer a
slightcostadvantageandalsoreduceEMI,sotheyarepreferred.
Note that normal recovery diodes (1N400X or similar types),
which may allow excessive drain voltage ringing, should not be
used.
In the CV region, increasing RLF increases the average output
voltage, while reducing the slope of the CV region (the change
in output voltage with the change in output current). In the CC
region, increasing RLF makes the average output current lower,
while tending to “bend” the curve inward slightly (fold back).
B
4/03
7
AN-35
RCABLE
with stable dielectrics (NPO or COG, for example) are higher
cost.Thevalueoflowcostceramiccapacitorsvariessignificantly
withvoltageandtemperature(Z5Udielectric, forexample)and
should not be used since they may cause output oscillation.
RLOAD
RINT_RES
RCABLE = 0.23 Ω
RINT_RES = 0.5 Ω
RLOAD= 11 Ω
CONTROL Pin Capacitor (CCP)
2 x 1N4001
10,000 µF
CCP sets the auto-restart period and also the time the output has
to reach regulation before entering auto-restart at power supply
start-up. If the load is a battery, then a value of 0.22 µF is
typical. However, if the supply is required to start into a
resistiveloadorconstantcurrentload(suchasabenchelectronic
load) at the peak output power point, then this should be
increased to 1 µF. This ensures enough time during start-up to
bring the output into regulation. The type of capacitor is not
critical. Either a small ceramic or electrolytic may be used with
a voltage rating of 10 V or more.
PI-2975-072402
Figure 7. Example of Battery Model Load (Values for a Typical
3 W, 5.5 V Battery Charger).
Atno-load,increasingRLF slightlyincreasestheno-loadvoltage
sincetheprimaryleakageinductanceisfilteredmoreeffectively,
butthesamepeakchargingduetosecondaryleakageinductance
occurs. Although the no-load voltage is slightly higher, there is
only a minor effect on no-load consumption.
Output Rectifier and Filter (DOUT, COUT
)
The output diode should be selected with an adequate peak
inverse voltage (PIV) rating. Either PN or Schottky diodes can
be used. Schottky diodes offer higher efficiency at higher cost
but provide the most linear CC output characteristic. Both fast
or ultra fast PN diodes may be used, but ultra fast (trr~50 ns)
are preferred giving CC linearity close to the performance of a
Schottky.
In a design that has high leakage, the value of RFB can be
increasedtoraisetheoveralloutputvoltage(Figure6). However,
this will also increase no-load voltage and therefore no-load
input power consumption.
To iterate RLF:
NS
NP
(26)
• Start with typical value of 100 Ω and a transformer with
nominal inductance.
PIV DOUT ≥ V
×
+ V ×1.5
(
)
DC(MAX)
O
• Verify CC portion of the curve and increase or decrease
RLF until CC curve is approximately vertical (current at
start of CC and end are approximately the same)
• Verify CV portion of the curve.
The output diode voltage rating should be calculated from
Equation 26. VDC(MAX) is the maximum primary DC rail voltage
(375 V for universal or 230 VAC and 187 V for 115 VAC only
designs). TheoutputvoltageVO ismultipliedby1.5toallowfor
increased output voltage at no-load. An output diode current
rating of 2 x IO is a good initial estimate.
- For minor adjustment, change value of RFB.
Clamp Capacitor (CCLAMP
)
WithsmallvaluesofclampcapacitorCCLAMP, theoutputvoltage
tendstobeslightlyhigher. WithlargervaluesforCCLAMP,output
voltage will be slightly lower. Further increases in CCLAMP will
not change the output voltage.
The output diode may be placed in either the upper or lower leg
of the secondary winding. However, placement in the lower leg
may provide lower conducted EMI with a suitably constructed
transformer.
CCLAMP isthereforechosenempiricallyasthesmallestvaluethat
doesnotsignificantlychangetheoutputvoltagewhencompared
to the next larger value. For most designs, 100 nF is typical and
standard device tolerances will have a negligible effect on the
output voltage. This capacitor should be rated above the VOR,
typically 100 V.
For battery charger applications, the size and cost of the output
capacitorCOUT canbesignificantlyreduced. Highripplecurrent
flows through COUT for only the short time a fully depleted
battery charges. The designer should take into account that
COUT ripple current rating can be exceeded for short periods of
time without reducing lifetime significantly. When the battery
is close to fully charged, the LinkSwitch circuit transitions to
CV mode, where capacitor ripple current is much smaller.
CCLAMP must have a stable value over temperature and also over
the operating voltage range. Metalized plastic film capacitors
are the best choice, since the higher voltage ceramic capacitors
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V
Peak Power
Curve
Increasing cable
resistance
Reference
Increased
output cable
resistance
Auto-restart
PI-2961-072202
I
PI-2962-072202
Figure 9. Effect on Output Characteristic Due to Increased Output
Cable Resistance.
Figure 8. Uneven Core Gapping Makes CC Portion Nonlinear and
Should be Avoided.
For adapter applications drawing rated load current in steady
state, COUT should be a low ESR type, properly rated for ripple
current.
To meet certain safety agency requirements RF1 should fail
open without emitting smoke, fire or incandescent material,
that might damage the primary-to-secondary insulation barrier.
Consult with a safety engineer or local safety agency for
specific guidance.
Designsforbatterychargingusuallydonotrequireanadditional
output L-C stage (π filter) to reduce switching noise. The
battery itself will filter this noise and output ripple. However,
if the load is resistive, then this stage may be required to meet
ripple and noise specifications. For evaluation of a battery
charger during design, a battery load can be simulated using a
circuit similar to that shown in Figure 7, which models both the
battery and output cable.
Diodes D1-D4 should be rated at 400 V or above and be
standard recovery types to minimize EMI.
The combined value of C1 and C2 should be selected to give
3 µF per watt (of output power), giving acceptable voltage
ripple for universal designs. For high single input voltage
ranges (185 VAC to 265 VAC), this recommendation can be
reduced to 1 µF/W, however ripple current ratings and
differentialmodelinetransientperformanceshouldbeverified.
Bridge Rectifier, Energy Storage, and EMI Filter
Figure 1 shows a typical input stage for a low cost design. D1-
D4 rectifies universal AC input voltage. C1 and C2 provide
energy storage, smoothing, and EMI filtering. RF1 reduces
surge current, EMI and will also safely open, like a fuse, if
another primary component fails in a short circuit.
L1, which is effective for low frequencies, is typically in the
range of 680 µH to 2.2 mH and should have a current rating of
≥80 mA RMS.
Hints and Tips
Transformer Construction
The conducted emissions EMI filter has effectively two
differential mode stages. RF1 and C1 form the first differential
mode stage. The second differential mode filter stage is formed
by L1 and C2.
Since the primary inductance is crucial in setting the peak
output power, the tolerance of this parameter should be well
controlled. ForaCCtoleranceatthepeakpowerpointof 20%/
25%(LNK501/LNK500,respectively)theprimaryinductance
tolerance should be 10% or better.
RF1 should be a 10 Ω low cost wire-wound fusible resistor or
be replaced by a fuse. A resistor is preferable to a fuse as it also
limitsinrushcurrentandprotectsagainstinputvoltagetransients
andsurges(differentialornormalmode). Lowervaluesincrease
dissipation (V2/R power term) during transients and inrush,
while higher values increase steady state dissipation (I2R) and
lower overall efficiency. Metal film types should not be used
since they do not have a high enough transient power capability
to survive line transient and inrush current and may fail
prematurely in service.
Tolerance of ungapped core permeability limits minimum gap
size for center leg gapping. For an EE13 core size, the practical
minimum center leg gap size, for an overall primary inductance
toleranceof 10%, is~0.08mm. Thisvarieswithcoresupplier,
so this should be verified before committing to a design.
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Other gapping techniques allow tighter tolerances, but may not
be universally supported, so again, this should be verified with
the preferred magnetics vendor. Film gapping, where thin
materialspacesallthreelegsofthecore,allowsbettermechanical
tolerance and improves overall primary inductance tolerance to
7% with a 0.05 mm gap. Since a gap now appears on the outer
legs of the core, flux spraying may result, causing pick up in the
input filter components and resulting in poorer than expected
conducted EMI. This can be prevented, if necessary, by adding
a single shorted turn of copper foil around the outside of the
transformer core also known as a “belly band.”
Reducing No-load Voltage with a Pre-load
At very light loads (< ~5 mA), the output voltage rises due to
secondary peak charging. This can be significantly reduced by
the addition of a small pre-load resistor. Figure 10 shows the
effect of a 1 mA and 2 mA pre-load on a 9 V output design,
reducingtheno-loadvoltageby1.3V.Thislevelofpre-loadhas
minimal effect on no-load consumption (~10 mW to 20 mW).
Minimizing No-Load Consumption
The major factors for no-load or standby consumption are PBIAS
and the capacitive switching loss PC(LOSS) (Equations 9 and 28). If
no-load consumption is too high, then the transformer may be
redesigned with a lower VOR.
Core gaps should be uniform. Uneven core gapping (see
Figure 8), especially with small gap sizes, may cause variation
in the primary inductance with flux density (partial saturation)
and make the constant current region nonlinear. To verify
uniform gapping, it is recommended that the primary switching
current waveshape be examined while feeding the supply from
a DC source. The slope is defined as di/dt = V/L and should
remain constant throughout the MOSFET on time. Any change
in slope of the current ramp is an indication of uneven gapping.
Total parasitic capacitance of device and transformer, typically
25 pF to 30 pF, causes a switching loss that increases with input
voltageandhasasignificanteffectonstandbyorno-loadoutput
power consumption.
CTOT × VM2AX × fS
(28)
P
=
C(LOSS)
Verifying Discontinuous Mode Operation
2
To verify a design will remain discontinuous conduction mode
under worst case condition use Equation 27:
VMAX is typically 340 V for universal or 230 VAC applications
and fS is 30 kHz at light or no load. Parasitic capacitance loss
PC(LOSS) is typically 40 mW to 100 mW. This loss is not included
in the LP calculation as this power is not processed through the
core.
2 × IO(MAX) × fS(MAX) × LP(MAX)
NP
<
(27)
D × (1− D) × VDC(MIN)
NS
To minimize transformer capacitance, double coated magnet
wire should be used for the primary winding. The technique of
vacuum impregnation should not be used since the varnish acts
as adielectric, increasingwindingcapacitance. Dipvarnishing
does not cause this problem.
whereIO(MAX) istheoutputcurrent(A)atmaximumCCtolerance
(typically IO(NOM) + 20%), fS(MAX) is the maximum LinkSwitch
switchingfrequency(Hz), LP(MAX) istheprimaryinductance(H)
at maximum tolerance, D is duty cycle at minimum input
voltage (typically 0.3 at 85 VAC or 0.13 at 195 VAC) and
VDC(MIN) the minimum DC voltage at lowest input line voltage
(typically 100 VDC for 85 VAC and 230 VDC for 195 VAC).
An RC snubber placed across the output diode also increases
no-load consumption. If necessary, minimize the value of the
Effect of Output Cable
15
Factors such as leakage inductance, the value for RLF, RFB and
CCLAMPhavebeencovered. However,thereareotherparameters
that should be considered when designing with LinkSwitch.
No pre-load
1 mA pre-load
2 mA pre-load
12
9
Ifthegaugeofwireselectedfortheoutputcableisreduced,then
the voltage drop across the cable resistance will increase. As
seen at the load, this appears as poorer CV operation and lower
efficiency, but with the CV/CC transition at the same output
current(seeFigure9). Ensurethatthevoltagedroporresistance
of the output cable is acceptable.
0
4
8
12
Output Current (mA)
PI-3227-082202
Figure 10. A Small Pre-load can Significantly Reduce No-load
Voltage.
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AN-35
capacitorused. Ifanultra-fastdiodehasbeenselected, tryafast
diode as this may allow the snubber to be removed.
feedback resistor RFB is split into two to form a divider which
limits the voltage across the optocoupler phototransistor. The
optocoupler therefore effectively adjusts the resistor divider
ratiotocontroltheDCvoltageacrossR2andthecurrentintothe
CONTROL pin. For an output tolerance ≤ 5%, VR1 should be
replaced by a reference IC (TL431).
Correct Oscilloscope Connection
To prevent the additional capacitance of an oscilloscope probe
from triggering the LinkSwitch current limit, do not connect the
scopegroundtotheSOURCEpin.Thescopeshouldbeconnected
as shown in Figure 11 to measure source to drain voltage. Since
the scope is referenced to the DC rail, an isolation transformer
must be used.
A full description of the operation with an optocoupler can be
found in the LinkSwitch data sheet.
Single Point Failure Testing
Improving CV Tolerance with Optocoupler
The LinkSwitch circuit requires few considerations for single
point failure testing. Breaking the feedback loop by opening
either RLF, DCLAMP or RFB results in LinkSwitch entering auto-
restart. Under this condition, the secondary output voltage will
rise but the output power is limited to ~8% of normal. This
prevents the output capacitor from failing catastrophically. If
The schematic in Figure 12 shows an example of adding a
secondary reference and optocoupler to improve CV tolerance
across the entire load range. The voltage drop (sense voltage)
across VR1, U1 and R3 sets the nominal output voltage. The
Isolation
Transformer
PI-3164-032403
Figure 11. Correct Method of Connecting an Oscilloscope to Measure Switching Waveform.
LinkSwitch
D
S
V
OUT
C
C1
R3
C2
R1
U1
R4
R
2
FB
R1 = R2 =
D1
R2
VR1
U1
C3
RTN
PI-3222-082202
Figure 12. Power Supply Outline Schematic with Optocoupler Feedback.
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AN-35
desired, a 0.5 W Zener can be added across the output to clamp
this voltage rise. The Zener voltage should be set above the
normal maximum output voltage at no-load. Short circuiting or
opening CCP safely prevents LinkSwitch operation.
Random
+ ∆I/∆V
Biases +
Random
Variable Biases Random ∆I/∆V
Primary
–
10%
2.5% 12.5%
Inductance
I2f
–
3.2%
–
6%
3%
2%
1.5%
7.5%
3%
However, on opening of CCLAMP, LinkSwitch does not enter
auto-restart. The output voltage may rise unacceptably high
underthisconditionandcausethefailureoftheoutputcapacitor.
As the supply delivers full power, output clamping requires a
Zenerpowerratingequaltoorabovethenominaloutputpower.
Input Line
–
–
CC Linearity
Tj
(25-65 C)
2%
–
–
–
1.5%
4.7%
°
Adding a second capacitor in parallel to CCLAMP prevents this
problem. When CCLAMP is open circuited the second capacitor
acts as CCLAMP. This second capacitor can be a small value
ceramic (0.01 µF) capacitor since during normal operation
CCLAMP dominates the parallel combination.
Totals
15%
19.7%
Table 1. Sources of CC Tolerance.
and biases or deterministic variations (apparent in a single unit
when tested). This distinction is made since random variations
are added using the root-sum-squares method, whereas biases
adddirectly. Afurthercolumn(∆I/∆V),applicabletotheI2fand
LP terms, contains the value including the effect of the change
inoutputcurrentwithoutputvoltage. Thisisnecessarybecause
the CV slope is nonzero. Therefore, for example, if the peak
power increases, the voltage at the new peak power point tends
to be lower, further increasing the output current.
Appendix A–LinkSwitch Tolerance
Analysis
Output Characteristic Tolerances
Boththedevicetoleranceandexternalcircuitgoverntheoverall
tolerance of the LinkSwitch power supply output characteristic.
For a typical design, the peak power point tolerances are 10%
for voltage and 20% (LNK501) / 25% (LNK500) for current
limit. This is the estimated overall variation due to LinkSwitch,
transformer tolerance and line variation in high volume
manufacturing.
The figure of 19.7% in Table 1 is the overall variation of the
CC region.
Itisimportanttonotethatthefigureof 2%forconstantcurrent
linearity (the straightness of the constant current characteristic)
is only valid for designs close to 3 W output power, with a
primary inductance of ~3 mH. This is due to the internal
compensationfordraincurrentdi/dtvariationsoverlinevoltage.
This compensation was arranged to correctly compensate, over
a line voltage range of 85 VAC to 265 VAC, with a primary
inductanceof3mH. Inlowerpowerdesigns,wheretheprimary
inductance is lower, an error results which increases the non-
linearity in the CC curve.
This appendix provides expressions to allow the calculation of
expected circuit variation when in high volume manufacturing
for a design employing a LNK501 as shown in Figure 3.
The same analysis can be extended to the LNK500. The only
significant difference is a wider I2f tolerance ( 12% compared
to 6% for LNK501) and associated increase in ∆I/∆V to 3%.
Constant Current Limit
Output diode of choice also effects CC linearity. The value in
Table 1 is based on a Schottky diode. The slower forward
recovery time of a PN diode can cause the CC characteristic to
bend outwards with falling output voltage.
Thepeakpowerpointpriortoenteringconstantcurrentoperation
isdefinedbythemaximumpowertransferredbythetransformer.
SinceLinkSwitch isdesignedtooperateindiscontinuousmode,
the power transferred is given by the expression
P = 1/2 L I2f, where L is the primary inductance, I is the primary
peak current and f is the switching frequency.
Constant Voltage Operation at Peak Power Point
During CV operation, the output characteristic is controlled by
adjusting the duty cycle, based on the voltage VFB across
capacitor CCLAMP (Figure 1). A number of parameters define the
actual output voltage, and therefore, the tolerance of the output
voltageatthepeakpowerpoint. Thekeyparameterstoconsider
are:
To simplify analysis, the data sheet parameter table specifies an
I2f coefficient. This is the product of current limit squared and
switching frequency, normalized to the feedback parameter
IDCT. This provides a single term that specifies the variation of
the peak power point in the power supply due to LinkSwitch.
Additional variations are summarized in Table 1, as both
random (unit-to-unit) or statistically independent variations
• Current variation through RFB due to line voltage variation
• CONTROL pin voltage - VC(IDCT)
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• Output diode forward voltage - VDOUT
Any change in the current through RFB, due to the tolerance of
the CONTROL pin current at 30% duty cycle, IDCT, will also
cause a change in the output voltage. The change in the voltage
across RFB (kΩ) due to the tolerance of IDCT (mA) is given by:
• Current variation through RFB due to CONTROL pin
voltage tolerance at 30% Duty Cycle (IDCT
• Feedback resistor tolerance - ∆%RFB
)
IDCT(MAX) − IDCT(MIN)
Each of the key parameters above is examined in turn.
∆VRFB(IDCT)
=
× RFB (A5)
2
The most significant variation in the output voltage is the
change with input line.
Expressed as a percentage of the voltage across VFB, the
variation is:
The voltage across RFB is defined at IDCT, corresponding to a
30% duty cycle at low line voltage. At higher line voltage, the
CONTROL pin current increases and the voltage across RFB
increases. ThechangeinvoltageacrossRFB, ∆VFB(LINE), depends
on the change in duty cycle ∆DC, the corresponding change in
CONTROL pin current ∆IC (mA) and the value RFB (kΩ). The
change in CONTROL pin current for a given change in duty
cycle can be found from a curve in the LinkSwitch data sheet.
∆VRFB(IDCT)
(A6)
∆%IDCT
=
×100%
VFB
Theoverallvariationcanthenbeestimatedusingtheexpression:
∆%CV = ∆%LINE ∆%VDOUT
∆%V2C(IDCT)
+
(A7)
∆%2IDCT + ∆%2RFB
Using the design shown in Figure 3 as an example:
6 V − 5.75 V
∆VRFB(LINE) = ∆IC × RFB
(A1)
For a universal input voltage design, ∆DC from low line to high
line is typically 0.2 (0.09 for a single input design) giving a
change in CONTROL pin current of typically 0.15 mA.
∆%VC(IDCT)
=
×100% = 0.46%
54.2 V
The value of ∆VRFB(LINE) should be expressed as a percentage of
VFB to give the variation at the power supply output. The
expression for line variation (at the peak power point) is
therefore:
(A8)
0.025 V
∆%VDOUT
=
×100% = 0.23%
2 × 5.5 V
∆VRFB(LINE)
2 × VFB
(A9)
(A2)
∆%LINE
=
×100%
∆VRFB(LINE) = 0.15 mA × 20.5 kΩ = 3.1 V
(A10)
The CONTROL pin voltage VC(IDCT) is specified at a current
equal to IDCT,giving a duty cycle of 30% for a typical design at
the peak power point, at 85 VAC input. The tolerance of this
parameter includes temperature variation and can be read from
the data sheet directly. Since the output voltage is actually
controlled using VFB, the variation of VC(IDCT) must be expressed
as a percentage of VFB. The expression for this is given by:
3.1 V
∆%LINE
=
×100% = 2.9%
2 × 54.2 V
(A11)
2.36 mA − 2.24 mA
∆VRFB(IDCT)
=
× 20.5 kΩ
2
(A12)
= 1.23 V
VC(IDCT)(MAX) − VC(IDCT)(TYP)
∆%VC(IDCT)
=
×100%
VFB
1.23 V
=
(A3)
(A13)
∆%IDCT
×100% = 2.27%
54.2 V
Anyvariationintheoutputdiodeforwarddropwithtemperature
will cause a change in the output voltage. Expressing as a
percentage of VO gives the expression:
The tolerance of R1 (RFB) is 1%.
∆VDOUT
2 × VO
(A4)
∆%VDOUT
=
×100%
∆%CV = 2.9% 0.23%
(0.462 + 2.272 +12 )
= 2.9% 0.23% 2.52%
= 5.65%
Typicalvaluesforthechangeinforwardvoltageforatemperature
change of +50 °C are +0.1 V for a silicon PN diode
and +0.025 V for Schottky diode. For device-to-device
variations, please consult diode manufacturer.
(A14)
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The overall tolerance is the sum of the deterministic variation
due to the change in line voltage and the change in the output
diode forward voltage with temperature, together with the root-
sum-square addition of the statistically independent circuit and
device variables.
Note that all of the above tolerances other than RFB and VC(IDCT)
arecompensatedoraccountedforinthepreviousanalysisofCC
tolerance. The contributions of RFB and VC(IDCT), since they are
unit-to-unit tolerances, have a very small influence (<0.1% on
the total sum of unit-to-unit tolerances).
In Equation A14 the ∆%LINE term ( 2.9%) is the expected
change in output voltage for a change of 90 VAC at 175 VAC,
the mid point of the specified input voltage range of 85 VAC to
265 VAC.
Constant Voltage Operation Below Peak Power Point
As the output load reduces from the peak power point, the
output voltage will tend to rise due to tracking errors compared
to the load terminals. Sources of these include the output cable
drop, output diode forward voltage and leakage inductance,
which is the dominant cause.
Equivalently, stating with the reference as 85 VAC, the output
voltage would increase +5.8% (twice 2.9%) when the input
increases to 265 VAC.
Astheloadreduces,theprimaryoperatingpeakcurrentreduces,
together with the leakage inductance energy, which reduces the
peak charging of CCLAMP. With a primary leakage inductance
figureof50µH, theoutputvoltagetypicallyrises40%fromfull
to no-load.
The analysis above is for a specific example, factors such as
diode choice, temperature range and output voltage can result
in a larger tolerance. However, for most cases the designer can
be confident the overall tolerance will be < 10%.
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B
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Revision
Notes
Date
8/02
4/03
–
A
B
1) Added support for LNK500
For the latest updates, visit our Web site: www.powerint.com
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any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others.
The products and applications illustrated herein (including circuits external to the products and transformer construction) may be covered by one or more U.S.
and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents
may be found at www.powerint.com.
LIFE SUPPORT POLICY
POWER INTEGRATIONS' PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS, INC. As used herein:
1. Life support devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when
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ThePIlogo, TOPSwitch, TinySwitch, LinkSwitchandEcoSmartareregisteredtrademarksofPowerIntegrations, Inc.
PI Expert and DPA-Switch are trademarks of Power Integrations, Inc. ©Copyright 2003, Power Integrations, Inc.
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