AN-05 [ETC]

SY69952 in an OC-3 Transmission System ; SY69952在OC- 3传输系统\n
AN-05
型号: AN-05
厂家: ETC    ETC
描述:

SY69952 in an OC-3 Transmission System
SY69952在OC- 3传输系统\n

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SY69952 IN AN OC-3  
TRANSMISSION SYSTEM  
APPLICATION NOTE  
AN-05  
Introduction  
General Requirements  
The SY69952 Serial Transceiver is used in SONET/SDH  
and ATM applications to recover clock and data information  
from a 155.52MHz or 51.84MHz NRZ (Non Return to Zero)  
or NRZI (Non Return to Zero Invert on ones) serial data  
stream. This device also provides a bit rate Transmit clock,  
from a byte rate source through the use of a frequency  
multiplier PLL, and differential data buffering for the Transmit  
side of the system. This device is compliant with all relevant  
SONET/SDH specifications including ANSI T1X1.6/91-022,  
ANSI T1X1.3/93-006R1 Draft and ITU/CCITT G958.  
For optimum performance of SY69952, loop filter networks  
are required. The loop filter network can be achieved using  
very few low cost external components. The purpose of the  
loop filter network is to minimize jitter characteristics of the  
device. In addition, proper power supply filtering techniques  
can also minimize jitter and matched impedance techniques  
should be used to maximize operating frequency and  
minimize wave-form distortion.  
FORMULAS FOR CALCULATION OF CONTROLLED IMPEDANCE RUNS  
Microstrip Stripline  
Ref. Plane  
(Ground)  
Dielectric  
Height H  
W
W
T
T
Dielectric  
Height H  
Ref. Plane (Ground)  
Ref. Plane  
(Ground)  
1/2  
Place Conductor  
Center at H/2  
Figure 1  
Figure 2  
Requirements: W/(H-T)<0.35 AND T/H<0.25  
60  
87  
5.98 H  
0.8 W + T  
4H  
Ln  
Ln  
0.536πW + 0.67πT  
Er + 1.41  
Er  
H is the height of the Dielectric to the Ground (Ref. Plane)  
W is the Trace Width (Design Variable)  
H is the height of the Dielectric to the Ground (Ref. Plane)  
W is the Trace Width (Design Variable)  
Er is the Dielectric Constant –  
Er is the Dielectric Constant –  
Consult with your Board Fabrication House (4.4 Typical)  
Consult with your Board Fabrication House (4.4 Typical)  
T is the thickness of the run –  
T is the thickness of the run –  
Consult with your Board Fabrication House (Typically 0.0022 with  
Plating)  
Consult with your Board Fabrication House (Typically 0.0022 with  
Plating)  
Rev.: C  
Amendment:/0  
Issue Date: June, 1998  
1
APPLICATION NOTE  
AN-05  
Micrel  
PIN DEFINITIONS  
Pin  
Pin No.  
Type  
Description  
If Unused NC or VCC. Route away from TX, & Digital Runs.(1)  
If Unused NC or VCC. Route away from TX, & Digital Runs.(1)  
Route away from TX, & Digital Runs.(1)  
ROUT+  
ROUT–  
RIN+  
RIN–  
1
2
3
4
5
6
Receive  
Receive  
Receive  
Receive  
Control  
Power  
Route away from TX, & Digital Runs.(1)  
MODE  
VCC  
No/LOW Frequency Switching.  
Isolation from system supply. Decouple with RF beads (or inductor or common mode  
chokes), NPO/COG ceramic and tantalum caps.(2)  
CD  
7
8
Control  
Control  
LOW Frequency Switching. Routing should avoid noisy areas so run is not conduit. Use  
common mode choke to isolate.(2)  
LOOP  
No/LOW Frequency Switching. Routing should avoid noisy areas so run is not a conduit.  
Use common mode choke to isolate.(2)  
REFCLK–  
REFCLK+  
TOUT–  
9
Reference  
Reference  
Transmit  
Transmit  
Transmit  
Route away from TX, & Digital Runs.(1)  
Route away from TX, & Digital Runs.(1)  
Route away from TX, & Digital Runs.(1)  
Route away from TX, & Digital Runs.(1)  
10  
11  
12  
13  
TOUT+  
PLL1+  
Place filter components next to IC. Do not route any signal near or beneath these pins or  
the TX filter connected to them. Use a ground guard around the filter components to  
collapse fields.  
PLL1–  
PLL2–  
PLL2+  
14  
15  
16  
Transmit  
Receive  
Receive  
Place filter components next to IC. Do not route any signal near or beneath these pins or  
the TX filter connected to them. Use a ground guard around the filter components to  
collapse fields.  
Place filter components next to IC. Do not route any signal near or beneath these pins or  
the TX filter connected to them. Use a ground guard around the filter components to  
collapse fields.  
Place filter components next to IC. Do not route any signal near or beneath these pins or  
the TX filter connected to them. Use a ground guard around the filter components to  
collapse fields.  
TSER–  
TSER+  
TCLK+  
TCLK–  
VCC  
17  
18  
19  
20  
21  
Transmit  
Transmit  
Transmit  
Transmit  
Power  
Route away from Receiver runs.(1)  
Route away from Receiver runs.(1)  
Route away from Receiver runs.(1)  
Route away from Receiver runs.(1)  
Isolation from system supply. Decouple with RF beads (or inductor or common mode  
chokes), NPO/COG ceramic and tant caps.(2)  
VEE (GND)  
VCC  
22  
23  
24  
Ground  
Power  
Alarm  
Tie to system ground. If the system GND is noisy then isolation from system GND with RF  
bead (or inductor or common mode choke). Ensure adequate current capacity.(2)  
Isolation from system supply. Decouple with RF beads (or inductor or common mode  
chokes), NPO/COG ceramic and tant caps.(2)  
LFI  
LOW Frequency Switching. Routing should avoid noisy areas so run is not conduit. Use  
common mode choke to isolate.(2)  
2
APPLICATION NOTE  
AN-05  
Micrel  
PIN DEFINITIONS (Continued)  
Pin  
Pin No.  
25  
Type  
Description  
Route away from TX, & Digital Runs.(1)  
RSER+  
RSER–  
RCLK+  
RCLK–  
Receive  
Receive  
Receive  
Receive  
26  
Route away from TX, & Digital Runs.(1)  
Route away from TX, & Digital Runs.(1)  
Route away from TX, & Digital Runs.(1)  
27  
28  
NOTES:  
1. a) These runs are to be held to an impedance of 50. See Microstrip or Stripline above. Parallel Termination 130/82shall be placed at their  
destinations; b) Runs must be of equal length to their corresponding differential counterpart. For example: RSER+ is equal to RSER, RCLK+ is equal  
to RCLK, etc.; c) These pairs must experience the same terrain of the PWB; d) Runs shall be constant distance to ground throughout their route. This  
will reduce crosstalk; e) Transmit runs shall be separated from receive runs.  
2. Effective use of Common Mode Chokes or RF Beads dictate the following rules: a) Single Ended Signals shall utilize one half and the other should be  
connected to Grounds. This recommendation includes VCC. For this application ensure the Choke's )or RF Bead's) Max. Impedance is below the  
Fundamental (First) Harmonic; b) Differential Signals would have the positive signal on one half and the negative signal on the other. For this application  
ensure the Choke's max. Impedance is beyond the third harmonic. Failure to do so will result in sinusoidal waveforms instead of square waveforms. RF  
Beads are NOT recommended for this application; c) Separation of Grounds would have noisy ground on both of the inputs and clean (Analog or Receive)  
Ground on both of the outputs. For this application ensure the Choke's (or RF Bead's) Max. Impedance is below the Fundamental (First) Harmonic.  
LAYOUT RECOMMENDATIONS (OPTIONAL)  
The layout in figure 3 shows a typical configuration for very dense systems. The emphasis is on the loop filters PLL1  
and PLL2 which are surrounded by a ground guard plane to reduce electromagnetic interference.  
SY69952  
Receiver Inputs  
Receiver Outputs  
to UNI  
V
CC/Control  
Alarm/VCC/Ground  
Transmit  
Outputs to Optics or  
Cable Interface  
Transmit Interface  
to UNI  
Ground  
Guard  
Transmit Filter  
(PLL1)  
Receive Filter  
(PLL2)  
Figure 3  
3
APPLICATION NOTE  
AN-05  
Micrel  
LOOP FILTER ADJUSTMENT  
This section is ONLY applicable if initial values of external  
loop filters need to be adjusted for tuning the SY69952 to a  
layout or for customer's desired jitter response. R1 and C1  
control response to Lower and Mid Range Modulation  
Frequencies. And C2 (optional) controls the the response  
to High Range Modulation Frequencies.  
C1  
C3  
R1  
Figure 4  
Transmit Filter Recommended Values:  
PLL1+, Pin 13, C1 = 0.1µF,  
Receive Filter Recommended Values:  
PLL2+, Pin 16, C1 = 0.1µF,  
PLL1, Pin 14, R1 = 500,  
PLL2, Pin 15, R1 = 120,  
Optional PLL1+ and PLL1, C2 = 47pF  
Optional PLL2+ and PLL2, C2 = 47pF  
If Jitter Amplitude response adjustment is required the  
following is an explanation of typical Loop Filter  
characteristics.  
Jitter  
Gain  
(dB)  
C2  
0.1  
R1, Then C1  
-20db/decade  
Acceptable  
Range  
-20  
130kHz  
Frequency  
Figure 5  
4
APPLICATION NOTE  
AN-05  
Micrel  
CONFIGURATION LAYOUT WITH SPLIT POWER SUPPLY  
5
APPLICATION NOTE  
AN-05  
Micrel  
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA  
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com  
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or  
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.  
© 2000 Micrel Incorporated  
6

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